SEMICONDUCTOR TECHNICAL DATA $ !$# # %# !# !$#" High-Performance Silicon-Gate CMOS The MC54/74HCT00A may be used as a level converter for interfacing TTL or NMOS outputs to high-speed CMOS inputs. The HCT00A is identical in pinout to the LS00. * * * * * * Output Drive Capability: 10 LSTTL Loads TTL/NMOS-Compatible Input Levels Outputs Directly Interface to CMOS, NMOS and TTL Operating Voltage Range: 4.5 to 5.5 V Low Input Current: 1.0 A In Compliance with the Requirements Defined by JEDEC Standard No. 7A * Chip Complexity: 48 FETs or 12 Equivalent Gates J SUFFIX CERAMIC PACKAGE CASE 632-08 14 1 N SUFFIX PLASTIC PACKAGE CASE 646-06 14 1 D SUFFIX SOIC PACKAGE CASE 751A-03 14 1 ORDERING INFORMATION MC54HCTXXAJ MC74HCTXXAN MC74HCTXXAD LOGIC DIAGRAM A1 B1 A2 B2 A3 B3 A4 B4 1 3 2 Ceramic Plastic SOIC Y1 PIN ASSIGNMENT 4 6 5 Y2 Y = AB 9 8 10 Y3 12 11 13 Y4 PIN 14 = VCC PIN 7 = GND A1 1 14 VCC B1 2 13 B4 Y1 3 12 A4 A2 4 11 Y4 B2 5 10 B3 Y2 6 9 A3 GND 7 8 Y3 FUNCTION TABLE Inputs 10/95 Motorola, Inc. 1995 1 REV 6 Output A B Y L L H H L H L H H H H L 3 IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIII III IIIIIIIIIIIIII IIIIII III IIIIIIIIIIIIIIIIIIIIIII III IIIIIIIIIIIIII IIIIII III IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIII MC54/74HCT00A MAXIMUM RATINGS* Symbol VCC Parameter DC Supply Voltage (Referenced to GND) Value Unit - 0.5 to + 7.0 V Vin DC Input Voltage (Referenced to GND) - 0.5 to VCC + 0.5 V Vout DC Output Voltage (Referenced to GND) - 0.5 to VCC + 0.5 V DC Input Current, per Pin 20 mA Iout DC Output Current, per Pin 25 mA ICC DC Supply Current, VCC and GND Pins 50 mA PD Power Dissipation in Still Air, Plastic or Ceramic DIP SOIC Package 750 500 mW Tstg Storage Temperature - 65 to + 150 _C Iin TL This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, Vin and Vout should be constrained to the range GND (Vin or Vout) VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open. v v _C Lead Temperature, 1 mm from Case for 10 Seconds SOIC or Plastic Package Ceramic Dip 260 300 * Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions. Derating -- Plastic DIP: - 10 mW/_C from 65_ to 125_C Ceramic DIP: - 10 mW/_C from 100_ to 125_C SOIC Package: - 7 mW/_C from 65_ to 125_C For high frequency or heavy load considerations, see Chapter 2 of the Motorola High-Speed CMOS Data Book (DL129/D). IIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIII 3 IIII IIII IIIIIIIIIIIIII III III III III IIIIIIII IIIIIIIII III IIIIIIIIIIII IIII IIIIIIIIIIIIII III III IIIIIIIIIIIIIII IIIIIIIIIIII III IIIIIIII IIIIIIIII III IIIII III IIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIII IIIII IIII III IIIIIIIIIIII IIIII IIIII IIII IIIIIIIIIIIIIIIIIIIIIIIIII III III III III II III IIIII IIIII IIII IIIIIIIIIIIIIIIIIIIIIIIIII III III III III v III v II IIIII IIIII IIII IIIIIIIIIIIIIIIIIIIIIIIIII IIIIII IIIIII IIIII IIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIII v IIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIII v IIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIII v IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIII v IIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIII v IIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIII IIIIIIIIIII IIIIIIIIIIIIIIIIIIII IIIIIIIIII v IIIIII IIIIIIIII IIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIII w III IIIIII IIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII RECOMMENDED OPERATING CONDITIONS Symbol Parameter VCC DC Supply Voltage (Referenced to GND) Vin, Vout Min Max Unit 2.0 6.0 V DC Input Voltage, Output Voltage (Referenced to GND) TA Operating Temperature, All Package Types tr, tf Input Rise and Fall Time (Figure 1) 0 VCC V - 55 + 125 _C 0 500 ns DC CHARACTERISTICS FOR THE MC54/74HCT00A (Voltages Referenced to GND) Guaranteed Limits Symbol Parameter Test Conditions - 55 to 25_C VCC V Min 2.00 2.00 Max 85_C Min 125_C Max VIH Minimum High-Level Input Voltage Vout = 0.1 or VCC - 0.1 V |Iout| 20 A 4.5 5.5 VIL Maximum Low-Level Input Voltage Vout = 0.1 or VCC - 0.1 V |Iout| 20 A 4.5 5.5 VOH Minimum High-Level Output Voltage Vin = VIH or VIL |Iout| 20 A 4.5 5.5 4.40 5.40 4.40 5.40 4.40 5.40 Vin = VIH or VIL |Iout| 4.0 mA 4.5 3.98 3.84 3.70 Vin = VIH or VIL |Iout| 20 A 4.5 5.5 Vin = VIH or VIL |Iout| = 4.0 mA VOL Maximum Low-Level Output Voltage 2.00 2.00 Min 0.80 0.80 0.10 0.10 Max 2.00 2.00 Unit V 0.80 0.80 0.80 0.80 V V 0.10 0.10 0.10 0.10 V 4.5 0.26 0.33 0.40 Iin Maximum Input Leakage Current Vin = VCC or GND 5.5 0.10 1.00 1.00 A ICC Maximum Quiescent Supply Current (per Package) Vin = VCC or GND |Iout| 0 A 5.5 1 10 40 A Additional Quiescent Supply Current Vin = 2.4 V, Any One Input Vin = VCC or GND, Other Inputs lout = 0 A ICC - 55_C 5.5 2.9 25 to 125_C 2.4 mA NOTE: Information on typical parametric values can be found in Chapter 2 of the Motorola High-Speed CMOS Data Book (DL129/D). MOTOROLA 2 High-Speed CMOS Logic Data DL129 -- Rev 6 IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIII IIIII IIII III IIIIIIIIIIIII IIIIII IIIII IIII IIIIIIIIIIIIIIIIIIIIIIIII III III III II III III IIIIIIIIIIIII IIIIII IIIII IIII IIIIIIIIIIIIIIIIIIIIIIIII III III II III v III vIII IIIIII IIIII IIII IIIIIIIIIIIIIIIIIIIIIIIII IIIIII IIIII IIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII MC54/74HCT00A AC CHARACTERISTICS FOR THE MC54/74HCT00A (VCC = 5.0 V 10%, CL = 50 pF, Input tr = tf = 6.0 ns) Guaranteed Limits - 55 to 25_C Symbol Parameter Fig. Min Max 85_C Min 125_C Max Min Max Unit tPLH, tPHL Maximum Propagation Delay, Input A or B to Output Y 1, 2 19 24 28 ns tTLH, tTHL Maximum Output Transition Time, Any Output 1, 2 15 19 22 ns Cin Maximum Input Capacitance -- 10 10 10 pF NOTE: For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the Motorola High- Speed CMOS Data Book (DL129/D). Typical @ 25C, VCC = 5.0 V CPD Power Dissipation Capacitance (Per Gate)* pF 15 * Used to determine the no-load dynamic power consumption: PD = CPD VCC2f + ICC VCC. For load considerations, see Chapter 2 of the Motorola High-Speed CMOS Data Book (DL129/D). tf INPUT A OR B tr TEST POINT 3.0 V 90% 1.3 V 10% OUTPUT GND tPLH DEVICE UNDER TEST tPHL 90% 1.3 V 10% OUTPUT Y tTLH 3 CL* tTHL * Includes all probe and jig capacitance Figure 1. Switching Waveforms Figure 2. Test Circuit EXPANDED LOGIC DIAGRAM (1/4 OF THE DEVICE) A Y B High-Speed CMOS Logic Data DL129 -- Rev 6 3 MOTOROLA MC54/74HCT00A OUTLINE DIMENSIONS J SUFFIX CERAMIC DIP PACKAGE CASE 632-08 ISSUE Y -A14 8 1 7 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEAD WHEN FORMED PARALLEL. 4. DIMESNION F MAY NARROW TO 0.76 (0.030) WHERE THE LEAD ENTERS THE CERAMIC BODY. -B- C -T- L DIM A B C D F G J K L M N K SEATING PLANE F G D 14 PL 0.25 (0.010) M N T A M J 14 PL 0.25 (0.010) S M T B S N SUFFIX PLASTIC DIP PACKAGE CASE 646-06 ISSUE L 14 B 7 3 A F DIM A B C D F G H J K L M N L C J N H G D SEATING PLANE K M D SUFFIX PLASTIC SOIC PACKAGE CASE 751A-03 ISSUE F -A- 14 1 P 7 PL 0.25 (0.010) 7 G D 0.25 (0.010) MOTOROLA M T F J M K 14 PL B S M R X 45 C SEATING PLANE B M A S 4 INCHES MIN MAX 0.715 0.770 0.240 0.260 0.145 0.185 0.015 0.021 0.040 0.070 0.100 BSC 0.052 0.095 0.008 0.015 0.115 0.135 0.300 BSC 0_ 10_ 0.015 0.039 MILLIMETERS MIN MAX 18.16 19.56 6.10 6.60 3.69 4.69 0.38 0.53 1.02 1.78 2.54 BSC 1.32 2.41 0.20 0.38 2.92 3.43 7.62 BSC 0_ 10_ 0.39 1.01 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. 8 -B- MILLIMETERS MIN MAX 19.05 19.94 6.23 7.11 3.94 5.08 0.39 0.50 1.40 1.65 2.54 BSC 0.21 0.38 3.18 4.31 7.62 BSC 0 15 0.51 1.01 NOTES: 1. LEADS WITHIN 0.13 (0.005) RADIUS OF TRUE POSITION AT SEATING PLANE AT MAXIMUM MATERIAL CONDITION. 2. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 3. DIMENSION B DOES NOT INCLUDE MOLD FLASH. 4. ROUNDED CORNERS OPTIONAL. 8 1 INCHES MIN MAX 0.750 0.785 0.245 0.280 0.155 0.200 0.015 0.020 0.055 0.065 0.100 BSC 0.008 0.015 0.125 0.170 0.300 BSC 0 15 0.020 0.040 DIM A B C D F G J K M P R MILLIMETERS MIN MAX 8.75 8.55 4.00 3.80 1.75 1.35 0.49 0.35 1.25 0.40 1.27 BSC 0.25 0.19 0.25 0.10 7 0 5.80 6.20 0.25 0.50 INCHES MIN MAX 0.337 0.344 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 7 0 0.228 0.244 0.010 0.019 High-Speed CMOS Logic Data DL129 -- Rev 6 MC54/74HCT00A 3 Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. 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Box 20912; Phoenix, Arizona 85036. 1-800-441-2447 JAPAN: Nippon Motorola Ltd.; Tatsumi-SPD-JLDC, Toshikatsu Otsuki, 6F Seibu-Butsuryu-Center, 3-14-2 Tatsumi Koto-Ku, Tokyo 135, Japan. 03-3521-8315 MFAX: RMFAX0@email.sps.mot.com -TOUCHTONE (602) 244-6609 INTERNET: http://Design-NET.com HONG KONG: Motorola Semiconductors H.K. Ltd.; 8B Tai Ping Industrial Park, 51 Ting Kok Road, Tai Po, N.T., Hong Kong. 852-26629298 High-Speed CMOS Logic Data DL129 -- Rev 6 CODELINE 5 *MC54/74HCT00A/D* MC54/74HCT00A/D MOTOROLA