MC74HCT74AD - Motorola / Freescale Semiconductor



SEMICONDUCTOR TECHNICAL DATA

1REV 6

 Motorola, Inc. 1995

10/95

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 !# !$#"

High–Performance Silicon–Gate CMOS

The MC54/74HCT00A may be used as a level converter for interfacing

TTL or NMOS outputs to high–speed CMOS inputs.

The HCT00A is identical in pinout to the LS00.

•Output Drive Capability: 10 LSTTL Loads

•TTL/NMOS–Compatible Input Levels

•Outputs Directly Interface to CMOS, NMOS and TTL

•Operating Voltage Range: 4.5 to 5.5 V

•Low Input Current: 1.0 µA

•In Compliance with the Requirements Defined by JEDEC Standard

No. 7A

•Chip Complexity: 48 FETs or 12 Equivalent Gates

LOGIC DIAGRAM

3Y1

PIN 14 = VCC

PIN 7 = GND

Y = AB

6Y2

A2 5

8Y3

A3 10

A4 13



FUNCTION TABLE

PIN ASSIGNMENT

105

VCC

GND

Inputs

Output

D SUFFIX

SOIC PACKAGE

CASE 751A–03

N SUFFIX

PLASTIC PACKAGE

CASE 646–06

ORDERING INFORMATION

MC54HCTXXAJ

MC74HCTXXAN

MC74HCTXXAD

Ceramic

Plastic

SOIC

J SUFFIX

CERAMIC PACKAGE

CASE 632–08

MC54/74HCT00A

MOTOROLA High–Speed CMOS Logic Data

DL129 — Rev 6

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

MAXIMUM RATINGS*

ÎÎÎ

Symbol

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Parameter

ÎÎÎÎÎÎ

Value

ÎÎÎ

Unit

ÎÎÎ

VCC

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

DC Supply Voltage (Referenced to GND)

ÎÎÎÎÎÎ

– 0.5 to + 7.0

ÎÎÎ

Vin

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

DC Input Voltage (Referenced to GND)

ÎÎÎÎÎÎ

– 0.5 to VCC + 0.5

ÎÎÎ

Vout

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

DC Output Voltage (Referenced to GND)

ÎÎÎÎÎÎ

– 0.5 to VCC + 0.5

ÎÎÎ

Iin

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

DC Input Current, per Pin

ÎÎÎÎÎÎ

± 20

ÎÎÎ

Iout

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

DC Output Current, per Pin

ÎÎÎÎÎÎ

± 25

ÎÎÎ

ICC

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

DC Supply Current, VCC and GND Pins

ÎÎÎÎÎÎ

± 50

ÎÎÎ

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Power Dissipation in Still Air,Plastic or Ceramic DIP†

SOIC Package†

ÎÎÎÎÎÎ

750

500

ÎÎÎ

Tstg

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Storage Temperature

ÎÎÎÎÎÎ

– 65 to + 150

ÎÎÎ

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Lead Temperature, 1 mm from Case for 10 Seconds

SOIC or Plastic Package

Ceramic Dip

ÎÎÎÎÎÎ

260

300

ÎÎÎ

*Maximum Ratings are those values beyond which damage to the device may occur.

Functional operation should be restricted to the Recommended Operating Conditions.

†Derating — Plastic DIP: – 10 mW/

C from 65

to 125

Ceramic DIP: – 10 mW/

C from 100

to 125

SOIC Package: – 7 mW/

C from 65

to 125

For high frequency or heavy load considerations, see Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).

RECOMMENDED OPERATING CONDITIONS

ÎÎÎÎ

Symbol

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Parameter

ÎÎÎ

Min

ÎÎÎ

Max

ÎÎÎ

Unit

ÎÎÎÎ

VCC

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

DC Supply Voltage (Referenced to GND)

ÎÎÎ

2.0

ÎÎÎ

6.0

ÎÎÎ

ÎÎÎÎ

Vin, Vout

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

DC Input Voltage, Output Voltage (Referenced to GND)

ÎÎÎ

VCC

ÎÎÎ

ÎÎÎÎ

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Operating Temperature, All Package Types

ÎÎÎ

– 55

ÎÎÎ

+ 125

ÎÎÎ

ÎÎÎÎ

tr, tf

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Input Rise and Fall Time (Figure 1)

ÎÎÎ

500

ÎÎÎ

DC CHARACTERISTICS FOR THE MC54/74HCT00A (Voltages Referenced to GND)

ÎÎÎ

ÎÎÎÎÎÎÎÎ

ÎÎÎÎÎÎÎÎÎ

ÎÎÎ

ÎÎÎÎÎÎÎÎÎÎÎÎ

Guaranteed Limits

ÎÎÎ

Symbol

ÎÎÎÎÎÎÎÎ

Parameter

ÎÎÎÎÎÎÎÎÎ

Test Conditions

ÎÎÎ

VCC

ÎÎÎÎÎ

– 55 to

ÎÎÎÎÎ

ÎÎÎÎ

125

ÎÎÎ

Unit

ÎÎÎ

Symbol

ÎÎÎÎÎÎÎÎ

Parameter

ÎÎÎÎÎÎÎÎÎ

Test Conditions

ÎÎÎ

VCC

ÎÎÎ

Min

ÎÎÎ

Max

ÎÎÎ

Min

ÎÎÎ

Max

ÎÎÎ

Min

ÎÎ

Max

ÎÎÎ

Unit

ÎÎÎ

VIH

ÎÎÎÎÎÎÎÎ

Minimum High–Level

Input Voltage

ÎÎÎÎÎÎÎÎÎ

Vout = 0.1 or VCC – 0.1 V

|Iout|

20 µA

ÎÎÎ

4.5

5.5

ÎÎÎ

2.00

ÎÎÎ

2.00

ÎÎÎ

2.00

ÎÎ

ÎÎÎ

VIL

ÎÎÎÎÎÎÎÎ

Maximum Low–Level

Input Voltage

ÎÎÎÎÎÎÎÎÎ

Vout = 0.1 or VCC – 0.1 V

|Iout|

20 µA

ÎÎÎ

4.5

5.5

ÎÎÎ

0.80

ÎÎÎ

0.80

ÎÎÎ

ÎÎ

0.80

ÎÎÎ

VOH

ÎÎÎÎÎÎÎÎ

Minimum High–Level

Output Voltage

ÎÎÎÎÎÎÎÎÎ

Vin = VIH or VIL

|Iout|

20 µA

ÎÎÎ

4.5

5.5

ÎÎÎ

4.40

5.40

ÎÎÎ

4.40

5.40

ÎÎÎ

4.40

5.40

ÎÎ

ÎÎÎ

ÎÎÎÎÎÎÎÎ

ÎÎÎÎÎÎÎÎÎ

Vin = VIH or VIL

|Iout|

4.0 mA

ÎÎÎ

4.5

ÎÎÎ

3.98

ÎÎÎ

3.84

ÎÎÎ

3.70

ÎÎ

ÎÎÎ

VOL

ÎÎÎÎÎÎÎÎ

Maximum Low–Level

Output Voltage

ÎÎÎÎÎÎÎÎÎ

Vin = VIH or VIL

|Iout|

20 µA

ÎÎÎ

4.5

5.5

ÎÎÎ

0.10

ÎÎÎ

0.10

ÎÎÎ

ÎÎ

0.10

ÎÎÎ

ÎÎÎÎÎÎÎÎ

ÎÎÎÎÎÎÎÎÎ

Vin = VIH or VIL

|Iout| = 4.0 mA

ÎÎÎ

4.5

ÎÎÎ

0.26

ÎÎÎ

0.33

ÎÎÎ

ÎÎ

0.40

ÎÎÎ

Iin

ÎÎÎÎÎÎÎÎ

Maximum Input Leakage

Current

ÎÎÎÎÎÎÎÎÎ

Vin = VCC or GND

ÎÎÎ

5.5

ÎÎÎ

±0.10

ÎÎÎ

±1.00

ÎÎÎ

ÎÎ

±1.00

ÎÎÎ

µA

ÎÎÎ

ICC

ÎÎÎÎÎÎÎÎ

Maximum Quiescent Sup-

ply Current (per Package)

ÎÎÎÎÎÎÎÎÎ

Vin = VCC or GND

|Iout|

0 µA

ÎÎÎ

5.5

ÎÎÎ

ÎÎ

ÎÎÎ

µA

ÎÎÎ

∆ICC

ÎÎÎÎÎÎÎÎ

Additional Quiescent

Supply Current

ÎÎÎÎÎÎÎÎÎ

Vin = 2.4 V, Any One Input

Vin = VCC or GND, Other Inputs

lout = 0 µA

ÎÎÎ

5.5

ÎÎÎÎÎÎÎ

– 55

ÎÎÎÎÎÎ

25 to 125

ÎÎÎ

ÎÎÎÎÎÎÎÎ

Supply Current

ÎÎÎÎÎÎÎÎÎ

Vin = VCC or GND, Other Inputs

lout = 0 µA

ÎÎÎ

5.5

ÎÎÎÎÎÎÎ

2.9

ÎÎÎÎÎÎ

2.4

ÎÎÎ

NOTE: Information on typical parametric values can be found in Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).

This device contains protection

circuitry to guard against damage

due to high static voltages or electric

fields. However, precautions must

be taken to avoid applications of any

voltage higher than maximum rated

voltages to this high–impedance cir-

cuit. For proper operation, Vin and

Vout should be constrained to the

range GND

(Vin or V out)

VCC.

Unused inputs must always be

tied to an appropriate logic voltage

level (e.g., either GND or VCC).

Unused outputs must be left open.

MC54/74HCT00A

High–Speed CMOS Logic Data

DL129 — Rev 6 3 MOTOROLA

AC CHARACTERISTICS FOR THE MC54/74HCT00A (VCC = 5.0 V ± 10%, CL = 50 pF, Input tr = tf = 6.0 ns)

ÎÎÎÎ

Symbol

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Parameter

ÎÎÎ

Fig.

ÎÎÎÎÎÎÎÎÎÎÎÎÎ

Guaranteed Limits

ÎÎÎ

Unit

ÎÎÎÎ

Symbol

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Parameter

ÎÎÎ

Fig.

ÎÎÎÎÎÎ

– 55 to 25

ÎÎÎÎÎ

ÎÎÎÎ

125

ÎÎÎ

Unit

ÎÎÎÎ

Symbol

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Parameter

ÎÎÎ

Fig.

ÎÎÎÎ

Min

ÎÎÎ

Max

ÎÎÎ

Min

ÎÎÎ

Max

ÎÎ

Min

ÎÎÎ

Max

ÎÎÎ

Unit

ÎÎÎÎ

tPLH,

tPHL

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Maximum Propagation Delay, Input A

or B to Output Y

ÎÎÎ

1, 2

ÎÎÎÎ

ÎÎÎ

ÎÎ

ÎÎÎ

ÎÎÎÎ

tTLH,

tTHL

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Maximum Output Transition

Time, Any Output

ÎÎÎ

1, 2

ÎÎÎÎ

ÎÎÎ

ÎÎ

ÎÎÎ

ÎÎÎÎ

Cin

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Maximum Input Capacitance

ÎÎÎ

—

ÎÎÎÎ

ÎÎÎ

ÎÎ

ÎÎÎ

NOTE:For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the Motorola High–

Speed CMOS Data Book (DL129/D).

CPD

Power Dissipation Capacitance (Per Gate)*

Typical @ 25°C, VCC = 5.0 V

CPD Power Dissipation Capacitance (Per Gate)*

*Used to determine the no–load dynamic power consumption: PD = CPD VCC2f + ICC VCC. For load considerations, see Chapter 2 of the

Motorola High–Speed CMOS Data Book (DL129/D).

Figure 1. Switching Waveforms

tftr3.0 V

GND

90%

1.3 V

10%

90%

1.3 V

10%

INPUT

A OR B

OUTPUT Y

tPHL

tPLH

tTLH tTHL

*Includes all probe and jig capacitance

Figure 2. Test Circuit

CL*

TEST POINT

DEVICE

UNDER

TEST

OUTPUT

EXPANDED LOGIC DIAGRAM

(1/4 OF THE DEVICE)

MC54/74HCT00A

MOTOROLA High–Speed CMOS Logic Data

DL129 — Rev 6

OUTLINE DIMENSIONS

J SUFFIX

CERAMIC DIP PACKAGE

CASE 632–08

ISSUE Y

MIN MINMAX MAX

INCHES MILLIMETERS

DIM

0.785

0.280

0.200

0.020

0.065

0.015

0.170

0.040

0.750

0.245

0.155

0.015

0.055

0.008

0.125

0.020

19.94

7.11

5.08

0.50

1.65

0.38

4.31

1.01

19.05

6.23

3.94

0.39

1.40

0.21

3.18

0.51

0.100 BSC

0.300 BSC

2.54 BSC

7.62 BSC

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI

Y14.5M, 1982.

2. CONTROLLING DIMENSION: INCH.

3. DIMENSION L TO CENTER OF LEAD WHEN

FORMED PARALLEL.

4. DIMESNION F MAY NARROW TO 0.76 (0.030)

WHERE THE LEAD ENTERS THE CERAMIC

BODY.

14 8

1 7

-A-

-B-

-T-

SEATING

PLANE

F G N

0.25 (0.010) T A

MS0.25 (0.010) T B

J 14 PL

D 14 PL

N SUFFIX

PLASTIC DIP PACKAGE

CASE 646–06

ISSUE L

NOTES:

1. LEADS WITHIN 0.13 (0.005) RADIUS OF TRUE

POSITION AT SEATING PLANE AT MAXIMUM

MATERIAL CONDITION.

2. DIMENSION L TO CENTER OF LEADS WHEN

FORMED PARALLEL.

3. DIMENSION B DOES NOT INCLUDE MOLD

FLASH.

4. ROUNDED CORNERS OPTIONAL.

1 7

14 8

H G D K

SEATING

PLANE

DIM MIN MAX MIN MAX

MILLIMETERSINCHES

A0.715 0.770 18.16 19.56

B0.240 0.260 6.10 6.60

C0.145 0.185 3.69 4.69

D0.015 0.021 0.38 0.53

F0.040 0.070 1.02 1.78

G0.100 BSC 2.54 BSC

H0.052 0.095 1.32 2.41

J0.008 0.015 0.20 0.38

K0.115 0.135 2.92 3.43

L0.300 BSC 7.62 BSC

M0 10 0 10

N0.015 0.039 0.39 1.01

_ _ _ _

D SUFFIX

PLASTIC SOIC PACKAGE

CASE 751A–03

ISSUE F

MIN MINMAX MAX

MILLIMETERS INCHES

DIM

8.55

3.80

1.35

0.35

0.40

0.19

0.10

5.80

0.25

8.75

4.00

1.75

0.49

1.25

0.25

6.20

0.50

0.337

0.150

0.054

0.014

0.016

0.008

0.004

0.228

0.010

0.344

0.157

0.068

0.019

0.049

0.009

0.244

0.019

1.27 BSC 0.050 BSC

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI

Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSIONS A AND B DO NOT INCLUDE

MOLD PROTRUSION.

4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)

PER SIDE.

5. DIMENSION D DOES NOT INCLUDE DAMBAR

PROTRUSION. ALLOWABLE DAMBAR

PROTRUSION SHALL BE 0.127 (0.005) TOTAL

IN EXCESS OF THE D DIMENSION AT

MAXIMUM MATERIAL CONDITION.

–A–

–B– P 7 PL

SEATING

PLANE

D 14 PL MJ

R X 45°

814

0.25 (0.010) T B A

MS S

B0.25 (0.010) M M

MC54/74HCT00A

High–Speed CMOS Logic Data

DL129 — Rev 6 5 MOTOROLA

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the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit,

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applications. All operating parameters, including “T ypicals” must be validated for each customer application by customer’s technical experts. Motorola does

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MC54/74HCT00A/D

*MC54/74HCT00A/D*

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