LT3710
1
3710f
The LT
®
3710 is a high efficiency step-down switching
regulator intended for auxiliary outputs in single second-
ary winding, multiple output power supplies.
The LT3710 drives dual synchronous N-channel MOSFETs
and achieves high efficiency. With leading edge modula-
tion, it operates well with either primary side peak current
or voltage mode control. It is synchronized to the falling
edge of the transformer secondary winding and can be
used in both single-ended and double-ended isolated
power converter topologies. A high speed operational
amplifier is incorporated to achieve optimum compensa-
tion and fast transient response. A user selectable discon-
tinuous conduction mode improves light load efficiency.
The LT3710 is available in a thermally enhanced TSSOP-16
exposed pad power package.
■
48V Isolated DC/DC Converters
■
Multiple Output Supplies
■
Offline Converters
, LTC and LT are registered trademarks of Linear Technology Corporation.
■
Generates a Regulated Auxiliary Output in Isolated
DC/DC Converters
■
0.8V ±1.5% Accurate Voltage Reference
■
Dual N-Channel MOSFET Synchronous Drivers
■
High Switching Frequency: Up to 500kHz
■
Programmable Current Limit Protection
■
Programmable Soft-Start
■
Automatic Frequency Synchronization
■
Small 16-Pin Thermally Enhanced TSSOP Package
Figure 1. Simplified Single Secondary Winding 3.3V and 1.8V Output Isolated DC/DC Converter
DESCRIPTIO
U
FEATURES
APPLICATIO S
U
TYPICAL APPLICATIO
U
Secondary Side
Synchronous Post Regulator
VCOMP
VDD
LTC1698
GND
VFB
CG
FG
ISNS
SYNC
OPTODRV
VCC
BIAS
L1 VOUT1
3.3V
AT 10A
BG
LT3781
SG
ISOLATION
BOUNDARY
COUT2: POSCAP, 680µF/4V
L2: SUMIDA CEP125-IR8MC-H
Q1, Q2: SILICONIX Si7440DP
PLEASE REFER TO FIGURE 3
IN THE APPLICATIONS SECTION
FOR THE COMPLETE SCHEMATIC
3710 F01
VIN
36V
TO 72V
VREF
VCVFB
TG ••
GBIAS
4.7µF
CMDSH-3
Q1
Q2 B340A
3.01k
2.32k
L2
1.8µH0.006Ω
VCC BOOST
CL–CL+
LT3710
SYNC
TG
CSET
ILCOMP
SS
••
–
+
0.1µF
3.3k
33nF
10pF
CS
680pF
10k
10k
180pF
0.01µFBGS
PGND
SW
BG
VAOUT
VFB
4700pF
VOUT2
1.8V
AT 10A
COUT2
+
220Ω
LT3710
2
3710f
V
CC
Supply Voltage.................................................. 26V
BOOST Pin Voltage With Respect to SW pin ........... 10V
BOOST Pin Voltage With Respect to GND pin.......... 35V
SYNC Pin Voltage .................................................... 30V
Operating Junction Temperature Range
(Notes 2, 3) ...................................... –40°C to 125°C
Storage Temperature Range ................. –65°C to 150°C
Lead Temperature (Soldering, 10 sec)..................300°C
Note: If higher than 30V on SYNC pin is needed, add a 10k resistor in series with the pin.
ORDER PART
NUMBER
T
JMAX
= 125°C, θ
JA
= 38°C/W
EXPOSED PAD IS SGND (PIN 17) MUST BE
CONNECTED TO PGND AND SOLDERED TO PCB
Consult LTC Marketing for parts specified with wider operating temperature ranges.
LT3710EFE
ABSOLUTE AXI U RATI GS
W
WW
U
PACKAGE/ORDER I FOR ATIO
UUW
(Note 1)
ELECTRICAL CHARACTERISTICS
The ● denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VCC = 11V, operating maximum VCC = 24V, no load on any outputs
unless otherwise noted.
1
2
3
4
5
6
7
8
TOP VIEW
FE PACKAGE
16-LEAD PLASTIC TSSOP
16
15
14
13
12
11
10
9
BOOST
TGATE
SW
CSET
SYNC
ILCOMP
SS
VFB
GBIAS
BGATE
PGND
VCC
CL–
CL+
VAOUT
BGS
17
PARAMETER CONDITIONS MIN TYP MAX UNITS
Overall
Supply Voltage (V
CC
)●824V
Supply Current (I
VCC
) VA
OUT
≤ 1.2V (Switching Off) 7 12 mA
Boost Pin Current V
BOOST
= V
SW
+ 8V, 0V ≤ V
SW
≤ 24V
TGATE High 2 3 mA
TGATE Low 2 3 mA
Voltage Amplifier VA
Reference Voltage (V
REF
)0.788 0.8 0.812 V
●0.780 0.820 V
FB Pin Input Current V
FB
= V
REF
0.2 0.5 µA
VA
OUT
High 4.5 V
VA
OUT
Low 0.8 V
VA
OUT
Source Current ●100 300 µA
Open-Loop Gain 100 dB
Gain Bandwidth Product 10 MHz
Soft-Start Current 51218 µA
Current Limit Amplifier CA1
Current Limit Threshold at (V
CL+
– V
CL–
) Common Mode Voltage from 0V to V
CC
– 2.5V ●50 70 85 mV
BGATE Off Threshold at (V
CL+
– V
CL–
), BGS Pin Float Common Mode Voltage from 0V to V
CC
– 2.5V 0 8 15 mV
Switching Off Threshold at ILCOMP V
ILCOMP
0.15 V
Input Current (CL
+
, CL
–
)V
CL+
= V
CL–
100 µA
FE PART
MARKING
3710EFE
LT3710
3
3710f
Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
Note 2: The LT3710E is guaranteed to meet performance specifications
from 0°C to 125°C. Specifications over the –40°C to 125°C operating
temperature range are assured by design, characterization and correlation
with statistical process controls.
PARAMETER CONDITIONS MIN TYP MAX UNITS
ELECTRICAL CHARACTERISTICS
The ● denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VCC = 11V, operating maximum VCC = 24V, no load on any outputs
unless otherwise noted.
Oscillator
Switching Frequency C
S
= 500pF (No SYNC) ●170 200 240 kHz
C
S
= 333pF (No SYNC) ●240 280 340 kHz
Synchronization Frequency Range C
S
= 500pF ●245 400 kHz
C
S
= 333pF ●345 500 kHz
CSET Ramp Valley Voltage C
S
= 1000pF (No SYNC) 0.90 1.15 1.4 V
CSET Peak-to-Peak Voltage C
S
= 1000pF (No SYNC) 2.4 V
Synchronization Pulse Threshold on SYNC Pin Falling Edge V
SYNC
2.5 V
Maximum Duty Cycle V
FB
= V
REF
– 5mV, C
S
> 500pF ●85 90 %
Gate Drivers (TGATE, BGATE)
V
GBIAS
I
GBIAS
< 25mA ●7.5 8.0 8.5 V
V
TGATE
High (V
TGATE
– V
SW
)I
TGATE
< 50mA, V
BOOST
= V
GBIAS
– 0.5V ●567 V
V
BGATE
High I
BGATE
< 50mA ●5 6 7.5 V
V
TGATE
Low (V
TGATE
– V
SW
)I
TGATE
< –50mA ●0.5 V
V
BGATE
Low I
BGATE
< –50mA ●0.5 V
Peak Gate Drive Current 10nF Load 1 A
Gate Drive Rise and Fall Time 1nF Load 25 ns
TYPICAL PERFOR A CE CHARACTERISTICS
UW
I
GBIAS
(mA)
0
V
GBIAS
(V)
8.1
8.0
7.9
7.8
7.7
3710 G01
10 20 26
–40°C
25°C
125°C
V
CC
(V)
8 1012141618202224
I
CC
(mA)
13
12
11
10
9
8
7
6
5
3710 G02
T
A
= 25°C
FREQUENCY (Hz)
10
GAIN (dB)
120
80
40
0
–20
PHASE (DEG)
–0
–50
–100
–150
–180
3710 G03
PHASE
0dB, 10MHz
(–111°)
GAIN
100 1k 10k 100k 1M 10M 100M
TA = 25°C
VGBIAS vs IGBIAS over Junction
Temperature ICC vs VCC (Switching Off) Voltage Amplifier VA Gain and
Phase
Note 3: This IC includes overtemperature protection that is intended to
protect the device during momentary overload conditions. Junction
temperature will exceed 125°C when overtemperature protection is active.
Continuous operation above the specified maximum operating junction
temperature may impair device reliability.
LT3710
4
3710f
TYPICAL PERFOR A CE CHARACTERISTICS
UW
V
CC
(V)
10 15 20 25
∆V
REF
(mV)
3
2
1
0
–1
∆FREQ (kHz)
1
0
–1
3710 G04
∆V
REF
CSET = 500pF
T
A
= 25°C
∆FREQ
JUNCTION TEMPERATURE (°C)
–20–40 2507550 125
V
REF
(V)
0.801
0.800
0.799
0.798
3710 G05
CSET = 500pF
CSET (pF)
400200 600 800 1000
FREQUENCY (kHz)
500
400
300
200
100
MAXIMUM DUTY CYCLE
1.00
0.95
0.90
0.85
0.80
0.75
0.70
3710 G07
MAXIMUM DUTY CYCLE
CSET
T
A
= 25°C
TIME
0
I
GBIAS
(mA)
300
250
200
150
100
50
0
V
GBIAS
(V)
12
10
8
6
4
2
0
500µs
3710 G08
1ms
V
GBIAS
C
GBIAS
= 2.2µF
I
GBIAS
V
CL+
– V
CL–
(mV)
6050 70 80 90
VA
OUT
(V)
8
7
6
5
4
3
2
1
0
3710 G09
CSET PEAK
V
CC
= 11V
V
CLN
= 5V
T
A
= 25°C
CSET VALLEY
∆VREF vs VCC, ∆FREQ vs VCC VREF vs Temperature
CSET vs Switching Frequency
GBIAS vs IGBIAS (Charging 2.2µF) Current Limit Amplifier CA1 Gain
at VCC = 11V, VCL– = 5V
JUNCTION TEMPERATURE (°C)
–20–40 2507550 125
SWITCHING FREQUENCY (kHz)
195
200
205
210
215
3710 G06
CSET = 500pF
Frequency vs Temperature
LT3710
5
3710f
BOOST (Pin 1): Topside (Boosted) Driver Supply. This pin
is used to bootstrap and supply the topside power switch
gate drive circuitry. In normal operation V
BOOST
is powered
from the internally generated 8V GBIAS, V
BOOST
= V
SW
+
8.2V when TGATE is on.
TGATE (Pin 2): Topside (Boosted) N-Channel MOSFET
Driver. When TGATE is on, the voltage is equal to V
SW
+ 6V.
SW (Pin 3): Switch Node Connection to Inductor.
CSET (Pin 4): Oscillator Timing Pin. The capacitor on this
pin sets the PWM switching frequency.
SYNC (Pin 5): Synchronization Input. This pin should be
connected to the secondary side output of the power
transformer with a series resistor. A filtering capacitor of
10pF is recommended.
ILCOMP (Pin 6): Current Limit Amplifier Compensation
Node. At current limit, CA1 pulls down on this pin to
regulate the output current.
SS (Pin 7): Soft-Start. A capacitor on this pin sets the
output ramp up rate. The typical time for SS to reach the
programmed level is (C • 0.8V)/10µA.
V
FB
(Pin 8): Voltage Amplifier Inverting Input. A resistor
divider to this pin sets the output voltage. Nominal voltage
at this pin is 0.8V.
PI FU CTIO S
UUU
BGS (Pin 9): Bottom Gate Switching Control. CA2 moni-
tors the inductor current and prohibits BGATE from turn-
ing on when the inductor current is low (below 8mV across
the current sense resistor RS1) to allow discontinous
mode operation. Grounding this pin disables comparator
CA2.
VA
OUT
(Pin 10): Voltage Amplifier Output.
CL
+
(Pin 11): Current Limit Amplifier Positive Input. The
threshold is set at 70mV.
CL
–
(Pin 12): Current Limit Amplifier Negative Input.
When used, CL
–
is connected to the output capacitor side
of the current + sense resistor and CL
+
is connected to the
inductor side of the current sense resistor.
V
CC
(Pin 13): Supply of the IC. For proper bypassing, a low
ESR capacitor is required.
PGND (Pin 14): Ground of the Bottom Side N-Channel
MOSFET Driver.
BGATE (Pin 15): Bottom Side N-Channel MOSFET Driver.
GBIAS (Pin 16): 8V Regulator Output for Boostrapping
V
BOOST
.
A bypass capacitor of at least 2µF is needed.
Exposed Pad (Pin 17): Connect to PGND (Pin 14).
LT3710
6
3710f
–
+
A11
A6
A2
SS
SW
1.6V
+
8mV
+
+
–
A10
+
–
PWM
3.5V
+
+
–
2.5V
+
70mV
–
+
A8
7V
+
8V
+
+
–
VA
+
–
CA1
A5
+
–
A3
BGATE
2.5V
+
A4
A1
TGATE
2
SW
3
GBIAS
C3
2µF
D3
16
BOOST
1
R1
BGATE
15
PGND
14
BGS
9
R2
2V
M1
L1
IL
RS1
M2
C2
0.3µF
CL+
11
CL–
12
VAOUT
10
VFB
8
SYNC 5
CSET 4
7
R3
R4
C4
2nF
R5
2k
C1
500pF
COUT
100µF
VOUT2
D6
D4
I1
10µA
5V
D7 VREF
0.8V
C7
5nF
SS
C5
500pF
NOTE: EXPOSED PAD (PIN 17) IS SGND
AND MUST BE CONNECTED TO PGND (PIN 14).
SGND
CS
10pF
C8
2µF
R8
R7
VS
A7
E4
+
–
8V
+
VCC 13
ONE
SHOT OSC
RS
RESET
+
–
CA2
ILCOMP
6R6
5k
C6
100pF
3710 BD
+
D5
D2
Q1
I2
200µA
E2 SHUTDOWN
RS
10k
D1
IO
17
BLOCK DIAGRA
W
LT3710
7
3710f
APPLICATIO S I FOR ATIO
WUUU
TRANSFORMER
SECONDARY VOLTAGE
SYNC SIGNAL V
RESET
RAMP V
CSET
SWITCH NODE V
SW
3710 F02
VA
OUT
TGATE
BGATE
I
L
D
1
T
V
SP
V
S
V
RESET
T
D
2
TV
SP
T
Figure 2. Leading Edge Modulation,
Trailing Edge Synchronization
OPERATIO
U
Synchronization and Oscillation Frequency Setting
The switching is synchronized to the secondary winding
falling edge and the synchronization threshold is typically
2.5V. The synchronization falling edge triggers an internal
inverted ramp (see Figure 2) and starts a new switching
cycle for the leading edge voltage mode PWM. The reason
for using leading edge modulation is to keep the trans-
former primary side peak current sensing undisturbed.
For proper synchronization, the oscillator frequency should
be set lower than the system switching frequency with
tolerances taken into account.
To generate isolated multiple outputs, most systems use
either multiple secondary windings or cascade regulators
for each additional output. Multiple secondary windings
sacrifice regulation of the auxiliary outputs. Cascaded
regulators require a larger inductor for the main output,
because all of the power is processed in series.
By generating the auxiliary output(s) from the secondary
winding of the main output, the LT3710 allows for parallel
processing of the output power. This minimizes the main
output inductor size and directly regulates the auxiliary
output. With synchronous rectification, the system effi-
ciency is greatly improved.
Refering to the Block Diagram, the LT3710 basic functions
include a voltage amplifier, VA, to regulate the output
voltage to within typically 1.5%, a voltage mode PWM with
trailing edge synchronization and leading edge modula-
tion, a current limit amplifier, CA1, and high speed syn-
chronous switch drivers.
During normal operation (see Figure 2), a switching cycle
begins at the falling edge of the transformer secondary
voltage V
S
. The internal oscillator is reset, turning off the
top MOSFET M1 and turning on the bottom MOSFET M2.
During this portion of the cycle, the inductor current is
discharged by the output voltage V
OUT2
. The transformer
secondary voltage V
S
will go high during this portion of the
cycle. Since M1 is off, the switch node voltage V
SW
remains zero. The inductor current continues to be dis-
charged by the output voltage V
OUT2
. This condition lasts
f
OSC
< (f
SL
• 0.8)
f
SL
is the low limit of the system switching frequency and
0.8 is the tolerance of f
OSC
.
For example, a system of 200KHz with 15% tolerance,
then f
SL
= 200k • 85% = 170kHz; and f
OSC
< (170k • 0.8),
f
OSC
should be set below 136kHz.
Once f
OSC
is determined, CSET can be calculated by
CSET = (107250pf/f
OSC(kHz)
) – 50pF.
For f
OSC
= 100kHz, CSET = 1022.5pF.
until the ramp signal intersects the feedback error ampli-
fier output VA
OUT
. The top MOSFET M1 turns on, pulling
the switch node voltage to V
S
. The inductor current of the
LT3710 circuit is then charged by V
S
– V
OUT2
. The effective
on time of this buck circuit ends when the secondary
voltage becomes zero. The next cycle repeats.
The ideal equation for duty cycle of the LT3710 is:
D2 = V
OUT2
/V
SP
where V
OUT2
is the auxiliary output voltage, V
SP
is the
amplitude of the secondary voltage and D2 is the duty
cycle of the switching node voltage V
SW
, as defined in
Figure 2.
LT3710
8
3710f
Output N-Channel MOSFET Drivers
The LT3710 employs high speed N-channel MOSFET
synchronous drivers to achieve high system efficiency.
GBIAS is the 8V regulator output to bias and supply the
drivers and should be properly bypassed with a low ESR
capacitor to ground plane. A Schottky catch diode is
required on the switch node.
Light Load Operation
If the BGS pin is grounded, the LT3710 stays in continuous
mode independent of load condition except in soft-start
operation (see Soft-Start section). If the BGS pin is left
open, under light load and V
RS1
drops below 8mV, BGATE
will be turned off(see comparator CA2 of Block Diagram)
and the LT3710 goes into discontinous mode operation.
Current Limit
Current limit is set by the 70mV threshold across CL
+
and
CL
–
, the inputs of the amplifier CA1. By connecting an
external resistor RS1(see Block Diagram), the current
limit is set for 70mV/R
S1
. R6 and C6 stablize the current
limit loop. If current limit is not used, both CL
+
and CL
–
should be grounded and the BGS pin should also be
grounded to disable comparator CA2.
Soft-Start and Shutdown
During soft-start, V
SS
is the reference voltage that controls
the output voltage and the output ramps up following V
SS
.
The effective range of V
SS
is from 0V to V
REF
. The typical
time for the output to reach the programmed level is
(C • 0.8V)/10µA.
During start up, BGATE will stay off until V
SS
gets up to
1.6V. This prevents the bottom MOSFET from turning on
if the output is precharged.
To shut down the LT3710, the SS pin should be pulled
below 50mV by a VN2222 type N-channel transistor. Note
that during shutdown BGATE will be locked off when V
SS
drops below 0.6V. This prevents the bottom MOSFET from
APPLICATIO S I FOR ATIO
WUUU
discharging the output, which would cause the output to
undershoot below ground.
Layout Considerations
For maximum efficiency, the switching rise and fall times
are less than 20ns. To prevent radiation, the power
MOSFETs, SW pin and input bypass capacitor leads should
be kept as short as possible. A ground plane should be
used under the switching circuitry to prevent interplane
coupling and to act as a thermal spreading path. Note that
the bottom metal of the package is the heat sink, as well as
the IC signal ground, and must be soldered to the ground
plane.
Output Voltage Programming
The feedback reference voltage is 0.8V. The output voltage
can be easily programmed by the resistor divider, R3 and
R4, as shown in the Block Diagram.
VR
R
OUT2 08 1 3
4
=+
.•
Filtering on the SYNC Input
It is necessary to add RC filtering on the SYNC input of the
LT3710 to eliminate the negative glitch at the turn on of the
top MOSFET. When the top MOSFET M1 turns on, the
transformer secondary current instantly changes from the
original first output inductor current to the sum of two
output inductor currents. The high di/dt on the trans-
former leakage inductance causes the transformer sec-
ondary voltage V
S
to drop for a short interval. If the leakage
inductance is large enough, the V
S
dip will be lower than
the synchronization threshold (about 2.5V), falsely trig-
gering the synchronization. The top MOSFET is turned off
immediately. As a result, the output voltage will not be
regulated properly.
A filter circuit is needed to ensure proper operation. A
small RC filter with R
S
= 10k and C
S
= 10pF are typical.
LT3710
9
3710f
Output Inductor Selection
The key parameters for choosing the inductor include
inductance, RMS and saturation current ratings and DCR.
The inductance must be selected to achieve a reasonable
value of ripple current, which is determined by:
∆= −
()
IVD
fL
LOUT2
12•
•
Typically, the inductor ripple current is designed to be
20% to 40% of the maximum output current.
The RMS current rating must be high enough to deliver the
maximum output current. A sufficient saturation current
rating should prevent the inductor core from saturating.
These two current ratings can be determined by:
II
I
III
RMS O LMAX
SAT O LMAX
≥+
∆
≥+
∆
22
12
2
where I
O
is the maximum output current and ∆I
LMAX
is the
maximum peak-to-peak inductor ripple current.
To optimize the efficiency, we usually choose the inductor
with the minimum DCR if the inductance and current
ratings are the same.
Power MOSFET Selection
The LT3710 drives two external N-channel MOSFETs to
deliver high currents at high efficiency. The gate drive
voltage is typically 6.5V. The key parameters for choos-
ing MOSFETs include drain to source voltage rating V
DSS
and R
DS(ON)
at 6.5V gate drive. Note that the transformer
secondary voltage waveform will overshoot at its rising
edge due to the ringing between transformer leakage
inductance and parasitic capacitance. The V
DSS
of both
top and bottom MOSFETs must be sufficiently higher
than the maximum overshoot. It is recommended that an
RC snubber or a voltage clamping circuitry be placed
across the transformer secondary winding to limit the V
S
overshoot.
The R
DS(ON)
of the MOSFETs should be selected to deliver
the required current at the desired efficiency as well as to
meet the thermal requirement of the MOSFET package.
The conduction power losses of the MOSFETs are:
P
M1
≅ I
O2
• R
DS(ON)M1
• D2
P
M2
≅ I
O2
• R
DS(ON)M2
• (1 – D2)
where I
O
is the maximum output current of LT3710 circuit,
R
DS(ON)M1
and R
DS(ON)M2
are the on-resistance for the top
and bottom MOSFETs, respectively. The R
DS(ON)
must be
determined with 6.5V gate drive and the expected operat-
ing temperature.
A good number of high performance power MOSFET
selections are available from Siliconix, International Rec-
tifier and Fairchild. If the V
DSS
and R
DS(ON)
ratings are the
same, the MOSFETs with the lowest gate charge Q
G
should
be chosen to minimize the power loss associated with the
MOSFET gate drives, the switching transitions and the
controller bias supply.
Output Capacitor Selection
The selection of the output capacitor is determined by the
output ripple and load transient requirements. In low
output voltage applications, always choose capacitors
with low ESR. The output ripple voltage is approximated
by:
∆≈∆ +
V I ESR fC
OUT L OUT
1
8
where ∆I
L
is the inductor peak-to-peak ripple current.
A partial list of low ESR high performance capacitor types
includes SP capacitors from Panasonic and Cornell Dubilier,
POSCAPs and OS-CON capacitors from Sanyo, T510 and
T520 surface mount capacitors from Kemet.
Design Example
Figure 3 shows an application example for the LT3710. It
is a dual output, high efficiency, isolated DC/DC power
supply with 36V to 72V input, 3.3V/10A and 1.8V/10A
outputs. The basic power stage topology is a 2-transistor
APPLICATIO S I FOR ATIO
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LT3710
10
3710f
Figure 3a. 36V to 72V DC to 3.3V/10A and 1.8V/10A (or 2.5V/10A) Dual Output Isolated Power Supply-Basic Circuit (Part 1 of 2, See Next Page)
APPLICATIO S I FOR ATIO
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V
CC
13
2
1
5
1µF 82pF
1nF
OVLO
SHDN
1.24k
73.2k
20k
11V
MMSZ5241B
FZT
853
B0540W
10k
1N4148
270k
4.7µF
5V
REF
6
F
SET
4.7nF
8
SS
10
14
BAS21
BAT54 T2
PULSE
P2033
BAS21
BAT54
BAT54
ZVN3310F
9
V
C
PGND
V
FB
374
THERM
LT3781
SYNC SGND
52.3k
1%
10Ω
1k
3k
1k
470Ω
4.7k
2k
FZT690B
4.7µF
0.22µF
NOTE UNLESS NOTED:
ALL CAPS 25V
ALL RESISTORS 0.1W, 5%
Q1, Q2 SILICONIX Si7456DP
V
CCS
CMPZ5240B
10V
1
3.3Ω
5V
REF
7143
1
4
8
7
5
14
15
6
5
82
3.3nF
4.7nF
0.1µF
5V
REF
12
SG
0.1µF
ON/OFF
11
SENSE
15
BG
18
BSTREF
19
TG
20
BAS21
DO1608C-105
V
BST
220pF
1.5µF
100V
1.2µH
COILCRAFT
D01813P-122HC
1.5µF
100V
22nF
1nF
••
SYNC V
FB
OVPIN
MARGIN
I
COMP
V
DD
OPTODRV
V
AUX
0.1µF
0.01µF
V
OUT1
12
I
SNS
11
I
SNSGND
16
FG
2
CG
PGND GND
LTC1698
PWRGD
6
8
9
7
13
1.24k
1%
1.78k
1%
2.43k
1%
1043
V
COMP
V
OUT1
TRIM
3710 F03a
3.01k
1%
B0540W
0.025Ω
1/2W
3
4
Q2
1nF
100V
2.2nF
250VAC
1nF
100V
Si7440DP
×2Si7440DP
470µF
4V
POSCAP
MUR120S
MUR120S
2
7
5
•
••
1
Q1
T1
PULSE
PA0191
V
IN+
V
IN–
V
OUT1+
3.3V
AT 10A
V
OUT
RTN
10Ω
10Ω
SEC 2.5µH
SUMIDA CEP125-2R5
+
470µF
4V
POSCAP
+
1µF
B0540W
1µF
0.1µF
330pF
10k
LT3710
11
3710f
forward converter with synchronous rectification. The
primary side controller uses an LT3781, a current mode
2-transistor forward controller with built-in MOSFET driv-
ers. On the secondary side, an LTC1698 is used to provide
the voltage feedback for the 3.3V output, as well as the gate
drive for the synchronous MOSFETs. The error amplifier
output is fed into the optocoupler and then relayed to
LT3781 on the primary side to complete the 3.3V regula-
tion. The 1.8V output is generated by the LT3710 circuit.
A planar transformer PA0191 built by Pulse Engineering is
employed as the power transformer in this design. This
transformer is constructed on a PQ20 core with a nine turn
primary winding, two turn secondary winding and seven
turn auxiliary winding for the LT3781 bias supply. Because
the maximum secondary voltage V
SP
is about 16V, 30V
MOSFETs are chosen with the consideration that the
secondary voltage overshoot is typically 20% to 30% of
V
SP
. In this particular design, Si7440DP is selected due to
its low R
SD(ON)
, 30V V
DSS
rating and its compact and
thermally enhanced PowerPak SO-8 package.
The switching frequency of the circuit is about 230kHz.
1500V input to output isolation is provided. Additional
features of this design include primary side on/off control,
±5% secondary side trimming on the 3.3V output, input
overvoltage protection and undervoltage lockout. The
complete design will mount within a standard half brick PC
board with about half inch height.
Figure 3b. 36V to 72V DC to 3.3V/10A and 1.8V/10A Dual Output Isolated Power Supply (Part 2 of 2, See Previous Page)
SYNC GBIAS
BOOST
VA
OUT
LT3710
3.3k
0.033µF
0.01µF
B340A
V
OUT2
1.8V/10A
1.8µH
SUMIDA
CEP125-IR8 0.006Ω
1%
TGATE
16
2
V
FB
SS
5
7
SW 3
V
CC
13
BGATE 15
CSET
4
BGS 9
PGND
14
CL
+
11
ILCOMP
6
CL
–
12
8
1
10
PGND
17
0.01µF
10pF
1µF
V
CCS
0.1µF
16V
Si7440DP
Si7440DP
220Ω
3710 F03b
330pF
4.7µF
16V
CMDSH-3
CMDSH-3
10Ω
10k
10k
180pF
C37 680pF
SEC
2.32k
1%
3.01k
1%
680µF
4V
POSCAP
+
680µF
4V
POSCAP
+
4700pF
APPLICATIO S I FOR ATIO
WUUU
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
LT3710
12
3710f
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900
●
FAX: (408) 434-0507
●
www.linear.com
LINEAR TECHNOLOGY CORPORATION 2002
LT/TP 0803 1K • PRINTED IN USA
RELATED PARTS
PACKAGE DESCRIPTIO
U
PART NUMBER DESCRIPTION COMMENTS
LT1339 High Power Synchronous DC/DC Controller Operation Up to 60V Maximum
LT1425 Isolated Flyback Switching Regulator General Purpose with External Application Resistor
LT1431 Programmable Reference 0.4% Initial Voltage Tolerance
LT1680 High Power DC/DC Step-Up Controller Operation Up to 60V Maximum
LT3781 Dual Transistor Synchronous Forward Controller Operation Up to 72V Maximum
LT1725 General Purpose Isolated Flyback Controller Drives External Power MOSFET with External I
SENSE
Resistor
LT1737 High Power Isolated Flyback Controller Sense Output Voltage Directly from Primary-Side Winding
LT1950 PWM Controller for Flyback, Forward and SEPIC 15W to 500W, Isolated and Nonisolated Power Supply 50% Smaller
Applications Transformer, Protects MOSFET
LT3804 Secondary Side Dual Output Controller Regulates Two Outputs, Optocoupler Feedback Driver and Second Output
with Optodriver Synchronous Driver Controller
FE Package
16-Lead Plastic TSSOP (4.4mm)
(Reference LTC DWG # 05-08-1663)
Exposed Pad Variation BA
FE16 (BA) TSSOP 0203
0.09 – 0.20
(.0036 – .0079)
0° – 8°
0.45 – 0.75
(.018 – .030)
4.30 – 4.50*
(.169 – .177)
6.40
BSC
134
5678
10 9
4.90 – 5.10*
(.193 – .201)
16 1514 13 12 11
1.10
(.0433)
MAX
0.05 – 0.15
(.002 – .006)
0.65
(.0256)
BSC
2.74
(.108)
2.74
(.108)
0.195 – 0.30
(.0077 – .0118)
2
MILLIMETERS
(INCHES) *DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.150mm (.006") PER SIDE
NOTE:
1. CONTROLLING DIMENSION: MILLIMETERS
2. DIMENSIONS ARE IN
RECOMMENDED SOLDER PAD LAYOUT
3. DRAWING NOT TO SCALE
0.45 ±0.05
0.65 BSC
4.50 ±0.10
6.60 ±0.10
1.05 ±0.10
2.74
(.108)
2.74
(.108)
SEE NOTE 4
4. RECOMMENDED MINIMUM PCB METAL SIZE
FOR EXPOSED PAD ATTACHMENT
