3PS8872H 09/26/08
PI2EQX4401D
2.5Gbps x1 Lane Serial PCI-Express Repeater/Equalizer
with Clock Buffer & Signal Defect Feature
Pin Description
Pin # Pin Name I/O Description
1, 6, 10, 23, 28 VDD PWR 1.8V Supply Voltage
2 AI+ I Positive CML Input Channel A with internal 50Ω pull down during normal
operation (EN_A=1). When EN_A=0, this pin is high-impedance.
3 AI- I Negative CML Input Channel A with internal 50Ω pull down during normal
operation (EN_A=1). When EN_A=0, this pin is high-impedance.
4, 9, 20, 25 GND PWR Supply Ground
22 BI+ I Positive CML Input Channel B with internal 50Ω pull down during normal
operation (EN_B=1). When EN_B=0, this pin is high-impedance.
21 BI- I Negative CML Input Channel B with internal 50Ω pull down during normal
operation (EN_B=1). When EN_B=0, this pin is high-impedance.
34, 33 SEL[0:1]_A I Selection pins for equalizer (see Amplifi er Confi guration Table)
w/ 50KΩ internal pull up
13, 14 SEL[0:1]_B I
32 SEL[2]_A I Selection pins for amplifi er (see Amplifi er Confi guration Table)
w/ 50KΩ internal pull up
15 SEL[2]_B I
31 SEL[3]_A I Selection pins for De-Emphasis (See De-Emphasis Confi guration Table)
w/ 50KΩ internal pull up
16 SEL[3]_B I
27 AO+ O Positive CML Output Channel A internal 50Ω pull up during normal opera-
tion and 2KΩ pull up otherwise.
26 AO- O Negative CML Output Channel A with internal 50Ω pull up during normal
operation and 2KΩ pull up otherwise.
7 BO+ O Positive CML Output Channel B with internal 50Ω pull up during normal
operation and 2KΩ pull up otherwise.
8 BO- O Negative CMLOutput Channel B with internal 50Ω pull up during normal
operation and 2KΩ pull up otherwise.
30, 29 EN_[A,B] I EN_[A:B] is the enable pin. A LVCMOS high provides normal operation. A
LVCMOS low selects a low power down mode.
12 CLKIN- I Differential Input Reference Clock. If clock buffer is not used, then both
CLKIN+, CLKIN- should be pulled high to VDD.
11 CLKIN+ I
17, 18 OUT+, OUT- O Differential Reference Clock Output
5 AVDD PWR 1.8V Analog supply voltage
24 AGND PWR Analog ground
19 IREF O External 475Ω resistor connection to set the differential output current. If the
clock buffer is not used, then IREF should be unconnected (open).
36, 35 SIG_A, SIG_B O SIG Detector output for channel A-B. Provides a LVCMOS high output when
an input signal greater than the threshold is detected