SM802111UMGR - Micrel, Inc. - Datasheet.Directory

SM802111

ClockWorks™GbE Dual 125MHz

Ultra-Low Jitter, LVPECL

Frequency Synthesizer

ClockWorks is a trademark of Micrel, Inc.

RotaryWave is a registered trademark of Multigig, Inc.

Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1 (408) 944-0800 • fax + 1 (408) 474-1000 • http://www.micrel.com

April 2011 M9999-041111-A

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General Description

The SM802111 is a member of the ClockWorks™ family of

devices from Micrel and provides an extremely low-noise

timing solution for Gigabit Ethernet clock signals. It is

based upon a unique patented RotaryWave® architecture

that provides very-low phase noise.

The device operates from a 3.3V or 2.5V power supply

and synthesizes two LVPECL output clocks at 125MHz.

The SM802111 accepts a 15MHz LVCMOS reference

clock.

Data sheets and support documentation can be found on

Micrel’s web site at: www.micrel.com.

Features

• Generates two LVPECL clock outputs at 125MHz

• 2.5V or 3.3V operating range

• Typical phase jitter @ 125MHz

(1.875MHz to 20MHz): 85fs (typical) at 3.3V

• Industrial temperature range

• Green, RoHS, and PFOS compliant

• Available in 24-pin 4mm × 4mm QFN

Applications

• Gigabit Ethernet

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Block Diagram

Micrel, Inc. SM802111

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Ordering Information

Part Number Marking Shipping Junction Temperature Range Package

SM802111UMG 802111 Tube –40° to +85°C 24-Pin QFN

SM802111UMGR 802111 Tape & Reel –40° to +85°C 24-Pin QFN

Note:

1. Devices are Green, RoHS, and PFOS compliant.

Pin Configur ation

24-Pin QFN

(Top View)

Pin Description

Pin Number Pin Name Pin Type Pin Level Pin Function

16, 17

20, 21

/Q0, Q0

/Q1, Q1 O, (DIF) LVPECL Differential Clock Output.

1, 18 VDDO PWR Power Supply for Clock Output.

2, 22 VSSO PWR Power Supply Grounds for Clock Output.

3, 4, 23, 24 NC No Connect,. Do not connect anything to these pins.

5 PLL_BYPASS I, (SE) LVCMOS

PLL Bypass, Selects Output Source

0 = Normal PLL Operation

1 = Output from Input Reference Clock

45K pull-down

7, 10, 11, 12,

15, 19 TEST Factory Test Pins. Do not connect anything to these pins.

8 VDD PWR Core Power Supply.

9 REF_IN I, (SE) LVCMOS Reference Clock Input.

6, 13, 14 VSS PWR Core Power Supply Ground.

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Absolute Maximum Ratings(1)

Supply Voltage (VDD, VDDO) .........................................+4.6V

Input Voltage (VIN) .............................. −0.50V to VDD + 0.5V

Lead Temperature (soldering, 20s)............................ 260°C

Case Temperature ..................................................... 115°C

Storage Temperature (Ts) ......................... −65°C to +150°C

Operating Ratings(2)

Supply Voltage (VDD, VDDO) .................. +2.375V to +3.465V

Ambient Temperature (TA) ..........................–40°C to +85°C

Junction Thermal Resistance(3)

QFN (θJA)

Still-Air.........................................................50°C/W

QFN (ψJB)

Junction-to-Board........................................30°C/W

DC Electrical Characteristics(4)

VDD = VDDO = 3.3V ±5% or 2.5V ±5%

VDD = 3.3V ±5%, VDDO = 3.3V ±5% or 2.5V ±5%

TA = –40°C to +85°C

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LVPECL DC Electrical Char acteristics(4)

VDD = VDDO 3.3V ±5% or 2.5V ±5%

VDD = 3.3V ±5%, VDDO = 3.3V ±5% or 2.5V ±5%

TA = –40°C to +85°C; RL = 50 to VDDO − 2V

LVCMOS (PLL_BYPASS) DC Electrical Characteristics(4)

VDD = 3.3V ±5% or 2.5V ±5%, TA = –40°C to +85°C

Symbol Parameter Condition Min. Typ. Max. Units

VIH Input High Voltage 2

VDD + 0.3 V

VIL Input Low Voltage −0.3 0.8 V

IIH Input High Current VDD = VIN = 3.465V 150

μA

IIL Input Low Current VDD = 3.465V, VIN = 0V −5

μA

Notes:

1. Permanent device damage may occur if absolute maximum ratings are exceeded. This is a stress rating only and functional operation is not

implied at conditions other than those detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for

extended periods may affect device reliability.

2. The data sheet limits are not guaranteed if the device is operated beyond the operating ratings.

3. Package thermal resistance assumes exposed pad is soldered (or equivalent) to the devices most negative potential on the PCB.

4. The circuit is designed to meet the AC and DC specifications shown in the above table after thermal equilibrium has been established.

Symbol Parameter Condition Min. Typ. Max. Units

VDD, VDDO 2.5V Operating Voltage 2.375 2.5 2.625 V

VDD, VDDO 3.3V Operating Voltage 3.135 3.3 3.465 V

IDD Supply Current, VDD + VDDO Outputs open 91 115 mA

Symbol Parameter Condition Min. Typ. Max. Units

VOH Output High Voltage VDDO – 1.145 VDDO – 0.97 VDDO – 0.845 V

VOL Output Low Voltage VDDO – 1.945 VDDO – 1.77 VDDO – 1.645 V

VSWING Output Voltage Swing 0.6 0.8 1.0 V

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Ref_IN DC Electrical Characteristics(4)

VDD = 3.3V ±5% or 2.5V ±5%, TA = –40°C to +85°C.

Symbol Parameter Condition Min. Typ. Max. Units

VIH Input High Voltage 1.1

VDD + 0.3 V

VIL Input Low Voltage −0.3 0.6 V

IIN Input Current VDD = 3.465V, VIN = 0V to VDD −5 5

μA

AC Electrical Characteristics(4, 5)

VDD = VDDO = 3.3V ±5% or 2.5V ±5%

VDD = 3.3V ±5%, VDDO = 3.3V ±5% or 2.5V ±5%

TA = −40°C to +85°C; RL = 50 to VDDO − 2V

Symbol Parameter Condition Min. Typ. Max. Units

FOUT Output Frequency 125 MHz

FREF Reference Input Frequency 15 MHz

TR/TF LVPECL Output Rise/Fall Time 20% – 80% 80 175 350 ps

ODC Output Duty Cycle 48 50 52 %

TSKEW Output-to-Output Skew Note 6 45 ps

TLOCK PLL Lock Time 20 ms

Tjit(∅) RMS Phase Jitter (7) Output = 125MHz Integration

Range (1.875MHz – 20MHz) 85 fs

Spurious Noise Components 5MHz -73 dBc

Notes:

5. All phase-noise measurements were taken with an Agilent 5052B phase-noise system.

6. Defined as skew between outputs at the same supply voltage and with equal load conditions; Measured at the output differential crossing points.

7. Ref_IN driven with a low-noise source ClockWorks SM802001 programmed for a 15MHz CMOS output. Phase noise will track the input phase

noise up to about 1MHz offset frequency.

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SM802111 Phase Noise Plot

Phase Noise Plot: 125MHz (1.875MHz − 20MHz 75fs)

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Figure 1. Duty Cycle Timing Figure 2. All Outputs Rise/Fall Time

Figure 3. RMS Phase Noise/Jitter Figure 4. LVPECL Outpu t Load and Test Circuit

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Package Information

24-Pin QFN

MICREL, INC. 2180 FORTUNE DRIVE SAN JOSE, CA 95131 USA

TEL +1 (408) 944-0800 FAX +1 (408) 474-1000 WEB http://www.micrel.com

Micrel makes no representations or warranties with respect to the accuracy or completeness of the information furnished in this data sheet. This

information is not intended as a warranty and Micrel does not assume responsibility for its use. Micrel reserves the right to change circuitry,

specifications and descriptions at any time without notice. No license, whether express, implied, arising by estoppel or otherwise, to any intellectual

property rights is granted by this document. Except as provided in Micrel’s terms and conditions of sale for such products, Micrel assumes no liability

whatsoever, and Micrel disclaims any express or implied warranty relating to the sale and/or use of Micrel products including liability or warranties

relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right.

Micrel Products are not designed or authorized for use as components in life support appliances, devices or systems where malfunction of a product

reasonably be expected to result in personal injury. Life support devices or systems are devices or systems that (a) are intended for surgical impla

into the body or (b) support or sustain life, and whose failure to perform can be reasonably expected to result in a significant injury to the user. A

Purchaser’s use or sale of Micrel Products for use in life support appliances, devices or systems is a Purchaser’s own risk and Purchaser agrees to fully

indemnify Micrel for any damages resulting from such use or sale.

can nt

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