74AC240, 74ACT240 — Octal Buffer/Line Driver with 3-STATE Outputs
©2006 Fairchild Semiconductor Corporation www.fairchildsemi.com
74AC240, 74ACT240 Rev. 1.2.0
January 2008
74AC240, 74ACT240
Octal Buffer/Line Driver with 3-STATE Outputs
Features
I
CC
and I
OZ
reduced by 50%
Inverting 3-STATE outputs drive bus lines or buffer
memory address registers
Outputs source/sink 24mA
ACT240 has TTL-compatible inputs
General Description
The AC/ACT240 is an octal buffer and line driver
designed to be employed as a memory address driver,
clock driver and bus oriented transmitter or receiver
which provides improved PC board density.
Ordering Information
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering number.
All packages are lead free per JEDEC: J-STD-020B standard.
Order Number
Package
Number Package Description
74AC240SC M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
74AC240SJ M20D 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74AC240MTC MTC20 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm
Wide
74AC240PC N20A 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
74ACT240SC M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
74ACT240SJ M20D 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74ACT240MTC MTC20 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm
Wide
74ACT240PC N20A 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
©2006 Fairchild Semiconductor Corporation www.fairchildsemi.com
74AC240, 74ACT240 Rev. 1.2.0 2
74AC240, 74ACT240 — Octal Buffer/Line Driver with 3-STATE Outputs
Connection Diagram
Pin Description
Logic Symbol
IEEE/IEC
Truth Tables
H
=
HIGH Voltage Level
L
=
LOW Voltage Level
X
=
Immaterial
Z
=
High Impedance
Pin Names Description
OE
1
, OE
2
3-STATE Output Enable Inputs
I
0
–I
7
Inputs
O
0
–O
7
Outputs
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
OE1
I0
O4
I1
O5
I2
O6
I3
O7
GND
VCC
OE2
O0
I4
O1
I5
O2
I6
O3
I7
Inputs Outputs
(Pins 12, 14, 16, 18)OE
1
I
n
LL H
LH L
HX Z
Inputs Outputs
(Pins 3, 5, 7, 9)OE
2
I
n
LL H
LH L
HX Z
O0
OE1EN
I0
O1
I1
O2
I2
O3
I3
O4
I4
O5
I5
O6
I6
O7
I7
OE2EN
©2006 Fairchild Semiconductor Corporation www.fairchildsemi.com
74AC240, 74ACT240 Rev. 1.2.0 3
74AC240, 74ACT240 — Octal Buffer/Line Driver with 3-STATE Outputs
Absolute Maximum Ratings
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be
operable above the recommended operating conditions and stressing the parts to these levels is not recommended.
In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability.
The absolute maximum ratings are stress ratings only.
Recommended Operating Conditions
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended
operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not
recommend exceeding them or designing to absolute maximum ratings.
Symbol Parameter Rating
V
CC
Supply Voltage
0.5V to
+
7.0V
I
IK
DC Input Diode Current
V
I
=
0.5V
20mA
V
I
=
V
CC
+
0.5
+
20mA
V
I
DC Input Voltage
0.5V to V
CC
+
0.5V
I
OK
DC Output Diode Current
V
O
=
0.5V
20mA
V
O
=
V
CC
+
0.5V
+
20mA
V
O
DC Output Voltage
0.5V to V
CC
+
0.5V
I
O
DC Output Source or Sink Current
±
50mA
I
CC
or I
GND
DC V
CC
or Ground Current per Output Pin
±
50mA
T
STG
Storage Temperature
65
°
C to
+
150
°
C
T
J
Junction Temperature 140
°
C
Symbol Parameter Rating
V
CC
Supply Voltage
AC 2.0V to 6.0V
ACT 4.5V to 5.5V
V
I
Input Voltage 0V to V
CC
V
O
Output Voltage 0V to V
CC
T
A
Operating Temperature
40
°
C to
+
85
°
C
V
/
t Minimum Input Edge Rate, AC Devices:
V
IN
from 30% to 70% of V
CC
,
V
CC
@ 3.3V, 4.5V, 5.5V
125mV/ns
V
/
t Minimum Input Edge Rate, ACT Devices:
V
IN
from 0.8V to 2.0V, V
CC
@ 4.5V, 5.5V
125mV/ns
©2006 Fairchild Semiconductor Corporation www.fairchildsemi.com
74AC240, 74ACT240 Rev. 1.2.0 4
74AC240, 74ACT240 — Octal Buffer/Line Driver with 3-STATE Outputs
DC Electrical Characteristics for AC
Notes:
1. All outputs loaded; thresholds on input associated with output under test.
2. I
IN
and I
CC
@ 3.0V are guaranteed to be less than or equal to the respective limit @ 5.5V V
CC
.
3. Maximum test duration 2.0ms, one output loaded at a time.
Symbol Parameter V
CC
(V) Conditions
T
A
=
+
25
°
CT
A
=
40
°
C to
+
85
°
C
UnitsTyp. Guaranteed Limits
V
IH
Minimum HIGH Level
Input Voltage
3.0 V
OUT
= 0.1V or
V
CC
– 0.1V
1.5 2.1 2.1 V
4.5 2.25 3.15 3.15
5.5 2.75 3.85 3.85
V
IL
Maximum LOW Level
Input Voltage
3.0 V
OUT
= 0.1V or
V
CC
– 0.1V
1.5 0.9 0.9 V
4.5 2.25 1.35 1.35
5.5 2.75 1.65 1.65
V
OH
Minimum HIGH Level
Output Voltage
3.0 I
OUT
= –50µA 2.99 2.9 2.9 V
4.5 4.49 4.4 4.4
5.5 5.49 5.4 5.4
3.0 V
IN
=
V
IL
or V
IH,
IOH = –12mA
2.56 2.46
4.5 VIN = VIL or VIH,
IOH = –24mA
3.86 3.76
5.5 VIN = VIL or VIH,
IOH = –24mA(1)
4.86 4.76
VOL Maximum LOW Level
Output Voltage
3.0 IOUT = 50µA 0.002 0.1 0.1 V
4.5 0.001 0.1 0.1
5.5 0.001 0.1 0.1
3.0 VIN = VIL or VIH,
IOL = 12mA
0.36 0.44
4.5 VIN = VIL or VIH,
IOL = 24mA
0.36 0.44
5.5 VIN = VIL or VIH,
IOL = 24mA(1)
0.36 0.44
IIN(2) Maximum Input
Leakage Current
5.5 VI = VCC, GND ±0.1 ±1.0 µA
IOZ Maximum 3-STATE
Leakage Current
5.5 VI (OE) = VIL, VIH;
VI = VCC, GND;
VO = VCC, GND
±0.25 ±2.5 µA
IOLD Minimum Dynamic
Output Current(3) 5.5 VOLD = 1.65V Max. 75 mA
IOHD 5.5 VOHD = 3.85V Min. -75 mA
ICC(2) Maximum Quiescent
Supply Current
5.5 VIN = VCC or GND 4.0 40.0 µA
©2006 Fairchild Semiconductor Corporation www.fairchildsemi.com
74AC240, 74ACT240 Rev. 1.2.0 5
74AC240, 74ACT240 — Octal Buffer/Line Driver with 3-STATE Outputs
DC Electrical Characteristics for ACT
Notes:
4. All outputs loaded; thresholds on input associated with output under test.
5. Maximum test duration 2.0ms, one output loaded at a time.
Symbol Parameter VCC (V) Conditions
TA = +25°CT
A = 40°C to +85°C
UnitsTyp. Guaranteed Limits
VIH Minimum HIGH Level
Input Voltage
4.5 VOUT = 0.1V or
VCC 0.1V
1.5 2.0 2.0 V
5.5 1.5 2.0 2.0
VIL Maximum LOW
Level Input Voltage
4.5 VOUT = 0.1V or
VCC 0.1V
1.5 0.8 0.8 V
5.5 1.5 0.8 0.8
VOH Minimum HIGH Level
Output Voltage
4.5 IOUT = 50µA 4.49 4.4 4.4 V
5.5 5.49 5.4 5.4
4.5 VIN = VIL or VIH,
IOH = 24mA
3.86 3.76
5.5 VIN = VIL or VIH,
IOH = 24mA(4)
4.86 4.76
VOL Maximum LOW
Level Output Voltage
4.5 IOUT = 50µA 0.001 0.1 0.1 V
5.5 0.001 0.1 0.1
4.5 VIN = VIL or VIH,
IOL = 24mA
0.36 0.44
5.5 VIN = VIL or VIH,
IOL = 24mA(4)
0.36 0.44
IIN Maximum Input
Leakage Current
5.5 VI = VCC, GND ±0.1 ±1.0 µA
IOZ Maximum 3-STATE
Leakage Current
5.5 VI = VIL, VIH;
VO = VCC, GND
±0.25 ±2.5 µA
ICCT Maximum ICC/Input 5.5 VI = VCC 2.1V 0.6 1.5 mA
IOLD Minimum Dynamic
Output Current(5) 5.5 VOLD = 1.65V Max. 75 mA
IOHD 5.5 VOHD = 3.85V Min. 75 mA
ICC Maximum Quiescent
Supply Current
5.5 VIN = VCC or GND 4.0 40.0 µA
©2006 Fairchild Semiconductor Corporation www.fairchildsemi.com
74AC240, 74ACT240 Rev. 1.2.0 6
74AC240, 74ACT240 — Octal Buffer/Line Driver with 3-STATE Outputs
AC Electrical Characteristics for AC
Note:
6. Voltage range 3.3 is 3.3V ± 0.3V. Voltage range 5.0 is 5.0V ± 0.5V.
AC Electrical Characteristics for ACT
Note:
7. Voltage range 5.0 is 5.0V ± 0.5V.
Capacitance
Symbol Parameter VCC (V)(6)
TA = +25°C,
CL = 50pF
TA = 40°C to +85°C,
CL = 50pF
UnitsMin. Typ. Max. Min. Max.
tPLH Propagation Delay
Data to Output
3.3 1.5 6.0 8.0 1.0 9.0 ns
5.0 1.5 4.5 6.5 1.0 7.0
tPHL Propagation Delay
Data to Output
3.3 1.5 5.5 8.0 1.0 8.5 ns
5.0 1.5 4.5 6.0 1.0 6.5
tPZH Output Enable Time 3.3 1.5 6.0 10.5 1.0 11.0 ns
5.0 1.5 5.0 7.0 1.0 8.0
tPZL Output Enable Time 3.3 1.5 7.0 10.0 1.0 11.0 ns
5.0 1.5 5.5 8.0 1.0 8.5
tPHZ Output Disable Time 3.3 1.5 7.0 10.0 1.0 10.5 ns
5.0 1.5 6.5 9.0 1.0 9.5
tPLZ Output Disable Time 3.3 1.5 7.5 10.5 1.0 11.5 ns
5.0 1.5 6.5 9.0 1.0 9.5
Symbol Parameter VCC (V)(7)
TA = +25°C,
CL = 50pF
TA = 40°C to +85°C,
CL = 50pF
UnitsMin. Typ. Max. Min. Max.
tPLH Propagation Delay,
Data to Output
5.0 1.5 6.0 8.5 1.5 9.5 ns
tPHL Propagation Delay,
Data to Output
5.0 1.5 5.5 7.5 1.5 8.5 ns
tPZH Output Enable Time 5.0 1.5 7.0 8.5 1.0 9.5 ns
tPZL Output Enable Time 5.0 2.0 7.0 9.5 1.5 10.5 ns
tPHZ Output Disable Time 5.0 2.0 8.0 9.5 2.0 10.5 ns
tPLZ Output Disable Time 5.0 2.5 6.5 10.0 2.0 10.5 ns
Symbol Parameter Conditions Typ. Units
CIN Input Capacitance VCC = OPEN 4.5 pF
CPD Power Dissipation Capacitance VCC = 5.0V 45.0 pF
©2006 Fairchild Semiconductor Corporation www.fairchildsemi.com
74AC240, 74ACT240 Rev. 1.2.0 7
74AC240, 74ACT240 — Octal Buffer/Line Driver with 3-STATE Outputs
Physical Dimensions
Figure 1. 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or
obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions,
specifically the warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/
0.10 C
C
A
SEE DETAIL A
NOTES: UNLESS OTHERWISE SPECIFIED
A) THIS PACKAGE CONFORMS TO JEDEC
MS-013, VARIATION AC, ISSUE E
B) ALL DIMENSIONS ARE IN MILLIMETERS.
C) DIMENSIONS DO NOT INCLUDE MOLD
FLASH OR BURRS.
E) LANDPATTERN STANDARD: SOIC127P1030X265-20L
PIN ONE
INDICATOR
0.25
110
BC A
M
20 11
B
X 45°
8°
0°
SEATING PLANE
GAGE PLANE
DETAIL A
SCALE: 2:1
SEATING PLANE
LAND PATTERN RECOMMENDATION
F) DRAWING FILENAME: MKT-M20BREV3
0.65
1.27
2.25
9.50
13.00
12.60
11.43
7.60
7.40
10.65
10.00
0.51
0.35 1.27
2.65 MAX
0.30
0.10
0.33
0.20
0.75
0.25
(R0.10)
(R0.10)
1.27
0.40
(1.40)
0.25
D) CONFORMS TO ASME Y14.5M-1994
©2006 Fairchild Semiconductor Corporation www.fairchildsemi.com
74AC240, 74ACT240 Rev. 1.2.0 8
74AC240, 74ACT240 — Octal Buffer/Line Driver with 3-STATE Outputs
Physical Dimensions (Continued)
Figure 2. 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or
obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions,
specifically the warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/
©2006 Fairchild Semiconductor Corporation www.fairchildsemi.com
74AC240, 74ACT240 Rev. 1.2.0 9
74AC240, 74ACT240 — Octal Buffer/Line Driver with 3-STATE Outputs
Physical Dimensions (Continued)
Figure 3. 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or
obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions,
specifically the warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/
©2006 Fairchild Semiconductor Corporation www.fairchildsemi.com
74AC240, 74ACT240 Rev. 1.2.0 10
74AC240, 74ACT240 — Octal Buffer/Line Driver with 3-STATE Outputs
Physical Dimensions (Continued)
Figure 4. 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or
obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions,
specifically the warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/
.001[.025] C
7°TYP
7°TYP
10.92 MAX
26.92
24.89
7.11
6.09
1.78
1.14
2.54 7.62
7.87
3.43
3.175.33 MAX
3.55
3.17
0.38 MIN
0.36
0.56 0.20
0.35
PIN #1
NOTES:
(0.97)
©2006 Fairchild Semiconductor Corporation www.fairchildsemi.com
74AC240, 74ACT240 Rev. 1.2.0 11
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PRODUCT STATUS DEFINITIONS
Definition of Terms
Datasheet Identification Product Status Definition
Advance Information Form
First Production
ative or In Design This datasheet contains the design specifications for product
development. Specifications may change in any manner without notice.
Preliminary
This datasheet contains preliminary data; supplementary data will be
published at a later date. Fairchild Semiconductor reserves the right to
make changes at any time without notice to improve design.
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This datasheet contains final specifications. Fairchild Semiconductor
reserves the right to make changes at any time without notice to improve
the design.
Obsolete Not In Production
This datasheet contains specifications on a product that has been
discontinued by Fairchild Semiconductor. The datasheet is printed for
reference information only.
Rev. I32
74AC240, 74ACT240 — Octal Buffer/Line Driver with 3-STATE Outputs