84324AM www.icst.com/products/hiperclocks.html REV. A JANUARY 22, 2003
1
Integrated
Circuit
Systems, Inc.
ICS84324
CRYSTAL-TO-3.3V L VPECL
FREQUENCY SYNTHESIZER WITH FANOUT BUFFER
PRELIMINARY
GENERAL DESCRIPTION
The ICS84324 is a Crystal-to-3.3V LVPECL Fre-
quency Synthesizer with Fanout Buffer and a mem-
ber of the HiPerClockS™ family of High Performance
Clock Solutions from ICS. Output frequency can
be programmed using the feedback and output fre-
quency select pins. The low phase noise characteristics of the
ICS84324 make it an ideal clock source for Fibre Channel 1
and Gigabit Ethernet applications.
BLOCK DIAGRAM PIN ASSIGNMENT
FEATURES
•6 differential 3.3V L VPECL outputs
•Crystal oscillator interface
•Output frequency range: 53.125MHz to 125MHz
•Crystal input frequency: 25MHz
• Cycle-to-cycle jitter: 25ps (typical)
•RMS phase jitter at 106.25MHz, using a 25MHz crystal
(637KHz to 10Mhz): 4.15ps
•T ypical Phase noise at 106.25MHz
Offset Noise Power
100Hz ..................-80dBc/Hz
1KHz ................-105dBc/Hz
10KHz ................-125dBc/Hz
100KHz ................-125dBc/Hz
•3.3V supply voltage
•0°C to 70°C ambient operating temperature
•Industrial termperature information available upon request
HiPerClockS™
,&6
Q0:Q5
ICS84324
24-Lead, 300-MIL SOIC
7.5mm x 15.33mm x 2.3mm body package
M Package
Top View
Q0
nQ0
Q1
nQ1
Q2
nQ2
Q3
nQ3
Q4
nQ4
Q5
nQ5
1
2
3
4
5
6
7
8
9
10
11
12
VCC
F_SEL0
F_SEL1
MR
XTAL1
XTAL2
VEE
VCCA
VCC
PLL_SEL
VEE
VCC
PLL
6
/
Feedback
Divider
OSC 6
/
Output
Divider
0
1
XTAL1
XTAL2
F_SEL1 PLL_SELMR F_SEL0
nQ0:nQ5
24
23
22
21
20
19
18
17
16
15
14
13
FUNCTION TABLE
stupnIycneuqerFtuptuO
RM1LES_F0LES_FTUO_F
1X X WOL
00 0 zHM521.35
00 1 zHM52.601
01 0 zHM5.26
01 1 zHM521
The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics a re based on initial
product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice.
84324AM www.icst.com/products/hiperclocks.html REV. A JANUARY 22, 2003
2
Integrated
Circuit
Systems, Inc.
ICS84324
CRYSTAL-TO-3.3V LVPECL
FREQUENCY SYNTHESIZER WITH FANOUT BUFFER
PRELIMINARY
TABLE 1. PIN DESCRIPTIONS
rebmuNemaNepyTnoitpircseD
2,10Qn,0QtuptuO.slevelecafretniLCEPVL.riaptuptuolaitnereffiD
4,31Qn,1QtuptuO.slevelecafretniLCEPVL.riaptuptuolaitnereffiD
6,52Qn,2QtuptuO.slevelecafretniLCEPVL.riaptuptuolaitnereffiD
8,73Qn,3QtuptuO.slevelecafretniLCEPVL.riaptuptuolaitnereffiD
01,94Qn,4QtuptuO.slevelecafretniLCEPVL.riaptuptuolaitnereffiD
21,115Qn,5QtuptuO.slevelecafretniLCEPVL.riaptuptuolaitnereffiD
42,61,31V
CC
rewoP.snipylppuseroC
81,41V
EE
.snipylppusevitageN
51LES_LLPtupnIpulluP .sredividehtottupniehtsastupnilatsyrcdnaLLPehtneewtebstceleS .2LATX,1LATXstceles,WOLnehW.LLPstceles,HGIHnehW .slevelecafretniLTTVL/SOMCVL
71V
ACC
rewoP.nipylppusgolanA
02,911LATX,2LATXtupnI .tuptuoehtsi2LATX.tupniehtsi1LATX.ecafretnirotallicsolatsyrC
12RMtupnInwodlluP .WOLstuptuoehtsecrof,HGIHcigolnehW.teseRretsaM .delbaneerastuptuoeht,WOLcigolnehW .slevelecafretniLTTVL/SOMCVL
221LES_FtupnInwodlluP .slevelecafretniLTTVL/SOMCVL.niptcelesycneuqerfkcabdeeF
320LES_FtupnIpulluP.slevelecafretniLTTVL/SOMCVL.niptcelesycneuqerftuptuO
:ETON
pulluP
dna
nwodlluP
.seulavlacipytrof,scitsiretcarahCniP,2elbaTeeS.srotsisertupnilanretniotrefer
TABLE 2. PIN CHARACTERISTICS
lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU
C
NI
ecnaticapaCtupnI 4Fp
R
PULLUP
rotsiseRpulluPtupnI 15KΩ
R
NWODLLUP
rotsiseRnwodlluPtupnI 15KΩ
84324AM www.icst.com/products/hiperclocks.html REV. A JANUARY 22, 2003
3
Integrated
Circuit
Systems, Inc.
ICS84324
CRYSTAL-TO-3.3V L VPECL
FREQUENCY SYNTHESIZER WITH FANOUT BUFFER
PRELIMINARY
TABLE 3A. POWER SUPPLY DC CHARACTERISTICS, VCC = VCCA = 3.3V±5%, TA = 0°C TO 70°C
TABLE 3B. LVCMOS / LVTTL DC CHARACTERISTICS, VCC = VCCA = 3.3V±5%, TA = 0°C TO 70°C
lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU
V
HI
egatloVhgiHtupnI ,RM,LES_LLP 1LES_F,0LES_F 2V
CC
3.0+V
V
LI
egatloVwoLtupnI ,RM,LES_LLP 1LES_F,0LES_F 3.0-8.0V
I
HI
tnerruChgiHtupnI 1LES_F,RMV
CC
V=
NI
V564.3=051Aµ
0LES_F,LES_LLPV
CC
V=
NI
V564.3=5Aµ
I
LI
tnerruCwoLtupnI 1LES_F,RMV
CC
V,V564.3=
NI
V0=5-Aµ
0LES_F,LES_LLPV
CC
V,V564.3=
NI
V0=051-Aµ
TABLE 3C. LVPECL DC CHARACTERISTICS, VCC = VCCA = 3.3V±5%, TA = 0°C TO 70°C
lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU
V
HO
1ETON;egatloVhgiHtuptuOV
CC
4.1-V
CC
0.1-V
V
LO
1ETON;egatloVwoLtuptuOV
CC
0.2-V
CC
7.1-V
V
GNIWS
gniwSegatloVtuptuOkaeP-ot-kaeP 6.00.1V
05htiwdetanimretstuptuO:1ETON ΩVot
CC
.V2-
lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU
V
CC
egatloVylppuSeroC 531.33.3564.3V
V
ACC
egatloVylppuSgolanA 531.33.3564.3V
I
EE
tnerruCylppuSrewoP 531Am
I
ACC
tnerruCylppuSgolanA 02Am
ABSOLUTE MAXIMUM RATINGS
Supply V oltage, VCCX 4.6V
Inputs, VCC -0.5V to VCC + 0.5 V
Outputs, VCC -0.5V to VCC + 0.5V
Package Thermal Impedance, θJA 50°C/W (0 lfpm)
Storage T emperature, TSTG -65°C to 150°C
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only . Functional
operation of product at these conditions or any conditions be-
yond those listed in the
DC Characteristics
or
AC Character-
istics
is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability .
84324AM www.icst.com/products/hiperclocks.html REV. A JANUARY 22, 2003
4
Integrated
Circuit
Systems, Inc.
ICS84324
CRYSTAL-TO-3.3V LVPECL
FREQUENCY SYNTHESIZER WITH FANOUT BUFFER
PRELIMINARY
TABLE 4. CRYSTAL CHARACTERISTICS
retemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU
noitallicsOfoedoM latnemadnuF
ycneuqerF 52zHM
)RSE(ecnatsiseRseireStnelaviuqE 07 Ω
ecnaticapaCtnuhS 7Fp
lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU
F
TUO
ycneuqerFtuptuO521.35521zHM
t
)cc(tij2ETON;rettiJelcyC-ot-elcyC 52sp
t
)o(ks2,1ETON;wekStuptuO DBTsp
t
R
emiTesiRtuptuO%08ot%02002056sp
t
F
emiTllaFtuptuO%08ot%02002056sp
cdoelcyCytuDtuptuO 05%
t
WP
htdiWesluPtuptuOt
DOIREP
DBT-2/t
PDOIRE
DBT+2/sp
t
KCOL
emiTkcoLLLP 1sm
.noitcesnoitamrofnItnemerusaeMretemaraPeeS .snoitidnocdaollauqehtiwdnaegatlovylppusemasehttastuptuoneewtebwekssadenifeD:1ETON VtaderusaeM
CC
.2/ .56dradnatSCEDEJhtiwecnadroccanidenifedsiretemarapsihT:2ETON
TABLE 5. AC CHARACTERISTICS, VCC = VCCA = 3.3V±5%, TA = 0°C TO 70°C
84324AM www.icst.com/products/hiperclocks.html REV. A JANUARY 22, 2003
5
Integrated
Circuit
Systems, Inc.
ICS84324
CRYSTAL-TO-3.3V LVPECL
FREQUENCY SYNTHESIZER WITH FANOUT BUFFER
PRELIMINARY
TYPICAL PHASE NOISE AT 106.25MHZ
USING A 25MHZ QUARTZ CRYSTAL
637KHz to 10MHz, 4.15ps RMS
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-120
-130
-140
-150
-160
-170
-180
-1901 100 1k 10k 100k 1M 10M 100M
Process Result
10.000
40.000M
106.250M
Hz
Hz
Hz
Noise only
sec. rms
4.15p
Start Freq.
Stop Freq.
Freq. carrier
Source
Mode
Integral
Execute Plot
84324AM www.icst.com/products/hiperclocks.html REV. A JANUARY 22, 2003
6
Integrated
Circuit
Systems, Inc.
ICS84324
CRYSTAL-TO-3.3V LVPECL
FREQUENCY SYNTHESIZER WITH FANOUT BUFFER
PRELIMINARY
3.3V OUTPUT LOAD AC TEST CIRCUIT OUTPUT SKEW
odc & tPERIOD
SCOPE
Qx
nQx
LVPECL
tsk(o)
Qy
Qx
Q0:Q5
➤
➤
➤
➤
Cycle-to-Cycle Jitter
t
jit(cc) =
t
cycle n –
t
cycle n+1
1000 Cycles
t
cycle n
t
cycle n+1
OUTPUT RISE/FALL TIME
Pulse Width
t
PERIOD
t
PW
t
PERIOD
odc =
Q0:Q5
Clock Outputs 20%
80% 80%
20%
t
R
t
F
PARAMETER MEASUREMENT INFORMATION
nQ0:nQ5
nQ0:nQ5
VCC, VCCA = 2V
VEE = -1.3V ± 0.165
nQy
nQx
84324AM www.icst.com/products/hiperclocks.html REV. A JANUARY 22, 2003
7
Integrated
Circuit
Systems, Inc.
ICS84324
CRYSTAL-TO-3.3V L VPECL
FREQUENCY SYNTHESIZER WITH FANOUT BUFFER
PRELIMINARY
APPLICATION INFORMATION
As in any high speed analog circuitry , the power supply pins
are vulnerable to random noise. The ICS84324 provides sepa-
rate power supplies to isolate any high switching
noise from the outputs to the internal PLL. VCC and V CCA should
be individually connected to the power supply
plane through vias, and bypass capacitors should be
used for each pin. To achieve optimum jitter performance,
power supply isolation is required.
Figure 2
illustrates how
a 10Ω resistor along with a 10µF and a .01µF bypass
capacitor should be connected to each VCCA pin.
POWER SUPPLY FILTERING TECHNIQUES
FIGURE 2. P OWER SUPPLY FILTERING
10Ω
VCCA 10 µF
.01µF
3.3V
.01µF
VCC
CRYSTAL INPUT INTERFACE
A crystal can be characterized for either series or parallel mode
operation. The ICS84324 has a built-in crystal oscillator circuit.
This interface can accept either a series or parallel crystal without
additional components and generate frequencies with accuracy
Figure 3. CRYSTAL INPUt INTERFACE
suitable for most applications. Additional accuracy can be
achieved by adding two small capacitors C1 and C2 as shown in
Figure 3
.
C2
22pF
C1
18pF
25MHz X1
ICS84324
19
20
XTAL2
XTAL1
84324AM www.icst.com/products/hiperclocks.html REV. A JANUARY 22, 2003
8
Integrated
Circuit
Systems, Inc.
ICS84324
CRYSTAL-TO-3.3V LVPECL
FREQUENCY SYNTHESIZER WITH FANOUT BUFFER
PRELIMINARY
The clock layout topology shown below is a typical termina-
tion for L VPECL outputs. The two different layouts mentioned
are recommended only as guidelines.
FOUT and nFOUT are low impedance follower outputs that
generate ECL/L VPECL compatible outputs. Therefore, terminat-
ing resistors (DC current path to ground) or current sources
must be used for functionality. These outputs are designed to
FIGURE 4B. LVPECL OUTPUT TERMINATION
3.3V
FOUT FIN
52Zo
Zo
52
Zo
32Zo
32
Zo = 50Ω
Zo = 50Ω
FIGURE 4A. LVPECL O UTPUT TERMINATION
RTT = 1
(VOH + VOL / VCC –2) –2Zo
Zo = 50Ω
Zo = 50Ω
50Ω
50Ω
RTT
VCC - 2V
FIN
FOUT
➤
drive 50Ω transmission lines. Matched impedance techniques
should be used to maximize operating frequency and minimize
signal distortion.
Figures 4A and 4B
show two different layouts
which are recommended only as guidelines. Other suitable clock
layouts may exist and it would be recommended that the board
designers simulate to guarantee compatibility across all printed
circuit and clock component process variations.
TERMINATION FOR LVPECL OUTPUTS
84324AM www.icst.com/products/hiperclocks.html REV. A JANUARY 22, 2003
9
Integrated
Circuit
Systems, Inc.
ICS84324
CRYSTAL-TO-3.3V L VPECL
FREQUENCY SYNTHESIZER WITH FANOUT BUFFER
PRELIMINARY
POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS84324.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS84324 is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for VCC = 3.3V + 5% = 3.465V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
•Power (core)MAX = VCC_MAX * IEE_MAX = 3.465V * 135mA = 468mW
•Power (outputs)MAX = 30.2mW/Loaded Output pair
If all outputs are loaded, the total power is 6 * 30.2mW = 181mW
Total Power_MAX (3.465V, with all outputs switching) = 468mW + 181mW = 649mW
2. Junction T emperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly af fects the reliability of the
device. The maximum recommended junction temperature for HiPerClockSTM devices is 125°C.
The equation for Tj is as follows: Tj = θJA * Pd_total + TA
Tj = Junction Temperature
θJA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
TA = Ambient T emperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming a
moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 43°C/W per Table 6 below.
Therefore, Tj for an ambient temperature of 70°C with all outputs switching is:
70°C + 0.649W * 43°C/W = 98°C. This is well below the limit of 125°C
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow ,
and the type of board (single layer or multi-layer).
qJA by V elocity (Linear Feet per Minute)
0 200 500
Multi-Layer PCB, JEDEC Standard Test Boards 50°C/W 43°C/W 38°C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
TABLE 6. THERMAL RESISTANCE qJA FOR 24-PIN SOIC, FORCED CONVECTION
84324AM www.icst.com/products/hiperclocks.html REV. A JANUARY 22, 2003
10
Integrated
Circuit
Systems, Inc.
ICS84324
CRYSTAL-TO-3.3V LVPECL
FREQUENCY SYNTHESIZER WITH FANOUT BUFFER
PRELIMINARY
3. Calculations and Equations.
The purpose of this section is to derive the power dissipated into the load.
L VPECL output driver circuit and termination are shown in
Figure 5.
To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load, and a termination
voltage of VCC- 2V .
•For logic high, V OUT = V OH_MAX = VCC_MAX – 1.0V
(VCC_MAX - VOH_MAX) = 1.0V
•For logic low , V OUT = V OL_MAX = VCC_MAX – 1.7V
(VCC_MAX - VOL_MAX) = 1.7V
Pd_H is power dissipation when the output drives high.
Pd_L is the power dissipation when the output drives low .
Pd_H = [(VOH_MAX – (VCC_MAX - 2V))/RL] * (VCC_MAX - VOH_MAX) = [(2V - (VCC_MAX - VOH_MAX))/RL] * (VCC_MAX - VOH_MAX) =
[(2V - 1V)/50Ω) * 1V = 20.0mW
Pd_L = [(VOL_MAX – (VCC_MAX - 2V))/RL] * (VCC_MAX - VOL_MAX) = [(2V - (VCC_MAX - VOL_MAX))/RL] * (VCC_MAX - VOL_MAX) =
[(2V - 1.7V)/50Ω) * 1.7V = 10.2mW
Total Power Dissipation per output pair = Pd_H + Pd_L = 30.2mW
FIGURE 5. LVPECL DRIVER CIRCUIT AND TERMINATION
Q1
VOUT
VCC
RL
50
VCC - 2V
84324AM www.icst.com/products/hiperclocks.html REV. A JANUARY 22, 2003
11
Integrated
Circuit
Systems, Inc.
ICS84324
CRYSTAL-TO-3.3V L VPECL
FREQUENCY SYNTHESIZER WITH FANOUT BUFFER
PRELIMINARY
RELIABILITY INFORMATION
TRANSISTOR COUNT
The transistor count for ICS84324 is: 2882
TABLE 7. θJAVS. AIR FLOW TABLE
qJA by V elocity (Linear Feet per Minute)
0 200 500
Multi-Layer PCB, JEDEC Standard Test Boards 50°C/W 43°C/W 38°C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
84324AM www.icst.com/products/hiperclocks.html REV. A JANUARY 22, 2003
12
Integrated
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Systems, Inc.
ICS84324
CRYSTAL-TO-3.3V LVPECL
FREQUENCY SYNTHESIZER WITH FANOUT BUFFER
PRELIMINARY
PACKAGE OUTLINE - M SUFFIX
TABLE 8. PACKAGE DIMENSIONS
Reference Document: JEDEC Publication 95, MS-013, MO-119
LOBMYS sretemilliM
muminiMmumixaM
N42
A--56.2
1A01.0--
2A50.255.2
B33.015.0
C81.023.0
D02.5158.51
E04.706.7
eCISAB72.1
H00.0156.01
h52.057.0
L04.072.1
α°0°8
84324AM www.icst.com/products/hiperclocks.html REV. A JANUARY 22, 2003
13
Integrated
Circuit
Systems, Inc.
ICS84324
CRYSTAL-TO-3.3V L VPECL
FREQUENCY SYNTHESIZER WITH FANOUT BUFFER
PRELIMINARY
TABLE 9. ORDERING INFORMATION
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use
or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use
in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are
not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS
product for use in life support devices or critical medical instruments.
rebmuNredrO/traPgnikraMegakcaPtnuoCerutarepmeT
MA42348SCIMA42348SCICIOSdaeL42ebutrep03C°07otC°0
TMA42348SCIMA42348SCIleeRdnaepaTnoCIOSdaeL420001C°07otC°0
