32K X 8 BIT LOW POWER CMOS SRAM
FEATURES
Access time : 55ns
Low power consumption:
Operation current :
15mA (TYP.), VCC = 3.0V
Standby current :
1µA (TYP.), VCC = 3.0V
Fully Compatible with all Competitors 5V product
Fully static operation
Tri-state output
Data retention voltage :1.5V (MIN.)
All products ROHS Compliant
Package : 28-pin 600 mil PDIP
28-pin 330 mil SOP
28-pin 8mm x 13.4mm sTSOP
GENERAL DESCRIPTION
The AS6C62256 is a 262,144-bit low power CMOS
static random access memory organized as 32,768
words by 8 bits. It is fabricated using very high
performance, high reliability CMOS technology. Its
standby current is stable within the range of
operating temperature.
The AS6C62256 is well designed for low power
application, and particularly well suited for battery
back-up nonvolatile memory application.
The AS6C62256 operates with wide range power
supply 2.7 ~ 5.5V
.
FUNCTIONAL BLOCK DIAGRAM
DECODER
I/O DATA
CIRCUIT
CONTROL
CIRCUIT
32Kx8
MEMORY ARRAY
COLUMN I/O
A0-A14
Vcc
Vss
DQ0-DQ7
CE#
WE#
OE#
PIN DESCRIPTION
SYMBOL DESCRIPTION
A0 - A14 Address Inputs
DQ0 – DQ7 Data Inputs/Outputs
CE# Chip Enable Input
WE# Write Enable Input
OE# Output Enable Input
VCC Power Supply
VSS Ground
®
Wide range power supply : 2.7 ~ 5.5V
Fully Compatible with all Competitors 3.3V product
February 2007
AS6C62256
02/FEB/07, v1.0
Alliance Memory Inc.
Page 1 of 12
All inputs and outputs TTL compatible
®
32K X 8 BIT LOW POWER CMOS SRAM
PIN CONFIGURATION
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
Vss
A14 Vcc
A8
A9
A11
A10
DQ7
DQ6
DQ5
DQ4
DQ3
AS6C62256
PDIP/SOP
28
14
13
12
11
10
9
8
7
6
5
4
3
2
1
17
16
15
20
19
18
22
23
24
25
26
27
21
A13
CE#
OE#
WE#
sTSOP
DQ3
A11
A9
A8
A13
DQ2
A10
A14
A12
A7
A6
A5
Vcc
DQ7
DQ6
DQ5
DQ4
Vss
DQ1
DQ0
A0
A1
A2
A4
A3
AS6C62256
28
14
13
12
11
10
9
8
7
6
5
4
3
2
1
17
16
15
20
19
18
22
23
24
25
26
27
21
OE#
WE#
CE#
ABSOLUTE MAXIMUM RATINGS*
PARAMETER SYMBOL RATING UNIT
Terminal Voltage with Respect to VSS VTERM -0.5 to 7.0 V
0 to 70(C grade)
TerutarepmeTgnitarepO A
-40 to 85(I grade)
TerutarepmeTegarotS STG -65 to 150
PnoitapissiDrewoP D1 W
ItnerruCtuptuOCD OUT 50 mA
Soldering Temperature (under 10 sec) TSOLDER 260
*Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress
rating only and functional operation of the device or any other conditions above those indicated in the operational sections of this
specification is not implied. Exposure to the absolute maximum rating conditions for extended period may affect device reliability.
TRUTH TABLE
MODE CE# OE# WE# I/O OPERATION SUPPLY CURRENT
Standby H X X High-Z ISB,ISB1
Output Disable L H H High-Z ICC,ICC1
Read L L H DOUT ICC,ICC1
Write L X L DIN ICC,ICC1
Note: H = VIH, L = VIL, X = Don't care.
ºC
ºC
ºC
February 2007
AS6C62256
02/FEB/07, v1.0
Alliance Memory Inc.
Page 2 of 12
®
32K X 8 BIT LOW POWER CMOS SRAM
DC ELECTRICAL CHARACTERISTICS
PARAMETER SYMBOL TEST CONDITION MIN. TYP. *5 MAX. UNIT
SupplyVoltageVCCV5.53.37.2
InputHighVoltageVIH*1V-V
2.4 CC+0.5 V
InputLowVoltageVIL*2V6.0-5.0-
Input Leakage Current ILI VCC VIN VSS - 1 - 1 µA
Output Leakage
Current ILO VCC VOUT VSS,
Output Disabled - 1 - 1 µA
Output High Voltage VOH IOH = -1mA 2.4 3.0 - V
Output Low Voltage VOL IOL = 2mA - - 0.4 V
-55 - 15 45 mA
ICC Cycle time = Min.
CE# = VIL , II/O = 0mA .
Average Operating
Power supply Current
ICC1
Cycle time = 1µs
CE#≦0.2V and II/O = 0mA
other pins at 0.2V or VCC-0.2V
- 3 10 mA
ISB CE# = VIH Am31-
-C - 1 50*4 µA
Standby Power
Supply Current ISB1 CE# VCC - 0.2V -I - 1 80
*4 µA
Notes: C = Commercial Temperature I = Industrial Temperature
1. VIH(max) = VCC + 3.0V for pulse width less than 10ns.
2. VIL(min) = VSS - 3.0V for pulse width less than 10ns.
3. Over/Undershoot specifications are characterized, not 100% tested.
4. 10µA for special request
5. Typical values are included for reference only and are not guaranteed or tested.
Typical valued are measured at VCC = VCC(TYP.) and TA= 25ºC
CAPACITANCE (TA= 25 , f?= 1.0MHz)
PARAMETER SYMBOL MIN. MAX UNIT
Input Capacitance CIN -6 pF
Input/Output Capacitance CI/O -8 pF
Note : These parameters are guaranteed by device characterization, but not production tested.
AC TEST CONDITIONS
VotV2.0sleveLesluPtupnI CC - 0.2V
sn3semiTllaFdnaesiRtupnI
Input and Output Timing Reference Levels 1.5V
CdaoLtuptuO L= 50pF + 1TTL, IOH/IOL = -1mA/2mA
February 2007
AS6C62256
02/FEB/07, v1.0
Alliance Memory Inc.
Page 3 of 12
>=
>=
>=
>=
>=
®
32K X 8 BIT LOW POWER CMOS SRAM
AC ELECTRICAL CHARACTERISTICS
(1) READ CYCLE AS6C62256-55
PARAMETER SYM MIN MAX. UNIT
Read Cycle Time tRC 55 - ns
Address Access Time tAA - 55 ns
Chip Enable Access Time tACE - 55 ns
Output Enable Access Time tOE - 30 ns
Chip Enable to Output in Low-Z tCLZ* 10 - ns
Output Enable to Output in Low-Z tOLZ* 5 - ns
Chip Disable to Output in High-Z tCHZ* - 20 ns
Output Disable to Output in High-Z tOHZ* - 20 ns
Output Hold from Address Change tOH 10 - ns
(2) WRITE CYCLE AS6C62256-55
PARAMETER SYM MIN. MAX. UNIT
Write Cycle Time tWC 55 - ns
Address Valid to End of Write tAW 50 - ns
Chip Enable to End of Write tCW 50 - ns
Address Set-up Time tAS 0 - ns
Write Pulse Width tWP 45 - ns
Write Recovery Time tWR 0 - ns
Data to Write Time Overlap tDW 25 - ns
Data Hold from End of Write Time tDH 0 - ns
Output Active from End of Write tOW* 5 - ns
Write to Output in High-Z tWHZ* - 20 ns
*These parameters are guaranteed by device characterization, but not production tested.
February 2007
AS6C62256
02/FEB/07, v1.0
Alliance Memory Inc.
Page 4 of 12
®
32K X 8 BIT LOW POWER CMOS SRAM
TIMING WAVEFORMS
READ CYCLE 1 (Address Controlled) (1,2)
Dout Data Valid
tOHtAA
Address
tRC
Previous Data Valid
READ CYCLE 2 (CE# and OE# Controlled) (1,3,4,5)
Dout Data Valid
tOH
OE#
tACE
CE#
tAA
Address
tRC
High-ZHigh-Z
tCLZ
tOLZ
tOE
tCHZ
tOHZ
Notes :
1.WE# is high for read cycle.
2.Device is continuously selected OE# = low, CE# = low.
3.Address must be valid prior to or coincident with CE# = low,; otherwise tAA is the limiting parameter.
4.tCLZ, tOLZ, tCHZ and tOHZ are specified with CL= 5pF. Transition is measured ±500mV from steady state.
5.At any given temperature and voltage condition, tCHZ is less than tCLZ , tOHZ is less than tOLZ.
February 2007
AS6C62256
02/FEB/07, v1.0
Alliance Memory Inc.
Page 5 of 12
®
32K X 8 BIT LOW POWER CMOS SRAM
WRITE CYCLE 1 (WE# Controlled) (1,2,3,5,6)
Dout
Din Data Valid
tDW tDH
(4) High-Z
tWHZ
WE#
tWP
tCW
CE#
tWRtAS
tAW
Address
tWC
(4)
TOW
WRITE CYCLE 2 (CE# Controlled) (1,2,5,6)
Dout
Din Data Valid
tDW tDH
(4) High-Z
tWHZ
WE#
tWP
tCW
CE# tWRtAS
tAW
Address
tWC
Notes :
1.WE#, CE# must be high during all address transitions.
2.A write occurs during the overlap of a low CE#, low WE#.
3.During a WE# controlled write cycle with OE# low, tWP must be greater than tWHZ + tDW to allow the drivers to turn off and data to be
placed on the bus.
4.During this period, I/O pins are in the output state, and input signals must not be applied.
5.If the CE# low transition occurs simultaneously with or after WE# low transition, the outputs remain in a high impedance state.
6.tOW and tWHZ are specified with CL = 5pF. Transition is measured ±500mV from steady state.
February 2007
AS6C62256
02/FEB/07, v1.0
Alliance Memory Inc.
Page 6 of 12
®
32K X 8 BIT LOW POWER CMOS SRAM
DATA RETENTION CHARACTERISTICS
PARAMETER SYMBOL TEST CONDITION MIN. TYP. MAX. UNIT
VCC for Data Retention VDR CE# V≧CC - 0.2V 1.5 - 5.5 V
Data Retention Current IDR VCC = 2.0V
CE# V≧CC - 0.2V - 0.5 20 µA
Chip Disable to Data
Retention Time tCDR See Data Retention
Waveforms (below) 0 - - ns
Recovery Time tRt RC* - - ns
tRC* = Read Cycle Time
DATA RETENTION WAVEFORM
Vcc
CE#
VDR ≧1.5V
CE# V≧cc-0.2V
Vcc(min.)
VIH
tRtCDR
VIH
Vcc(min.)
February 2007
AS6C62256
02/FEB/07, v1.0
Alliance Memory Inc.
Page 7 of 12
®
32K X 8 BIT LOW POWER CMOS SRAM
PACKAGE OUTLINE DIMENSION
28 pin 600 mil PDIP Package Outline Dimension
UNIT
SYM. INCH.(BASE) MM(REF)
A1 0.010 (MIN) 0.254 (MIN)
A2 0.150±0.005 3.810±0.127
B 0.020 (MAX) 0.508(MAX)
B1 0.055 (MAX) 1.397(MAX)
c 0.012 (MAX) 0.304 (MAX)
D 1.430 (MAX) 36.322 (MAX)
E 0.6 (TYP) 15.24 (TYP)
E1 0.52 (MAX) 13.208 (MAX)
e 0.100 (TYP) 2.540(TYP)
eB 0.625 (MAX) 15.87 (MAX)
L 0.180(MAX) 4.572(MAX)
S 0.06 (MAX) 1.524 (MAX)
Q1 0.08(MAX) 2.032(MAX)
Θ 15o(MAX) 15o(MAX)
February 2007
AS6C62256
02/FEB/07, v1.0
Alliance Memory Inc.
Page 8 of 12
®
32K X 8 BIT LOW POWER CMOS SRAM
28 pin 330 mil SOP Package Outline Dimension
UNIT
SYM. INCH(BASE) MM(REF)
A 0.120 (MAX) 3.048 (MAX)
A1 0.002(MIN) 0.05(MIN)
A2 0.098±0.005 2.489±0.127
b 0.016 (TYP) 0.406(TYP)
c 0.010 (TYP) 0.254(TYP)
D 0.728 (MAX) 18.491 (MAX)
E 0.340 (MAX) 8.636 (MAX)
E1 0.465±0.012 11.811±0.305
e 0.050 (TYP) 1.270(TYP)
L 0.05 (MAX) 1.270 (MAX)
L1 0.067±0.008 1.702 ±0.203
S 0.047 (MAX) 1.194 (MAX)
y 0.003(MAX) 0.076(MAX)
Θ0o～10o 0o～10o
February 2007
AS6C62256
02/FEB/07, v1.0
Alliance Memory Inc.
Page 9 of 12
®
32K X 8 BIT LOW POWER CMOS SRAM
28 pin 8mm x 13.4mm sTSOP Package Outline Dimension
UNIT
SYM. INCH(BASE) MM(REF)
A 0.047 (MAX) 1.20 (MAX)
A1 0.004±0.002 0.10±0.05
A2 0.039±0.002 1.00±0.05
b 0.006 (TYP) 0.15(TYP)
c 0.010 (TYP) 0.254(TYP)
Db 0.465±0.004 11.80±0.10
E 0.315±0.004 8.00±0.10
e 0.022 (TYP) 0.55(TYP)
D 0.528±0.008 13.40±0.20
L 0.020±0.004 0.50±0.10
L1 0.0315±0.004 0.80±0.10
y 0.08(MAX) 0.003(MAX)
Θ0o～5o 0o～5o
Note：E dimension is not including end flash. The total of both sides’ end flash is not above 0.3mm.
February 2007
AS6C62256
02/FEB/07, v1.0
Alliance Memory Inc.
Page 10 of 12
®
32K X 8 BIT LOW POWER CMOS SRAM
ORDERING INFORMATION
Ordering Codes
Part numbering system
AS6C 62256 - 55 X X N
Temperature Range:
C = Commercial
(0ºC to +70º C)
I = Industrial
(-40º to +85º C)
N = Lead
Free ROHS
Compliant
Part
low
power
SRAM
prefix
Device
Number
62256
Access
Time
Package Options:
P = 28 pin 600 mil P-DIP
S = 28 pin 330 mil SOP
ST = 28 pin sTSOP (8mm x 13.4 mm)
February 2007
AS6C62256
02/FEB/07, v1.0
Alliance Memory Inc.
Page 11 of 12
Alliance Organization VCC range Package
Operating
Temp
Speed
ns
AS6C62256-55PCN 32k x 8 2.7-5.5V 28pin 600mil PDIP
Commercial ~
0º C to 70º C
55
AS6C62256-55SCN 32k x 8 2.7-5.5V 28pin 330mil SOP
Commercial ~
0º C to 70º C
55
AS6C62256-55SIN 32k x 8 2.7-5.5V 28pin 330mil SOP
Industrial ~
-40ºC to 85º C
55
AS6C62256-55STCN 32k x 8 2.7-5.5V 28pin sTSOP (8 x 13.4 mm)
Commercial ~
0º C to 70º C
55
AS6C62256-55STIN 32k x 8 2.7-5.5V 28pin sTSOP (8 x 13.4 mm)
Industrial ~
-40ºC to 85º C
55
Rev 1
®
Alliance Memory, Inc.
1116 South Amphlett, #2,
San Mateo, CA 94402
Tel: 650-525-3737
Fax: 650-525-0449
www.alliancememory.com
Copyright © Alliance Memory
All Rights Reserved
Part Number: AS6C62256
Document Version: v. 1.0
© Copyright 2003 Alliance Memory, Inc. All rights reserved. Our three-point logo, our name and Intelliwatt are trademarks or registered trademarks of
Alliance. All other brand and product names may be the trademarks of their respective companies. Alliance reserves the right to make changes to this
document and its products at any time without notice. Alliance assumes no responsibility for any errors that may appear in this document. The data
contained herein represents Alliance's best data and/or estimates at the time of issuance. Alliance reserves the right to change or correct this data at any
time, without notice. If the product described herein is under development, significant changes to these specifications are possible. The information in
this product data sheet is intended to be general descriptive information for potential customers and users, and is not intended to operate as, or provide,
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trademarks, or any other intellectual property rights of Alliance or third parties. Alliance does not authorize its products for use as critical components in
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claims arising from such use.
®
February 2007
AS6C62256
02/FEB/07, v1.0
Alliance Memory Inc.
Page 12 of 12
