TLC1543QDWG4 - Texas Instruments - Datasheet.Directory

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FEATURES

DESCRIPTION

GND

VCC

EOC

I/O CLOCK

ADDRESS

DATA OUT

REF+

REF−

A10

DB, DW, J, OR N PACKAGE

(TOP VIEW)

3 2 1 20 19

9 10 11 12 13

I/O CLOCK

ADDRESS

DATA OUT

REF+

FK OR FN PACKAGE

(TOP VIEW)

A10

REF − EOC

GND

A9 VCC

TLC1542I , , TLC1542M , , TLC1542QTLC1542C , TLC1543C , TLC1543I , TLC1543Q

SLAS052G – MARCH 1992 – REVISED JANUARY 2006

10-BIT ANALOG-TO-DIGITAL CONVERTERSWITH SERIAL CONTROL AND 11 ANALOG INPUTS

•10-Bit Resolution A/D Converter•11 Analog Input Channels•Three Built-In Self-Test Modes•Inherent Sample-and-Hold Function•Total Unadjusted Error: ±1LSB Max•On-Chip System Clock•End-of-Conversion (EOC) Output•Terminal Compatible With TLC542•CMOS Technology

The TLC1542C, TLC1542I, TLC1542M, TLC1542Q,TLC1543C, TLC1543I, and TLC1543Q are CMOS10-bit switched-capacitor successive-approximationanalog-to-digital converters. These devices havethree inputs and a 3-state output [chip select ( CS),input-output clock (I/O CLOCK), address input(ADDRESS), and data output (DATA OUT)] thatprovide a direct 4-wire interface to the serial port of ahost processor. These devices allow high-speed datatransfers from the host.

In addition to a high-speed A/D converter andversatile control capability, these devices have anon-chip 14-channel multiplexer that can select anyone of 11 analog inputs or any one of three internalself-test voltages. The sample-and-hold function isautomatic. At the end of A/D conversion, theend-of-conversion (EOC) output goes high toindicate that conversion is complete. The converterincorporated in the devices features differentialhigh-impedance reference inputs that facilitateratiometric conversion, scaling, and isolation ofanalog circuitry from logic and supply noise. Aswitched-capacitor design allows low-errorconversion over the full operating free-airtemperature range.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Copyright © 1992–2006, Texas Instruments IncorporatedProducts conform to specifications per the terms of the TexasInstruments standard warranty. Production processing does notnecessarily include testing of all parameters.

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14-Channel

Analog

Multiplexer

REF+ REF−

DATA

OUT

ADDRESS

I/O CLOCK

EOC

A10

14 13

10-Bit

Analog-to-Digital

Converter

(switched capacitors)

Sample and

Hold

Input Address

Self-Test

Reference

Output

Data

System Clock,

Control Logic,

and I/O

Counters

10-to-1 Data

Selector and

Driver

TYPICAL EQUIVALENT INPUTS

INPUT CIRCUIT IMPEDANCE DURING SAMPLING MODE INPUT CIRCUIT IMPEDANCE DURING HOLD MODE

1 kΩ TYP

Ci = 60 pF TYP

(equivalent input

capacitance)

5 MΩ TYP

A0−A10 A0−A10

TLC1542I , , TLC1542M , , TLC1542QTLC1542C , TLC1543C , TLC1543I , TLC1543Q

SLAS052G – MARCH 1992 – REVISED JANUARY 2006

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foamduring storage or handling to prevent electrostatic damage to the MOS gates.

AVAILABLE OPTIONS

PACKAGE

SMALLT

SMALL OUTLINE CHIP CARRIER PLASTIC DIP CHIP CARRIER CERAMIC DIPOUTLINE

(DW) (FN) (N) (FK) (J)(DB)

TLC1542CDW TLC1542CFN TLC1542CN0°C to 70 °C

TLC1543CDB TLC1543CDW TLC1543CFN TLC1543CNTLC1542IDW TLC1542IFN TLC1542IN-40 °C to 85 °C

TLC1543IDB TLC1543IDW TLC1543IFN TLC1543INTLC1542QFN-40 °C to 125 °C

TLC1543QDB TLC1543QDW TLC1543QFN-55 °C to 125 °C TLC1542MFK TLC1542MJ

FUNCTIONAL BLOCK DIAGRAM

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DETAILED DESCRIPTION

TLC1542I , , TLC1542M , , TLC1542QTLC1542C , TLC1543C , TLC1543I , TLC1543Q

SLAS052G – MARCH 1992 – REVISED JANUARY 2006

TERMINAL FUNCTIONS

TERMINAL

I/O DESCRIPTIONNAME NO.

ADDRESS 17 I Serial address input. A 4-bit serial address selects the desired analog input or test voltage that is to beconverted next. The address data is presented with the MSB first and shifts in on the first four risingedges of I/O CLOCK. After the four address bits have been read into the address register, this input isignored for the remainder of the current conversion period.A0-A10 1-9, 11, 12 I Analog signal inputs. The 11 analog inputs are applied to these terminals and are internallymultiplexed. The driving source impedance should be less than or equal to 1 k Ω.CS 15 I Chip select. A high-to-low transition on this input resets the internal counters and controls and enablesDATA OUT, ADDRESS, and I/O CLOCK within a maximum of a setup time plus two falling edges ofthe internal system clock. A low-to-high transition disables ADDRESS and I/O CLOCK within a setuptime plus two falling edges of the internal system clock.DATA OUT 16 O The 3-state serial output for the A/D conversion result. This output is in the high-impedance statewhen CS is high and active when CS is low. With a valid chip select, DATA OUT is removed from thehigh-impedance state and is driven to the logic level corresponding to the MSB value of the previousconversion result. The next falling edge of I/O CLOCK drives this output to the logic levelcorresponding to the next most significant bit, and the remaining bits shift out in order with the LSBappearing on the ninth falling edge of I/O CLOCK. On the tenth falling edge of I/O CLOCK, DATAOUT is driven to a low logic level so that serial interface data transfers of more than ten clocksproduce zeroes as the unused LSBs.EOC 19 O End of conversion. This output goes from a high to a low logic level on the trailing edge of the tenthI/O CLOCK and remains low until the conversion is complete and data are ready for transfer.GND 10 I The ground return terminal for the internal circuitry. Unless otherwise noted, all voltage measurementsare with respect to this terminal.I/O CLOCK 18 I Input/output clock. This terminal receives the serial I/O CLOCK input and performs the following fourfunctions: 1) It clocks the four input address bits into the address register on the first four rising edgesof the I/O CLOCK with the multiplex address available after the fourth rising edge. 2) On the fourthfalling edge of I/O CLOCK, the analog input voltage on the selected multiplex input begins chargingthe capacitor array and continues to do so until the tenth falling edge of I/O CLOCK. 3) It shifts thenine remaining bits of the previous conversion data out on DATA OUT. 4) It transfers control of theconversion to the internal state controller on the falling edge of the tenth clock.REF+ 14 I The upper reference voltage value (nominally V

) is applied to this terminal. The maximum inputvoltage range is determined by the difference between the voltage applied to this terminal and thevoltage applied to the REF- terminal.REF- 13 I The lower reference voltage value (nominally ground) is applied to this terminal.V

20 I Positive supply voltage

With chip select ( CS) inactive (high), the ADDRESS and I/O CLOCK inputs are initially disabled and DATA OUTis in the high-impedance state. When the serial interface takes CS active (low), the conversion sequence beginswith the enabling of I/O CLOCK and ADDRESS and the removal of DATA OUT from the high-impedance state.The serial interface then provides the 4-bit channel address to ADDRESS and the I/O CLOCK sequence to I/OCLOCK. During this transfer, the serial interface also receives the previous conversion result from DATA OUT.I/O CLOCK receives an input sequence that is between 10 and 16 clocks long from the host serial interface. Thefirst four I/O clocks load the address register with the 4-bit address on ADDRESS, selecting the desired analogchannel, and the next six clocks providing the control timing for sampling the analog input.

There are six basic serial-interface timing modes that can be used with the device. These modes are determinedby the speed of I/O CLOCK and the operation of CS as shown in Table 1. These modes are (1) a fast mode witha 10-clock transfer and CS inactive (high) between conversion cycles, (2) a fast mode with a 10-clock transferand CS active (low) continuously, (3) a fast mode with an 11- to 16-clock transfer and CS inactive (high)between conversion cycles, (4) a fast mode with a 16-clock transfer and CS active (low) continuously, (5) a slowmode with an 11- to 16-clock transfer and CS inactive (high) between conversion cycles, and (6) a slow modewith a 16-clock transfer and CS active (low) continuously.

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FAST MODES

MODE 1: FAST MODE, CS INACTIVE (HIGH) BETWEEN CONVERSION CYCLES, 10-CLOCK TRANSFER

MODE 2: FAST MODE, CS ACTIVE (LOW) CONTINUOUSLY, 10-CLOCK TRANSFER

MODE 3: FAST MODE, CS INACTIVE (HIGH) BETWEEN CONVERSION CYCLES, 11- to 16-CLOCK

TLC1542I , , TLC1542M , , TLC1542QTLC1542C , TLC1543C , TLC1543I , TLC1543Q

SLAS052G – MARCH 1992 – REVISED JANUARY 2006

The MSB of the previous conversion appears at DATA OUT on the falling edge of CS in mode 1, mode 3, andmode 5, on the rising edge of EOC in mode 2 and mode 4, and following the sixteenth clock falling edge inmode 6. The remaining nine bits are shifted out on the next nine falling edges of I/O CLOCK. Ten bits of dataare transmitted to the host-serial interface through DATA OUT. The number of serial clock pulses used alsodepends on the mode of operation, but a minimum of ten clock pulses is required for conversion to begin. Onthe tenth clock falling edge, the EOC output goes low and returns to the high logic level when conversion iscomplete and the result can be read by the host. Also, on the tenth clock falling edge, the internal logic takesDATA OUT low to ensure that the remaining bit values are zero when the I/O CLOCK transfer is more than tenclocks long.

Table 1 lists the operational modes with respect to the state of CS, the number of I/O serial transfer clocks thatcan be used, and the timing edge on which the MSB of the previous conversion appears at the output.

Table 1. MODE OPERATION

TIMINGMODES CS NO. OF 1/O CLOCK MSB AT DATA OUT

(1)

DIAGRAM

Mode 1 High between conversion cycles 10 CS falling edge Figure 9Mode 2 Low continuously 10 EOC rising edge Figure 10Fast Modes

Mode 3 High between conversion cycles 11 TO 16

(2)

CS falling edge Figure 11Mode 4 Low continuously 16

(2)

EOC rising edge Figure 12Mode 5 High between conversion cycles 11 to 16

(3)

CS falling edge Figure 13Slow Modes

Mode 6 Low continuously 16

(3)

16th clock falling edge Figure 14

(1) These edges also initiate serial-interface communication.(2) No more than 16 clocks should be used.(3) No more than 16 clocks should be used.

The device is in a fast mode when the serial I/O CLOCK data transfer is completed before the conversion iscompleted. With a 10-clock serial transfer, the device can only run in a fast mode since a conversion does notbegin until the falling edge of the tenth I/O CLOCK.

In this mode, CS is inactive (high) between serial I/O CLOCK transfers and each transfer is ten clocks long. Thefalling edge of CS begins the sequence by removing DATA OUT from the high-impedance state. The rising edgeof CS ends the sequence by returning DATA OUT to the high-impedance state within the specified delay time.Also, the rising edge of CS disables the I/O CLOCK and ADDRESS terminals within a setup time plus two fallingedges of the internal system clock.

In this mode, CS is active (low) between serial I/O CLOCK transfers and each transfer is ten clocks long. Afterthe initial conversion cycle, CS is held active (low) for subsequent conversions; the rising edge of EOC thenbegins each sequence by removing DATA OUT from the low logic level, allowing the MSB of the previousconversion to appear immediately on this output.

TRANSFER

In this mode, CS is inactive (high) between serial I/O CLOCK transfers, and each transfer can be 11 to 16 clockslong. The falling edge of CS begins the sequence by removing DATA OUT from the high-impedance state. Therising edge of CS ends the sequence by returning DATA OUT to the high-impedance state within the specifieddelay time. Also, the rising edge of CS disables the I/O CLOCK and ADDRESS terminals within a setup timeplus two falling edges of the internal system clock.

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MODE 4: FAST MODE, CS ACTIVE (LOW) CONTINUOUSLY, 16-CLOCK TRANSFER

SLOW MODES

MODE 5: SLOW MODE, CS INACTIVE (HIGH) BETWEEN CONVERSION CYCLES, 11- to 16-CLOCK

MODE 6: SLOW MODE, CS ACTIVE (LOW) CONTINUOUSLY, 16-CLOCK TRANSFER

ADDRESS BITS

ANALOG INPUTS AND TEST MODES

TLC1542I , , TLC1542M , , TLC1542QTLC1542C , TLC1543C , TLC1543I , TLC1543Q

SLAS052G – MARCH 1992 – REVISED JANUARY 2006

In this mode, CS is active (low) between serial I/O CLOCK transfers and each transfer must be exactly 16 clockslong. After the initial conversion cycle, CS is held active (low) for subsequent conversions; the rising edge ofEOC then begins each sequence by removing DATA OUT from the low logic level, allowing the MSB of theprevious conversion to appear immediately on this output.

In a slow mode, the conversion is completed before the serial I/O CLOCK data transfer is completed. A slowmode requires a minimum 11-clock transfer into I/O CLOCK, and the rising edge of the eleventh clock mustoccur before the conversion period is complete; otherwise, the device loses synchronization with the host-serialinterface and CS has to be toggled to initialize the system. The eleventh rising edge of the I/O CLOCK mustoccur within 9.5 µs after the tenth I/O clock falling edge.

TRANSFER

In this mode, CS is inactive (high) between serial I/O CLOCK transfers and each transfer can be 11 to 16 clockslong. The falling edge of CS begins the sequence by removing DATA OUT from the high-impedance state. Therising edge of CS ends the sequence by returning DATA OUT to the high-impedance state within the specifieddelay time. Also, the rising edge of CS disables the I/O CLOCK and ADDRESS terminals within a setup timeplus two falling edges of the internal system clock.

In this mode, CS is active (low) between serial I/O CLOCK transfers and each transfer must be exactly 16 clockslong. After the initial conversion cycle, CS is held active (low) for subsequent conversions. The falling edge ofthe sixteenth I/O CLOCK then begins each sequence by removing DATA OUT from the low state, allowing theMSB of the previous conversion to appear immediately at DATA OUT. The device is then ready for the next16-clock transfer initiated by the serial interface.

The 4-bit analog channel-select address for the next conversion cycle is presented to the ADDRESS terminal(MSB first) and is clocked into the address register on the first four leading edges of I/O CLOCK. This addressselects one of 14 inputs (11 analog inputs or three internal test inputs).

The 11 analog inputs and the three internal test inputs are selected by the 14-channel multiplexer according tothe input address as shown in Tables 2 and 3. The input multiplexer is a break-before-make type to reduceinput-to-input noise injection resulting from channel switching.

Sampling of the analog input starts on the falling edge of the fourth I/O CLOCK, and sampling continues for sixI/O CLOCK periods. The sample is held on the falling edge of the tenth I/O CLOCK. The three test inputs areapplied to the multiplexer, sampled, and converted in the same manner as the external analog inputs.

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Vref+ − Vref−

CONVERTER AND ANALOG INPUT

TLC1542I , , TLC1542M , , TLC1542QTLC1542C , TLC1543C , TLC1543I , TLC1543Q

SLAS052G – MARCH 1992 – REVISED JANUARY 2006

Table 2. ANALOG-CHANNEL-SELECT ADDRESS

VALUE SHIFTED INTO ADDRESS

INPUTANALOG INPUT SELECTED

BINARY HEX

A0 0000 0A1 0001 1A2 0010 2A3 0011 3A4 0100 4A5 0101 5A6 0110 6A7 0111 7A8 1000 8A9 1001 9A10 1010 A

Table 3. TEST-MODE-SELECT ADDRESS

VALUE SHIFTED INTOINTERNAL SELF-TEST

ADDRESS INPUT

OUTPUT RESULT (HEX)

(2)VOLTAGE SELECTED

(1)

BINARY HEX

1011 B 200

ref-

1100 C 000V

ref+

1101 D 3FF

(1) V

ref+

is the voltage applied to the REF+ input, and V

ref-

is the voltage applied to the REF- input.(2) The output results shown are the ideal values and vary with the reference stability and with internaloffsets.

The CMOS threshold detector in the successive-approximation conversion system determines each bit byexamining the charge on a series of binary-weighted capacitors (see Figure 1). In the first phase of theconversion process, the analog input is sampled by closing the S

switch and all S

switches simultaneously.This action charges all the capacitors to the input voltage.

In the next phase of the conversion process, all S

and S

switches are opened and the threshold detectorbegins identifying bits by identifying the charge (voltage) on each capacitor relative to the reference (REF-)voltage. In the switching sequence, ten capacitors are examined separately until all ten bits are identified andthen the charge-convert sequence is repeated. In the first step of the conversion phase, the threshold detectorlooks at the first capacitor (weight = 512). Node 512 of this capacitor is switched to the REF+ voltage, and theequivalent nodes of all the other capacitors on the ladder are switched to REF-. If the voltage at the summingnode is greater than the trip point of the threshold detector (approximately one-half V

), a 0 bit is placed in theoutput register and the 512-weight capacitor is switched to REF-. If the voltage at the summing node is less thanthe trip point of the threshold detector, a 1 bit is placed in the register and the 512-weight capacitor remainsconnected to REF+ through the remainder of the successive-approximation process. The process is repeated forthe 256-weight capacitor, the 128-weight capacitor, and so forth down the line until all bits are counted.

With each step of the successive-approximation process, the initial charge is redistributed among the capacitors.The conversion process relies on charge redistribution to count and weigh the bits from MSB to LSB.

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Threshold

Detector

Node 512

REF−

REF+

512

To Output

Latches

REF+REF+ REF+ REF+

124816128256 1

REF+ REF+

REF− REF− REF− REF− REF− REF− REF− REF−

STSTSTSTSTSTSTST

CHIP-SELECT OPERATION

REFERENCE VOLTAGE INPUTS

TLC1542I , , TLC1542M , , TLC1542QTLC1542C , TLC1543C , TLC1543I , TLC1543Q

SLAS052G – MARCH 1992 – REVISED JANUARY 2006

Figure 1. Simplified Model of the Successive-Approximation System

The trailing edge of CS starts all modes of operation, and CS can abort a conversion sequence in any mode. Ahigh-to-low transition on CS within the specified time during an ongoing cycle aborts the cycle, and the devicereturns to the initial state (the contents of the output data register remain at the previous conversion result).Exercise care to prevent CS from being taken low close to completion of conversion because the output datacan be corrupted.

There are two reference inputs used with the device: REF+ and REF-. These voltage values establish the upperand lower limits of the analog input to produce a full-scale and zero reading respectively. The values of REF+,REF-, and the analog input should not exceed the positive supply or be lower than GND consistent with thespecified absolute maximum ratings. The digital output is at full scale when the input signal is equal to or higherthan REF+ and at zero when the input signal is equal to or lower than REF-.

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ABSOLUTE MAXIMUM RATINGS

RECOMMENDED OPERATING CONDITIONS

TLC1542I , , TLC1542M , , TLC1542QTLC1542C , TLC1543C , TLC1543I , TLC1543Q

SLAS052G – MARCH 1992 – REVISED JANUARY 2006

over operating free-air temperature range (unless otherwise noted)

(1)

UNIT

, see

(2)

Supply voltage range -0.5 V to 6.5 VV

Input voltage range -0.3 V to V

+ 0.3 VV

Output voltage range -0.3 V to V

+ 0.3 VV

ref+

Positive reference voltage V

+ 0.1 VV

ref-

Negative reference voltage -0.1 VPeak input current (any input) ±20 mAPeak total input current (all inputs) ±30 mATLC1542C, TLC1543C 0 °C to 70 °CTLC1542I, TLC1543I -40 °C to 85 °CT

Operating free-air temperature range

TLC1542Q, TLC1543Q -40 °C to 125 °CTLC1542M -55 °C to 125 °CT

stg

Storage temperature range, -65 °C to 150 °CLead temperature 1,6 mm (1/16 inch) from the case for 10 seconds 260 °C

(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratingsonly, and functional operation of the device at these or any other conditions beyond those indicated under recommended operatingconditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.(2) All voltage values are with respect to digital ground with REF- and GND wired together (unless otherwise noted).

MIN NOM MAX UNIT

Supply voltage 4.5 5 5.5 VV

ref+

, see

(1)

Positive reference voltage V

ref-

, see

(1)

Negative reference voltage 0 VV

+0.V

ref+

-V

ref-

, see

(1)

Differential reference voltage 2.5 V

V2Analog input voltage ,see

(1)

0 V

High-level control input voltage V

= 4.5 V to 5.5 V 2 VV

Low-level control input voltage V

= 4.5 V to 5.5 V 0.8 VSetup time, address bits at data input before I/Ot

su(A)

, see Figure 4 100 nsCLOCK ↑t

h(A)

, see Figure 4 Hold time, address bits after I/O CLOCK ↑0 nst

h(CS)

, see Figure 5 Hold time, CS low after last I/O CLOCK ↓0 nst

su(CS)

, see

(2)

and Setup time, CS low before clocking in first

1.425 µsFigure 5 address bitClock frequency at I/O CLOCK, see

(3)

0 2.1 MHzt

wH(I/O)

Pulse duration, I/O CLOCK high, 190 nst

wL(I/O)

Pulse duration, I/O CLOCK low, 190 nst

t(I/O)

, see

(4)

and

Transition time, I/O CLOCK, 1 µsFigure 6t

t(CS)

Transition time, ADDRESS and CS, 10 µs

(1) Analog input voltages greater than that applied to REF+ convert as all ones (1111111111), while input voltages less than that applied toREF- convert as all zeros (0000000000). The device is functional with reference voltages down to 1 V (V

ref+

- V

ref-

); however, theelectrical specifications are no longer applicable.(2) To minimize errors caused by noise at CS, the internal circuitry waits for a setup time plus two falling edges of the internal system clockafter CS↓before responding to control input signals. Therefore, no attempt should be made to clock in an address until the minimum CSsetup time has elapsed.(3) For 11- to 16-bit transfers, after the tenth I/O CLOCK falling edge ( ≤2 V) at least 1 I/O CLOCK rising edge ( ≥2 V) must occur within 9.5µs.(4) This is the time required for the clock input signal to fall from V

min to V

max or to rise from V

max to V

min. In the vicinity of normalroom temperature, the devices function with input clock transition time as slow as 1 µs for remote data-acquisition applications wherethe sensor and the A/D converter are placed several feet away from the controlling microprocessor.

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ELECTRICAL CHARACTERISTICS

OPERATING CHARACTERISTICS

TLC1542I , , TLC1542M , , TLC1542QTLC1542C , TLC1543C , TLC1543I , TLC1543Q

SLAS052G – MARCH 1992 – REVISED JANUARY 2006

RECOMMENDED OPERATING CONDITIONS (continued)

MIN NOM MAX UNIT

TLC1542C, TLC1543C 0 70TLC1542I, TLC1543I -40 85T

Operating free-air temperature, °CTLC1542Q, TLC1543Q -40 125TLC1542M -55 125

over recommended operating free-air temperature range, V

= V

ref+

= 4.5 V to 5.5 V, I/O CLOCK frequency = 2.1 MHz(unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP

(1)

MAX UNIT

= 4.5 V, I

= -1.6 mA 2.4V

High-level output voltage VV

= 4.5 V to 5.5 V, I

= -20 µA V

-0.1V

= 4.5 V, I

= 1.6 mA 0.4V

Low-level output voltage VV

= 4.5 V to 5.5 V, I

= 20 µA 0.1Off-state V

= V

, CS at V

10I

(high-impedance-state) µAV

= 0, CS at V

-10output currentI

High-level input current V

= V

0.005 2.5 µAI

Low-level input current V

= 0 0.005 -2.5 µAI

Operating supply current CS at 0 V 0.8 2.5 mASelected channel leakage Selected channel at V

, Unselected channel at 0 V 1current TLC1542/TLC1543 µASelected channel at 0 V, Unselected channel at V

-1C, I, or Q

Selected channel at V

Unselected channel at 0 V, 1T

= 25 °CSelected channel at 0 V,Selected channel leakage

Unselected channel at V

, -1

µAT

= 25 °Ccurrent TLC1542M

Selected channel at V

, Unselected channel at 0 V 2.5Selected channel at 0 V, Unselected channel at V

-2.5Maximum static analog

ref+

= V

, V

ref-

= GND 10 µAreference current into REF+

Analog

7inputsInputC

pFcapacitance

Control

5inputs

(1) All typical values are at V

= 5 V, T

= 25 °C.

over recommended operating free-air temperature range, V

= V

ref+

= 4.5 V to 5.5 V, I/O CLOCK frequency = 2.1 MHz(unless otherwise noted)

TEST

MIN TYP

(1)

MAX UNITCONDITIONS

TLC1542C, I, or Q ±0.5 LSBE

Linearity error, see

(2)

) TLC1543C, I, or Q ±1 LSBTLC1542M ±1 LSB

(1) All typical values are at T

= 25 °C.(2) Linearity error is the maximum deviation from the best straight line through the A/D transfer characteristics.

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TLC1542I , , TLC1542M , , TLC1542QTLC1542C , TLC1543C , TLC1543I , TLC1543Q

SLAS052G – MARCH 1992 – REVISED JANUARY 2006

OPERATING CHARACTERISTICS (continued)over recommended operating free-air temperature range, V

= V

ref+

= 4.5 V to 5.5 V, I/O CLOCK frequency = 2.1 MHz(unless otherwise noted)

TEST

MIN TYP

(1)

MAX UNITCONDITIONS

TLC1542C, I, or Q See

(4)

±1 LSBE

Zero-scale error, see

(3)

TLC1543C, I, or Q See

(4)

±1 LSBTLC1542M See

(4)

±1 LSBTLC1542C, I, or Q See

(4)

±1 LSBE

Full-scale error, see

(3)

TLC1543C, I, or Q See

(4)

±1 LSBTLC1542M See

(4)

±1 LSBTLC1542C, I, or Q ±1 LSBTotal unadjusted error, see

(5)

TLC1543C, I, or Q ±1 LSBTLC1542M ±1 LSBADDRESS = 1011 512Self-test output code, see Table 3 and

(6)

ADDRESS = 1100 0ADDRESS = 1101 1023See timingt

conv

Conversion time 21 µsdiagrams

21See timing +10 I/Ot

Total cycle time (access, sample, and conversion) µsdiagrams and

(7)

CLOCK

periodsSee timing I/O CLOCKt

acq

Channel acquisition time (sample) 6diagrams and

(7)

periodst

Valid time, DATA OUT remains valid after I/O CLOCK ↓See Figure 6 10 nst

d(I/O-DATA)

Delay time, I/O CLOCK ↓to DATA OUT valid See Figure 6 240 nst

d(I/O-EOC)

Delay time, tenth I/O CLOCK ↓to EOC ↓See Figure 7 70 240 nst

d(EOC-DATA)

Delay time, EOC ↑to DATA OUT (MSB) See Figure 8 100 nst

PZH

, t

PZL

Enable time, CS↓to DATA OUT (MSB driven) See Figure 3 1.3 µst

PHZ

, t

PLZ

Disable time, CS↑to DATA OUT (high impedance) See Figure 3 150 nst

r(EOC)

Rise time, EOC See Figure 8 300 nst

f(EOC)

Fall time, EOC See Figure 7 300 nst

r(DATA)

Rise time, data bus See Figure 6 300 nst

f(DATA)

Fall time, data bus See Figure 6 300 nsDelay time, tenth I/O CLOCK ↓to CS↓to abortt

d(I/O-CS)

9µsconversion (see Note

(8)

)

(3) Zero-scale error is the difference between 0000000000 and the converted output for zero input voltage; full-scale error is the differencebetween 1111111111 and the converted output for full-scale input voltage.(4) Analog input voltages greater than that applied to REF+ convert as all ones (1111111111), while input voltages less than that applied toREF- convert as all zeros (0000000000). The device is functional with reference voltages down to 1 V (V

ref+

-V

ref-

); however, theelectrical specifications are no longer applicable.(5) Total unadjusted error comprises linearity, zero-scale, and full-scale errors.(6) Both the input address and the output codes are expressed in positive logic.(7) I/O CLOCK period = 1/(I/O CLOCK frequency) (see Figure 6)(8) Any transitions of CS are recognized as valid only if the level is maintained for a setup time plus two falling edges of the internal clock(1.425 µs) after the transition.

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PARAMETER MEASUREMENT INFORMATION

EOC

CL = 50 pF 12 kΩ

DATA OUT

Test Point VCC

RL = 2.18 kΩ

CL = 100 pF 12 kΩ

Test Point VCC

RL = 2.18 kΩ

DATA

OUT

2.4 V

0.4 V

90%

10%

tPZH, tPZL tPHZ, tPLZ

0.8 V

2 V

ADDRESS

th(A)

0.8 V

2 V

I/O CLOCK

Address

Valid

tsu(A)

0.8 V

Last

Clock

CS 0.8 V

2 V

0.8 V

tsu(CS)

0.8 V

I/O CLOCK

th(CS)

First

Clock

TLC1542I , , TLC1542M , , TLC1542QTLC1542C , TLC1543C , TLC1543I , TLC1543Q

SLAS052G – MARCH 1992 – REVISED JANUARY 2006

Figure 2. Load Circuits

Figure 3. DATA OUT Enable and Disable Voltage Waveforms

Figure 4. ADDRESS Setup and Hold Time Voltage Waveforms

Figure 5. I/O CLOCK Setup and Hold Time Voltage Waveforms

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0.4 V

2.4 V

0.4 V

2.4 V

2 V 0.8 V

I/O CLOCK

DATA OUT

tt(I/O)

0.8 V

2 V

tr(DATA), tf(DATA)

td(I/O-DATA)

tt(I/O)

0.8 V

I/O CLOCK Period

10th

Clock 0.8 V

2.4 V 0.4 V

tf(EOC)

td(I/O-EOC)

I/O CLOCK

EOC

0.4 V

2.4 V

EOC

Valid MSB

DATA OUT

0.4 V 2.4 V

tr(EOC)

td(EOC-DATA)

TLC1542I , , TLC1542M , , TLC1542QTLC1542C , TLC1543C , TLC1543I , TLC1543Q

SLAS052G – MARCH 1992 – REVISED JANUARY 2006

PARAMETER MEASUREMENT INFORMATION (continued)

Figure 6. I/O CLOCK and DATA OUT Voltage Waveforms

Figure 7. I/O CLOCK and EOC Voltage Waveforms

Figure 8. EOC and DATA OUT Voltage Waveforms

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TIMING DIAGRAMS

ÎÎÎÎÎÎ

ÎÎ

ÎÎÎ

ÎÎ

Access Cycle B

Shift in New Multiplexer Address;

Simultaneously Shift Out Previous

Conversion Value

Sample Cycle B

A/D Conversion

Interval InitializeInitialize

MSB LSB

Previous Conversion Data

MSB LSB

B3 B2 B1 B0 C3

B9A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Hi-Z State

1 2 3 4 5 6 7 8 9 10 1

I/O

CLOCK

DATA

OUT

ADDRESS

(see Note A)

EOC

ÎÎÎ

ÎÎ

ÎÎÎ

Access Cycle B

Shift in New Multiplexer Address;

Simultaneously Shift Out Previous

Conversion Value

Sample Cycle B

A/D Conversion

Interval

Initialize

MSB LSB

Previous Conversion Data

MSB LSB

B3 B2 B1 B0 C3

B9A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Low Level

1 2 3 4 5 6 7 8 9 10 1

I/O

CLOCK

DATA

OUT

ADDRESS

EOC

Initialize

(see Note A)

Must be High on Power Up

TLC1542I , , TLC1542M , , TLC1542QTLC1542C , TLC1543C , TLC1543I , TLC1543Q

SLAS052G – MARCH 1992 – REVISED JANUARY 2006

PARAMETER MEASUREMENT INFORMATION (continued)

Figure 9. Timing for 10-Clock Transfer Using CS

Figure 10. Timing for 10-Clock Transfer Not Using CS

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ÎÎÎ

ÎÎ

ÎÎÎ

ÎÎ

ÎÎÎ

Access Cycle B

Shift in New Multiplexer Address;

Simultaneously Shift Out Previous

Conversion Value

Sample Cycle B

A/D Conversion

Interval

Initialize

MSB LSB

Previous Conversion Data

MSB LSB

B3 B2 B1 B0 C3

B9A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

1 2 3 4 5 6 7 8 9 10 1

I/O

CLOCK

DATA

OUT

ADDRESS

EOC

Initialize

ÏÏÏ

ÎÎÎ

Low

Level Hi-Z

See Note B

11 16

(see Note A)

TLC1542I , , TLC1542M , , TLC1542QTLC1542C , TLC1543C , TLC1543I , TLC1543Q

SLAS052G – MARCH 1992 – REVISED JANUARY 2006

PARAMETER MEASUREMENT INFORMATION (continued)

A. To minimize errors caused by noise at CS, the internal circuitry waits for a setup time plus two falling edges of theinternal system clock after CS↓before responding to control input signals. Therefore, no attempt should be made toclock in an address until the minimum CS setup time has elapsed.B. A low-to-high transition of CS disables ADDRESS and the I/O CLOCK within a maximum of a setup time plus twofalling edges of the internal system clock.

Figure 11. Timing for 11- to 16-Clock Transfer UsingCS (Serial Transfer Interval Shorter Than Conversion)

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ÎÎ

ÎÎÎ

Access Cycle B

Shift in New Multiplexer Address;

Simultaneously Shift Out Previous

Conversion Value

Sample Cycle B

A/D Conversion

Interval

Initialize

MSB LSB

Previous Conversion Data

MSB LSB

B3 B2 B1 B0 C3

B9A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Low Level

1 2 3 4 5 6 7 8 9 10 1

I/O

CLOCK

DATA

OUT

ADDRESS

EOC

Initialize

Must Be High on Power Up

14 15 16

See Note B

(see Note A)

ÎÎÎ

TLC1542I , , TLC1542M , , TLC1542QTLC1542C , TLC1543C , TLC1543I , TLC1543Q

SLAS052G – MARCH 1992 – REVISED JANUARY 2006

PARAMETER MEASUREMENT INFORMATION (continued)

A. To minimize errors caused by noise at CS, the internal circuitry waits for a setup time plus two falling edges of theinternal system clock after CS↓before responding to control input signals. Therefore, no attempt should be made toclock in an address until the minimum CS setup time has elapsed.B. The first I/O CLOCK must occur after the rising edge of EOC.

Figure 12. Timing for 16-Clock Transfer Not UsingCS (Serial Transfer Interval Shorter Than Conversion)

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ÎÎÎ

ÎÎ

ÎÎÎ

Access Cycle B

Shift in New Multiplexer Address;

Simultaneously Shift Out Previous

Conversion Value

Sample Cycle B

A/D Conversion

Interval

Initialize

MSB LSB

Previous Conversion Data

MSB LSB

B3 B2 B1 B0 C3

B9A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

1 2 3 4 5 6 7 8 9 10 1

I/O

CLOCK

DATA

OUT

ADDRESS

EOC

Initialize

ÏÏÏ

ÎÎ

ÎÎÎ

Hi-Z State

See Note B

ÏÏÏ

Low

Level

(see Note A)

TLC1542I , , TLC1542M , , TLC1542QTLC1542C , TLC1543C , TLC1543I , TLC1543Q

SLAS052G – MARCH 1992 – REVISED JANUARY 2006

PARAMETER MEASUREMENT INFORMATION (continued)

A. To minimize errors caused by noise at CS, the internal circuitry waits for a setup time plus two falling edges of theinternal system clock after CS↓before responding to control input signals. Therefore, no attempt should be made toclock in an address until the minimum CS setup time has elapsed.B. The 11th rising edge of the I/O CLOCK sequence must occur before the conversion is complete to prevent losingserial interface synchronization.

Figure 13. Timing for 11- to 16-Clock Transfer UsingCS (Serial Transfer Interval Longer Than Conversion)

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ÎÎ

ÎÎÎ

ÎÎ

ÎÎÎ

Shift in New Multiplexer Address;

Simultaneously Shift Out Previous

Conversion Value

Sample Cycle B

A/D Conversion

Interval

Initialize

MSB LSB

Previous Conversion Data

MSB LSB

B3 B2 B1 B0 C3

B9A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

1 2 3 4 5 6 7 8 9 10 1

I/O

CLOCK

DATA

OUT

ADDRESS

EOC

Must be High on Power Up

14 15 16

See Note C

See Note B

Low Level

Access Cycle B

(see Note A)

TLC1542I , , TLC1542M , , TLC1542QTLC1542C , TLC1543C , TLC1543I , TLC1543Q

SLAS052G – MARCH 1992 – REVISED JANUARY 2006

PARAMETER MEASUREMENT INFORMATION (continued)

A. A. To minimize errors caused by noise at CS, the internal circuitry waits for a setup time plus two falling edges of theinternal system clock after CS↓before responding to control input signals. Therefore, no attempt should be made toclock in an address until the minimum CS setup time has elapsed.B. The 11th rising edge of the I/O CLOCK sequence must occur before the conversion is complete to prevent losingserial interface synchronization.C. C. The I/O CLOCK sequence is exactly 16 clock pulses long.

Figure 14. Timing for 16-Clock Transfer Not UsingCS (Serial Transfer Interval Longer Than Conversion)

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APPLICATION INFORMATION

1000000000

0111111111

0000000010

0000000001

0000000000

1111111110

0 0.0096 2.4528 2.4576 2.4624

Digital Output Code

1000000001

1111111101

1111111111

4.9056 4.9104 4.9152

512

511

1022

Step

513

1021

1023

0.0024

VI − Analog Input Voltage − V

VZT =VZS + 1/2 LSB

VZS

See Notes A and B

4.9080

0.0048

VFT = VFS − 1/2 LSB

VFS

Processor Control

Circuit

Analog

Inputs

A10

I/O CLOCK

ADDRESS

DATA OUT

EOC

REF+

REF−

GND

TLC1542/43

To Source

Ground

5-V DC Regulator

TLC1542I , , TLC1542M , , TLC1542QTLC1542C , TLC1543C , TLC1543I , TLC1543Q

SLAS052G – MARCH 1992 – REVISED JANUARY 2006

A. This curve is based on the assumption that V

ref+

and V

ref-

have been adjusted so that the voltage at the transitionfrom digital 0 to 1 (V

) is 0.0024 V and the transition to full scale (V

) is 4.908 V. 1 LSB = 4.8 mV.B. The full-scale value (V

) is the step whose nominal midstep value has the highest absolute value. The zero-scalevalue (V

) is the step whose nominal midstep value equals zero.

Figure 15. Ideal Conversion Characteristics

Figure 16. Serial Interface

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SIMPLIFIED ANALOG INPUT ANALYSIS

VC = VS 1−e −t c/RtCi

( )

where Rt = Rs + ri

(1)

VC (1/2 LSB) = VS − (VS/2048)

(2)

VS −(VS/2048) = VS 1−e

( )

−t c/RtCi

and tc (1/2 LSB) = Rt × Ci × ln(2048)

(3)

tc (1/2 LSB) = (Rs + 1 kΩ) × 60 pF × ln(2048)

(4)

Rsri

VSVC

1 kΩ MAX

Driving Source†TLC1542/3

50 pF MAX

VI= Input Voltage at A0−A10

VS= External Driving Source Voltage

Rs= Source Resistance

ri= Input Resistance

Ci= Equivalent Input Capacitance

†Driving source requirements:

•Noise and distortion for the source must be equivalent to the

resolution of the converter.

•Rs must be real at the input frequency.

TLC1542I , , TLC1542M , , TLC1542QTLC1542C , TLC1543C , TLC1543I , TLC1543Q

SLAS052G – MARCH 1992 – REVISED JANUARY 2006

APPLICATION INFORMATION (continued)

Using the equivalent circuit in Figure 17 Figure 17, the time required to charge the analog input capacitance from0 to V

within 1/2 LSB can be derived as follows:

The capacitance charging voltage is given by

The final voltage to 1/2 LSB is given by

Equating equation 1 to equation 2 and solving for time t

gives

Therefore, with the values given the time for the analog input signal to settle is

This time must be less than the converter sample time shown in the timing diagrams.

Figure 17. Equivalent Input Circuit Including the Driving Source

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PACKAGING INFORMATION

Orderable Device Status (1) Package

Type Package

Drawing Pins Package

Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)

5962-9064202Q2A OBSOLETE LCCC FK 20 TBD Call TI Call TI

5962-9064202QRA OBSOLETE CDIP J 20 TBD Call TI Call TI

TLC1542CDW ACTIVE SOIC DW 20 25 Green (RoHS &

no Sb/Br) CU NIPDAU Level-1-260C-UNLIM

TLC1542CDWG4 ACTIVE SOIC DW 20 25 Green (RoHS &

no Sb/Br) CU NIPDAU Level-1-260C-UNLIM

TLC1542CDWR ACTIVE SOIC DW 20 2000 Green (RoHS &

no Sb/Br) CU NIPDAU Level-1-260C-UNLIM

TLC1542CDWRG4 ACTIVE SOIC DW 20 2000 Green (RoHS &

no Sb/Br) CU NIPDAU Level-1-260C-UNLIM

TLC1542CFN ACTIVE PLCC FN 20 46 Green (RoHS &

no Sb/Br) CU SN Level-1-260C-UNLIM

TLC1542CFNG3 ACTIVE PLCC FN 20 46 Green (RoHS &

no Sb/Br) CU SN Level-1-260C-UNLIM

TLC1542CN ACTIVE PDIP N 20 20 Pb-Free

(RoHS) CU NIPDAU N / A for Pkg Type

TLC1542CNE4 ACTIVE PDIP N 20 20 Pb-Free

(RoHS) CU NIPDAU N / A for Pkg Type

TLC1542IDW ACTIVE SOIC DW 20 25 Green (RoHS &

no Sb/Br) CU NIPDAU Level-1-260C-UNLIM

TLC1542IDWG4 ACTIVE SOIC DW 20 25 Green (RoHS &

no Sb/Br) CU NIPDAU Level-1-260C-UNLIM

TLC1542IDWR ACTIVE SOIC DW 20 2000 Green (RoHS &

no Sb/Br) CU NIPDAU Level-1-260C-UNLIM

TLC1542IDWRG4 ACTIVE SOIC DW 20 2000 Green (RoHS &

no Sb/Br) CU NIPDAU Level-1-260C-UNLIM

TLC1542IFN OBSOLETE PLCC FN 20 TBD Call TI Call TI

TLC1542IN ACTIVE PDIP N 20 20 Pb-Free

(RoHS) CU NIPDAU N / A for Pkg Type

TLC1542INE4 ACTIVE PDIP N 20 20 Pb-Free

(RoHS) CU NIPDAU N / A for Pkg Type

TLC1542MFKB OBSOLETE LCCC FK 20 TBD Call TI Call TI

TLC1542MJB OBSOLETE CDIP J 20 TBD Call TI Call TI

TLC1542QFN ACTIVE PLCC FN 20 46 Green (RoHS &

no Sb/Br) CU SN Level-1-260C-UNLIM

TLC1543CDB ACTIVE SSOP DB 20 70 Green (RoHS &

no Sb/Br) CU NIPDAU Level-1-260C-UNLIM

TLC1543CDBG4 ACTIVE SSOP DB 20 70 Green (RoHS &

no Sb/Br) CU NIPDAU Level-1-260C-UNLIM

TLC1543CDBLE OBSOLETE SSOP DB 20 TBD Call TI Call TI

TLC1543CDBR ACTIVE SSOP DB 20 2000 Green (RoHS &

no Sb/Br) CU NIPDAU Level-1-260C-UNLIM

TLC1543CDBRG4 ACTIVE SSOP DB 20 2000 Green (RoHS &

no Sb/Br) CU NIPDAU Level-1-260C-UNLIM

TLC1543CDW ACTIVE SOIC DW 20 25 Green (RoHS &

no Sb/Br) CU NIPDAU Level-1-260C-UNLIM

TLC1543CDWG4 ACTIVE SOIC DW 20 25 Green (RoHS &

no Sb/Br) CU NIPDAU Level-1-260C-UNLIM

PACKAGE OPTION ADDENDUM

www.ti.com 31-Mar-2010

Addendum-Page 1

Orderable Device Status (1) Package

Type Package

Drawing Pins Package

Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)

TLC1543CDWR ACTIVE SOIC DW 20 2000 Green (RoHS &

no Sb/Br) CU NIPDAU Level-1-260C-UNLIM

TLC1543CDWRG4 ACTIVE SOIC DW 20 2000 Green (RoHS &

no Sb/Br) CU NIPDAU Level-1-260C-UNLIM

TLC1543CFN ACTIVE PLCC FN 20 46 Green (RoHS &

no Sb/Br) CU SN Level-1-260C-UNLIM

TLC1543CFNG3 ACTIVE PLCC FN 20 46 Green (RoHS &

no Sb/Br) CU SN Level-1-260C-UNLIM

TLC1543CFNR ACTIVE PLCC FN 20 1000 Green (RoHS &

no Sb/Br) CU SN Level-1-260C-UNLIM

TLC1543CFNRG3 ACTIVE PLCC FN 20 1000 Green (RoHS &

no Sb/Br) CU SN Level-1-260C-UNLIM

TLC1543CN ACTIVE PDIP N 20 20 Pb-Free

(RoHS) CU NIPDAU N / A for Pkg Type

TLC1543CNE4 ACTIVE PDIP N 20 20 Pb-Free

(RoHS) CU NIPDAU N / A for Pkg Type

TLC1543IDB ACTIVE SSOP DB 20 70 Green (RoHS &

no Sb/Br) CU NIPDAU Level-1-260C-UNLIM

TLC1543IDBG4 ACTIVE SSOP DB 20 70 Green (RoHS &

no Sb/Br) CU NIPDAU Level-1-260C-UNLIM

TLC1543IDBLE OBSOLETE SSOP DB 20 TBD Call TI Call TI

TLC1543IDBR ACTIVE SSOP DB 20 2000 Green (RoHS &

no Sb/Br) CU NIPDAU Level-1-260C-UNLIM

TLC1543IDBRG4 ACTIVE SSOP DB 20 2000 Green (RoHS &

no Sb/Br) CU NIPDAU Level-1-260C-UNLIM

TLC1543IDW ACTIVE SOIC DW 20 25 Green (RoHS &

no Sb/Br) CU NIPDAU Level-1-260C-UNLIM

TLC1543IDWG4 ACTIVE SOIC DW 20 25 Green (RoHS &

no Sb/Br) CU NIPDAU Level-1-260C-UNLIM

TLC1543IDWR ACTIVE SOIC DW 20 2000 Green (RoHS &

no Sb/Br) CU NIPDAU Level-1-260C-UNLIM

TLC1543IDWRG4 ACTIVE SOIC DW 20 2000 Green (RoHS &

no Sb/Br) CU NIPDAU Level-1-260C-UNLIM

TLC1543IFN ACTIVE PLCC FN 20 46 Green (RoHS &

no Sb/Br) CU SN Level-1-260C-UNLIM

TLC1543IFNG3 ACTIVE PLCC FN 20 46 Green (RoHS &

no Sb/Br) CU SN Level-1-260C-UNLIM

TLC1543IN ACTIVE PDIP N 20 20 Pb-Free

(RoHS) CU NIPDAU N / A for Pkg Type

TLC1543INE4 ACTIVE PDIP N 20 20 Pb-Free

(RoHS) CU NIPDAU N / A for Pkg Type

TLC1543QDB ACTIVE SSOP DB 20 70 TBD CU NIPDAU Level-1-220C-UNLIM

TLC1543QDBG4 ACTIVE SSOP DB 20 70 Green (RoHS &

no Sb/Br) CU NIPDAU Level-1-260C-UNLIM

TLC1543QDBR ACTIVE SSOP DB 20 2000 Pb-Free

(RoHS) CU NIPDAU Level-2-250C-1 YEAR/

Level-1-235C-UNLIM

TLC1543QDBRG4 ACTIVE SSOP DB 20 2000 Green (RoHS &

no Sb/Br) CU NIPDAU Level-1-260C-UNLIM

TLC1543QDW ACTIVE SOIC DW 20 25 Green (RoHS &

no Sb/Br) CU NIPDAU Level-1-260C-UNLIM

TLC1543QDWG4 ACTIVE SOIC DW 20 25 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

PACKAGE OPTION ADDENDUM

www.ti.com 31-Mar-2010

Addendum-Page 2

Orderable Device Status (1) Package

Type Package

Drawing Pins Package

Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)

no Sb/Br)

TLC1543QDWR ACTIVE SOIC DW 20 2000 Green (RoHS &

no Sb/Br) CU NIPDAU Level-1-260C-UNLIM

TLC1543QDWRG4 ACTIVE SOIC DW 20 2000 Green (RoHS &

no Sb/Br) CU NIPDAU Level-1-260C-UNLIM

TLC1543QFN ACTIVE PLCC FN 20 46 Green (RoHS &

no Sb/Br) CU SN Level-1-260C-UNLIM

(1) The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in

a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check

http://www.ti.com/productcontent for the latest availability information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements

for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered

at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and

package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS

compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame

retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)

(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder

temperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is

provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the

accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take

reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on

incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited

information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI

to Customer on an annual basis.

OTHER QUALIFIED VERSIONS OF TLC1543 :

•Enhanced Product: TLC1543-EP

NOTE: Qualified Version Definitions:

•Enhanced Product - Supports Defense, Aerospace and Medical Applications

PACKAGE OPTION ADDENDUM

www.ti.com 31-Mar-2010

Addendum-Page 3

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package

Type Package

Drawing Pins SPQ Reel

Diameter

(mm)

Reel

Width

W1 (mm)

(mm) B0

(mm) K0

(mm) P1

(mm) W

(mm) Pin1

Quadrant

TLC1543CDBR SSOP DB 20 2000 330.0 16.4 8.2 7.5 2.5 12.0 16.0 Q1

TLC1543CDWR SOIC DW 20 2000 330.0 24.4 10.8 13.0 2.7 12.0 24.0 Q1

TLC1543IDBR SSOP DB 20 2000 330.0 16.4 8.2 7.5 2.5 12.0 16.0 Q1

TLC1543IDWR SOIC DW 20 2000 330.0 24.4 10.8 13.0 2.7 12.0 24.0 Q1

TLC1543QDBR SSOP DB 20 2000 330.0 16.4 8.2 7.5 2.5 12.0 16.0 Q1

PACKAGE MATERIALS INFORMATION

www.ti.com 14-Jul-2012

Pack Materials-Page 1

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)

TLC1543CDBR SSOP DB 20 2000 367.0 367.0 38.0

TLC1543CDWR SOIC DW 20 2000 367.0 367.0 45.0

TLC1543IDBR SSOP DB 20 2000 367.0 367.0 38.0

TLC1543IDWR SOIC DW 20 2000 367.0 367.0 45.0

TLC1543QDBR SSOP DB 20 2000 367.0 367.0 38.0

PACKAGE MATERIALS INFORMATION

www.ti.com 14-Jul-2012

Pack Materials-Page 2

MECHANICAL DATA

MPLC004A – OCTOBER 1994

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

FN (S-PQCC-J**) PLASTIC J-LEADED CHIP CARRIER

4040005/B 03/95

20 PIN SHOWN

0.026 (0,66)

0.032 (0,81)

D2/E2

0.020 (0,51) MIN

0.180 (4,57) MAX

0.120 (3,05)

0.090 (2,29)

D2/E2

0.013 (0,33)

0.021 (0,53)

Seating Plane

MAX

D2/E2

0.219 (5,56)

0.169 (4,29)

0.319 (8,10)

0.469 (11,91)

0.569 (14,45)

0.369 (9,37)

MAX

0.356 (9,04)

0.456 (11,58)

0.656 (16,66)

0.008 (0,20) NOM

1.158 (29,41)

0.958 (24,33)

0.756 (19,20)

0.191 (4,85)

0.141 (3,58)

MIN

0.441 (11,20)

0.541 (13,74)

0.291 (7,39)

0.341 (8,66)

E1E

MINMAXMIN

PINS

0.385 (9,78)

0.485 (12,32)

0.685 (17,40)

84 1.185 (30,10)

0.985 (25,02)

0.785 (19,94)

D/E

0.395 (10,03)

0.495 (12,57)

1.195 (30,35)

0.995 (25,27)

0.695 (17,65)

0.795 (20,19)

NO. OF D1/E1

0.350 (8,89)

0.450 (11,43)

1.150 (29,21)

0.950 (24,13)

0.650 (16,51)

0.750 (19,05)

0.004 (0,10)

0.007 (0,18)

0.050 (1,27)

NOTES: A. All linear dimensions are in inches (millimeters).

B. This drawing is subject to change without notice.

C. Falls within JEDEC MS-018

MECHANICAL DATA

MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE

4040065 /E 12/01

28 PINS SHOWN

Gage Plane

8,20

7,40

0,55

0,95

0,25

12,90

12,30

10,50

8,50

Seating Plane

9,907,90

10,50

9,90

0,38

5,60

5,00

0,22

2016

6,50

0,05 MIN

5,905,90

DIM

A MAX

A MIN

PINS **

2,00 MAX

6,90

7,50

0,65 M

0,15

0°–ā8°

0,10

0,09

0,25

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.

C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.

D. Falls within JEDEC MO-150

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