NLSX5012DMR2G - ON SEMICONDUCTOR - Datasheet.Directory

April, 2011 − Rev. 2

1Publication Order Number:

NLSX5012/D

NLSX5012

2-Bit 100 Mb/s Configurable

Dual-Supply Level

Translator

The NLSX5012 is a 2-bit configurable dual-supply autosensing

bidirectional level translator that does not require a direction control

pin. The I/O VCC- and I/O VL-ports are designed to track two

different power supply rails, VCC and VL respectively. Both the VCC

and the VL supply rails are configurable from 0.9 V to 4.5 V. This

allows a logic signal on the VL side to be translated to either a higher

or a lower logic signal voltage on the VCC side, and vice-versa.

The NLSX5012 offers the feature that the values of the VCC and

VL supplies are independent. Design flexibility is maximized

because VL can be set to a value either greater than or less than the

VCC supply. In contrast, the majority of competitive auto sense

translators have a restriction that the value of the VL supply must be

equal to less than (VCC - 0.4) V.

The NLSX5012 has high output current capability, which allows

the translator to drive high capacitive loads such as most high

frequency EMI filters. Another feature of the NLSX5012 is that each

I/O_VLn and I/O_VCCn channel can function as either an input or an

output.

An Output Enable (EN) input is available to reduce the power

consumption. The EN pin can be used to disable both I/O ports by

putting them in 3-state which significantly reduces the supply current

from both VCC and VL. The EN signal is referenced to the VL supply.

Features

•Wide VCC, VL Operating Range: 0.9 V to 4.5 V

•VL and VCC are independent

− VL may be greater than, equal to, or less than VCC

•High 100 pF Capacitive Drive Capability

•High−Speed with 140 Mb/s Guaranteed Date Rate

for VCC, VL > 1.8 V

•Low Bit−to−Bit Skew

•Overvoltage Tolerant Enable and I/O Pins

•Non−preferential Power−Up Sequencing

•Power−Off Protection

•Small packaging: UDFN8, SO−8, Micro8

•These are Pb−Free Devices

Typical Applications

•Mobile Phones, PDAs, Other Portable Devices

Important Information

•ESD Protection for All Pins:

♦HBM (Human Body Model) > 8000 V

http://onsemi.com

†For information on tape and reel specifications,

including part orientation and tape sizes, please

refer to our Tape and Reel Packaging Specification

Brochure, BRD8011/D.

UDFN8

MU SUFFIX

CASE 517AJ

VA = Specific Device Code

M = Date Code

G= Pb−Free Package

AE M

SO−8

D SUFFIX

CASE 751

A = Assembly Location

Y = Year

W = Work Week

G= Pb−Free Package

SX5012

ALYWG

Micro8

DM SUFFIX

CASE 846A

5012

AYWG

A = Assembly Location

L = Wafer Lot

Y = Year

W = Work Week

G= Pb−Free Package

MARKING

DIAGRAMS

Device Package Shipping†

ORDERING INFORMATION

NLSX5012MUTAG UDFN8

(Pb−Free)

3000/Tape & Reel

NLSX5012DR2G SO−8

(Pb−Free)

2500/Tape & Reel

NLSX5012DMR2G Micro8

(Pb−Free)

4000/Tape & Reel

NLSX5012

http://onsemi.com

Figure 1. Typical Application Circuit

I/O VL1

I/O VLn

ENOE

I/On

I/O1

GND

+1.8 V System

+1.8V +3.6V

+3.6 V System

I/On

I/O1

GNDGND

NLSX5012

I/O VCC1

I/O VCCn

VLVCC

Figure 2. Simplified Functional Diagram (1 I/O Line)

One−Shot

I/O VLI/O VCC

VCC

Figure 3. Application Example for VL < VCC

ENANO

2.5 V 3.0 V

Peripheral

GND

NLSX5012

VLVCC

I/O VL2 I/O VCC2RX TX

I/O VL1 I/O VCC1TX RX

Figure 4. Application Example for VL > VCC

ENANO

2.5 V 1.8 V

Peripheral

GND

NLSX5012

VLVCC

I/O VL2 I/O VCC2RX TX

I/O VL1 I/O VCC1TX RX

NLSX5012

http://onsemi.com

Figure 5. Logic Diagram

VLVCC GND

I/O VL1

I/O VL2

I/O VCC1

I/O VCC2

Figure 6. Pin Assignments

Micro8

(Top View)

1 8

SOIC−8

(Top View)

UDFN8

(Top View)

VCC

I/O VCC1

I/O VCC2

I/O VL1

I/O VL2

GND

VCC

I/O VCC1

I/O VCC2

I/O VL1

I/O VL2

GND

VCC

I/O VCC1

I/O VCC2

I/O VL1

I/O VL2

GND

PIN ASSIGNMENT

Pins Description

VCC VCC Input Voltage

VLVL Input Voltage

GND Ground

EN Output Enable

I/O VCCnI/O Port, Referenced to VCC

I/O VLnI/O Port, Referenced to VL

FUNCTION TABLE

EN Operating Mode

L Hi−Z

HI/O Buses Connected

NLSX5012

http://onsemi.com

MAXIMUM RATINGS

Symbol Parameter Value Condition Unit

VCC High−side DC Supply Voltage −0.5 to +5.5 V

VLLow−side DC Supply Voltage −0.5 to +5.5 V

I/O VCC VCC−Referenced DC Input/Output Voltage −0.5 to +5.5 V

I/O VLVL−Referenced DC Input/Output Voltage −0.5 to +5.5 V

VIEnable Control Pin DC Input Voltage −0.5 to +5.5 V

IIK DC Input Diode Current −50 VI < GND mA

IOK DC Output Diode Current −50 VO < GND mA

ICC DC Supply Current Through VCC $100 mA

ILDC Supply Current Through VL$100 mA

IGND DC Ground Current Through Ground Pin $100 mA

TSTG Storage Temperature −65 to +150 °C

Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the

Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect

device reliability.

RECOMMENDED OPERATING CONDITIONS

Symbol Parameter Min Max Unit

VCC High−side Positive DC Supply Voltage 0.9 4.5 V

VLLow−side Positive DC Supply Voltage 0.9 4.5 V

VIEnable Control Pin Voltage GND 4.5 V

VIO Bus Input/Output Voltage I/O VCC

I/O VL

GND

4.5

TAOperating Temperature Range −55 +125 °C

Dt/DVInput Transition Rise or Rate

VI, VIO from 30% to 70% of VCC; VCC = 3.3 V $ 0.3 V

0 10 ns

NLSX5012

http://onsemi.com

DC ELECTRICAL CHARACTERISTICS

Symbol Parameter

Test Conditions

(Note 1)

VCC (V)

(Note 2)

VL (V)

(Note 3)

−405C to +855C−555C to +1255C

Unit

Min

Typ

(Note 4) Max Min Max

VIHC I/O VCC Input HIGH Voltage 0.9 – 4.5 0.9 – 4.5 2/3 *

VCC

− − 2/3 *

VCC

−V

VILC I/O VCC Input LOW Voltage 0.9 – 4.5 0.9 – 4.5 − − 1/3 *

VCC

−1/3 *

VCC

VIHL I/O VL Input HIGH Voltage 0.9 – 4.5 0.9 – 4.5 2/3 *

− − 2/3 * VL−V

VILL I/O VL Input LOW Voltage 0.9 – 4.5 0.9 – 4.5 − − 1/3 *

−1/3 * VLV

VIH Control Pin Input HIGH

Voltage

TA = +25°C0.9 – 4.5 0.9 – 4.5 2/3 *

− − 2/3 * VL−V

VIL Control Pin Input LOW

Voltage

TA = +25°C0.9 – 4.5 0.9 – 4.5 − − 1/3 *

−1/3 * VLV

VOHC I/O VCC Output HIGH

Voltage

I/O VCC source

current = 20 mA

0.9 – 4.5 0.9 – 4.5 0.9 *

VCC

− − 0.9 *

VCC

−V

VOLC I/O VCC Output LOW Voltage I/O VCC sink

current = 20 mA

0.9 – 4.5 0.9 – 4.5 − − 0.2 −0.2 V

VOHL I/O VL Output HIGH Voltage I/O VL source

current = 20 mA

0.9 – 4.5 0.9 – 4.5 0.9 *

− − 0.9 * VL−V

VOLL I/O VL Output LOW Voltage I/O VL sink current

= 20 mA

0.9 – 4.5 0.9 – 4.5 − − 0.2 −0.2 V

IQVCC VCC Supply Current EN = VL, IO = 0 A,

(I/O VCC = 0 V or

VCC, I/O VL = float)

(I/O VCC = float, I/O

VL = 0 V or VL)

0.9 – 4.5 0.9 – 4.5 −−1−2.5 mA

IQVL VL Supply Current 0.9 – 4.5 0.9 – 4.5 −−1−2.5 mA

ITS−VCC VCC Tristate Output Mode

Supply Current

TA = +25°C,

EN = 0 V

(I/O VCC = 0 V or

VCC, I/O VL = float)

(I/O VCC = float, I/O

VL = 0 V or VL)

0.9 – 4.5 0.9 – 4.5 − − 0.5 −1.5 mA

ITS−VL VL Tristate Output Mode

Supply Current

0.9 – 4.5 0.9 – 4.5 − − 0.5 −1.5 mA

IOZ I/O Tristate Output Mode

Leakage Current

TA = +25°C,

EN = 0V

0.9 – 4.5 0.9 – 4.5 − − ±1−±1.5 mA

IIControl Pin Input Current TA = +25°C0.9 – 4.5 0.9 – 4.5 − − ±1−±1mA

IOFF Power Off Leakage Current I/O VCC = 0 to 4.5V, 0 0 −−1−1.5 mA

I/O VL = 0 to 4.5 V 0.9 – 4.5 0−−1−1.5

00.9 – 4.5 −−1−1.5

1. Normal test conditions are VI = 0 V, CIOVCC ≤ 15 pF and CIOVL ≤ 15 pF, unless otherwise specified.

2. VCC is the supply voltage associated with the I/O VCC port, and VCC ranges from +0.9 V to 4.5 V under normal operating conditions.

3. VL is the supply voltage associated with the I/O VL port, and VL ranges from +0.9 V to 4.5 V under normal operating conditions.

4. Typical values are for VCC = +2.8 V, VL = +1.8 V and TA = +25°C. All units are production tested at TA = +25°C. Limits over the operating

temperature range are guaranteed by design.

NLSX5012

http://onsemi.com

TIMING CHARACTERISTICS

Symbol Parameter

Test Conditions

(Note 5)

VCC (V)

(Note 6)

VL (V)

(Note 7)

−555C to +1255C

Unit

Min

Typ

(Note 8) Max

tR−VCC I/O VCC Rise Time CIOVCC = 15 pF 0.9 – 4.5 0.9 – 4.5 − − 8.5 nS

1.8 – 4.5 1.8 – 4.5 − − 3.5

tF−VCC I/O VCC Fall Time CIOVCC = 15 pF 0.9 – 4.5 0.9 – 4.5 − − 8.5 nS

1.8 – 4.5 1.8 – 4.5 − − 3.5

tR−VL I/O VL Rise Time CIOVL = 15 pF 0.9 – 4.5 0.9 – 4.5 − − 8.5 nS

1.8 – 4.5 1.8 – 4.5 − − 3.5

tF−VL I/O VL Fall Time CIOVL = 15 pF 0.9 – 4.5 0.9 – 4.5 − − 8.5 nS

1.8 – 4.5 1.8 – 4.5 − − 3.5

ZOVCC I/O VCC One−Shot

Output Impedance

(Note 9) 0.9

1.8

4.5

0.9 – 4.5 −

−

6.0

−

ZOVL I/O VL One−Shot Out-

put Impedance

(Note 9) 0.9

1.8

4.5

0.9 – 4.5 −

−

6.0

−

tPD_VL−VCC Propagation Delay

(Driving I/O VCC)

CIOVCC = 15 pF 0.9 – 4.5 0.9 – 4.5 − − 35 nS

1.8 – 4.5 1.8 – 4.5 − − 10

CIOVCC = 30 pF 0.9 – 4.5 0.9 – 4.5 − − 35

1.8 – 4.5 1.8 – 4.5 − − 10

CIOVCC = 50 pF 1.0 – 4.5 1.0 – 4.5 − − 37

1.8 – 4.5 1.8 – 4.5 − − 11

CIOVCC = 100 pF 1.2 – 4.5 1.2 – 4.5 − − 40

1.8 – 4.5 1.8 – 4.5 − − 13

tPD_VCC−VL Propagation Delay

(Driving I/O VL)

CIOVL = 15 pF 0.9 – 4.5 0.9 – 4.5 − − 35 nS

1.8 – 4.5 1.8 – 4.5 − − 10

CIOVL = 30 pF 0.9 – 4.5 0.9 – 4.5 − − 35

1.8 – 4.5 1.8 – 4.5 − − 10

CIOVL = 50 pF 1.0 – 4.5 1.0 – 4.5 − − 37

1.8 – 4.5 1.8 – 4.5 − − 11

CIOVL = 100 pF 1.2 – 4.5 1.2 – 4.5 − − 40

1.8 – 4.5 1.8 – 4.5 − − 13

tSK Channel−to−Channel

Skew

CIOVCC = 15 pF, CIOVL = 15 pF

(Note 9)

0.9 – 4.5 0.9 – 4.5 − − 0.15 nS

IIN_PEAK Input Driver Maximum

Peak Current

EN = VL;

I/O_VCC = 1 MHz Square Wave,

Amplitude = VCC, or

I/O_VL = 1 MHz Square Wave,

Amplitude = VL (Note 9)

0.9 – 4.5 0.9 – 4.5 − − 5.0 mA

5. Normal test conditions are VI = 0 V, CIOVCC ≤ 15 pF and CIOVL ≤ 15 pF, unless otherwise specified.

6. VCC is the supply voltage associated with the I/O VCC port, and VCC ranges from +0.9 V to 4.5 V under normal operating conditions.

7. VL is the supply voltage associated with the I/O VL port, and VL ranges from +0.9 V to 4.5 V under normal operating conditions.

8. Typical values are for VCC = +2.8 V, VL = +1.8 V and TA = +25°C. All units are production tested at TA = +25°C. Limits over the operating

temperature range are guaranteed by design.

9. Guaranteed by design.

NLSX5012

http://onsemi.com

TIMING CHARACTERISTICS (continued)

Symbol Parameter

Test Conditions

(Note 10)

VCC (V)

(Note 11)

VL (V)

(Note 12)

−555C to +1255C

Unit

Min

Typ

(Note 13) Max

tEN−VCC I/O_VCC Output Enable Time tPZH CIOVCC = 15 pF,

I/O_VL = VL

0.9 – 4.5 0.9 – 4.5 − − 160 nS

tPZL CIOVCC = 15 pF,

I/O_VL = 0 V

0.9 – 4.5 0.9 – 4.5 − − 130

tEN−VL I/O_VL Output Enable Time tPZH CIOVL = 15 pF,

I/O_VCC = VCC

0.9 – 4.5 0.9 – 4.5 − − 160 nS

tPZL CIOVL = 15 pF,

I/O_VCC = 0 V

0.9 – 4.5 0.9 – 4.5 − − 130

tDIS−VCC I/O_VCC Output Disable Time tPHZ CIOVCC = 15 pF,

I/O_VL = VL

0.9 – 4.5 0.9 – 4.5 − − 210 nS

tPLZ CIOVCC = 15 pF,

I/O_VL = 0 V

0.9 – 4.5 0.9 – 4.5 − − 175

tDIS−VL I/O_VL Output Disable Time tPHZ CIOVL = 15 pF,

I/O_VCC = VCC

0.9 – 4.5 0.9 – 4.5 − − 210 nS

tPLZ CIOVL = 15 pF,

I/O_VCC = 0 V

0.9 – 4.5 0.9 – 4.5 − − 175

MDR Maximum Data Rate CIO = 15 pF 0.9 – 4.5 0.9 – 4.5 50 − − mbps

1.8 – 4.5 1.8 – 4.5 140 − −

CIO = 30 pF 0.9 – 4.5 0.9 – 4.5 40 − −

1.8 – 4.5 1.8 – 4.5 120 − −

CIO = 50 pF 1.0 – 4.5 1.0 – 4.5 30 − −

1.8 – 4.5 1.8 – 4.5 100 − −

CIO = 100 pF 1.2 – 4.5 1.2 – 4.5 20 − −

1.8 – 4.5 1.8 – 4.5 60 − −

10. Normal test conditions are VI = 0 V, CIOVCC ≤ 15 pF and CIOVL ≤ 15 pF, unless otherwise specified.

11. VCC is the supply voltage associated with the I/O VCC port, and VCC ranges from +0.9 V to 4.5 V under normal operating conditions.

12.VL is the supply voltage associated with the I/O VL port, and VL ranges from +0.9 V to 4.5 V under normal operating conditions.

13.Typical values are for VCC = +2.8 V, VL = +1.8 V and TA = +25°C. All units are production tested at TA = +25°C. Limits over the operating

temperature range are guaranteed by design.

NLSX5012

http://onsemi.com

DYNAMIC POWER CONSUMPTION (TA = +25°C)

Symbol Parameter Test Conditions VCC (V)

(Note 14)

VL (V)

(Note 15)

Typ

(Note 16)

Unit

CPD_VL VL = Input port,

VCC = Output Port

CLoad = 0, f = 1 MHz,

EN = VL (outputs enabled)

0.9 4.5 39 pF

1.5 1.8 20

1.8 1.5 17

1.8 1.8 14

1.8 2.8 13

2.5 2.5 14

2.8 1.8 13

4.5 0.9 19

VCC = Input port,

VL = Output Port

CLoad = 0, f = 1 MHz,

EN = VL (outputs enabled)

0.9 4.5 37 pF

1.5 1.8 30

1.8 1.5 29

1.8 1.8 29

1.8 2.8 29

2.5 2.5 30

2.8 1.8 29

4.5 0.9 19

CPD_VCC VL = Input port,

VCC = Output Port

CLoad = 0, f = 1 MHz,

EN = VL (outputs enabled)

0.9 4.5 29 pF

1.5 1.8 29

1.8 1.5 29

1.8 1.8 29

1.8 2.8 29

2.5 2.5 30

2.8 1.8 29

4.5 0.9 35

VCC = Input port,

VL = Output Port

CLoad = 0, f = 1 MHz,

EN = VL (outputs enabled)

0.9 4.5 21 pF

1.5 1.8 18

1.8 1.5 18

1.8 1.8 14

1.8 2.8 13

2.5 2.5 14

2.8 1.8 13

4.5 0.9 30

14.VCC is the supply voltage associated with the I/O VCC port, and VCC ranges from +0.9 V to 4.5 V under normal operating conditions.

15.VL is the supply voltage associated with the I/O VL port, and VL ranges from +0.9 V to 4.5 V under normal operating conditions.

16. Typical values are at TA = +25°C.

17.CPD VL and CPD VCC are defined as the value of the IC’s equivalent capacitance from which the operating current can be calculated for the

VL and VCC power supplies, respectively. ICC = ICC (dynamic) + ICC (static) ≈ ICC(operating) ≈ CPD x VCC x fIN x NSW where ICC = ICC_VCC

+ ICC VL and NSW = total number of outputs switching.

NLSX5012

http://onsemi.com

STATIC POWER CONSUMPTION (TA = +25°C)

Symbol Parameter Test Conditions VCC (V)

(Note 18)

VL (V)

(Note 19)

Typ

(Note 20)

Unit

CPD_VL VL = Input port,

VCC = Output Port

CLoad = 0, f = 1 MHz,

EN = GND (outputs disabled)

0.9 4.5 0.01 pF

1.5 1.8 0.01

1.8 1.5 0.01

1.8 1.8 0.01

1.8 2.8 0.01

2.5 2.5 0.01

2.8 1.8 0.01

4.5 0.9 0.01

VCC = Input port,

VL = Output Port

CLoad = 0, f = 1 MHz,

EN = GND (outputs disabled)

0.9 4.5 0.01 pF

1.5 1.8 0.01

1.8 1.5 0.01

1.8 1.8 0.01

1.8 2.8 0.01

2.5 2.5 0.01

2.8 1.8 0.01

4.5 0.9 0.01

CPD_VCC VL = Input port,

VCC = Output Port

CLoad = 0, f = 1 MHz,

EN = GND (outputs disabled)

0.9 4.5 0.01 pF

1.5 1.8 0.01

1.8 1.5 0.01

1.8 1.8 0.01

1.8 2.8 0.01

2.5 2.5 0.01

2.8 1.8 0.01

4.5 0.9 0.01

VCC = Input port,

VL = Output Port

CLoad = 0, f = 1 MHz,

EN = GND (outputs disabled)

0.9 4.5 0.01 pF

1.5 1.8 0.01

1.8 1.5 0.01

1.8 1.8 0.01

1.8 2.8 0.01

2.5 2.5 0.01

2.8 1.8 0.01

4.5 0.9 0.01

18.VCC is the supply voltage associated with the I/O VCC port, and VCC ranges from +0.9 V to 4.5 V under normal operating conditions.

19.VL is the supply voltage associated with the I/O VL port, and VL ranges from +0.9 V to 4.5 V under normal operating conditions.

20. Typical values are at TA = +25°C

NLSX5012

http://onsemi.com

NLSX5012

I/O VL

VLVCC

CIOVCC

tRISE/FALL v

3 ns

I/O VL

I/O VCC

tPD_VL−VCC

90%

50%

10%

90%

50%

10%

tPD_VL−VCC

tF−VCC tR−VCC

Figure 7. Driving I/O VL Test Circuit and Timing

I/O VCC

NLSX5012

I/O VL

VLVCC

CIOVL

Source

tRISE/FALL v 3 nsI/O VCC

I/O VL

tPD_VCC−VL

90%

50%

10%

90%

50%

10%

tPD_VCC−VL

tF−VL tR−VL

Figure 8. Driving I/O VCC Test Circuit and Timing

I/O VCC

Source

OPEN

PULSE

GENERATOR

DUT

VCC

2xVCC

Test Switch

tPZH, tPHZ Open

tPZL, tPLZ 2 x VCC

CL = 15 pF or equivalent (Includes jig and probe capacitance)

RL = R1 = 50 kW or equivalent

RT = ZOUT of pulse generator (typically 50 W)

Figure 9. Test Circuit for Enable/Disable Time Measurement

VCC

GND

10%

50%

90%

10%

50%

90%

tPLH tPHL

50%

90%

10%

tPZL tPLZ

tPZH tPHZ

GND

HIGH

IMPEDANCE

VOL

VOH

HIGH

IMPEDANCE

Figure 10. Timing Definitions for Propagation Delays and Enable/Disable Measurement

Input

50% VL

Output

NLSX5012

http://onsemi.com

IMPORTANT APPLICATIONS INFORMATION

Level Translator Architecture

The NLSX5012 auto−sense translator provides

bi−directional logic voltage level shifting to transfer data

in multiple supply voltage systems. These level translators

have two supply voltages, VL and VCC, which set the logic

levels on the input and output sides of the translator. When

used to transfer data from the I/O VL to the I/O VCC ports,

input signals referenced to the VL supply are translated to

output signals with a logic level matched to VCC. In a

similar manner, the I/O VCC to I/O VL translation shifts

input signals with a logic level compatible to VCC to an

output signal matched to VL.

The NLSX5012 translator consists of bi−directional

channels that independently determine the direction of the

data flow without requiring a directional pin. One−shot

circuits are used to detect the rising or falling input signals.

In addition, the one−shots decrease the rise and fall times

of the output signal for high−to−low and low−to−high

transitions.

Input Driver Requirements

Auto−sense translators such as the NLSX5012 have a

wide bandwidth, but a relatively small DC output current

rating. The high bandwidth of the bi−directional I/O circuit

is used to quickly transform from an input to an output

driver and vice versa. The I/O ports have a modest DC

current output specification so that the output driver can be

over driven when data is sent in the opposite direction. For

proper operation, the input driver to the auto−sense

translator should be capable of driving 2 mA of peak output

current. The bi−directional configuration of the translator

results in both input stages being active for a very short time

period. Although the peak current from the input signal

circuit is relatively large, the average current is small and

consistent with a standard CMOS input stage.

Enable Input (EN)

The NLSX5012 translator has an Enable pin (EN) that

provides tri−state operation at the I/O pins. Driving the

Enable pin to a low logic level minimizes the power

consumption of the device and drives the I/O VCC and I/O

VL pins to a high impedance state. Normal translation

operation occurs when the EN pin is equal to a logic high

signal. The EN pin is referenced to the VL supply and has

Over−Voltage Tolerant (OVT) protection.

Uni−Directional versus Bi−Directional Translation

The NLSX5012 translator can function as a

non−inverting uni−directional translator. One advantage of

using the translator as a uni−directional device is that each

I/O pin can be configured as either an input or output. The

configurable input or output feature is especially useful in

applications such as SPI that use multiple uni−directional

I/O lines to send data to and from a device. The flexible I/O

port of the auto sense translator simplifies the trace

connections on the PCB.

Power Supply Guidelines

The values of the VL and VCC supplies can be set to

anywhere between 0.9 and 4.5 V. Design flexibility is

maximized because VL may be either greater than or less

than the VCC supply. In contrast, the majority of the

competitive auto sense translators has a restriction that the

value of the VL supply must be equal to less than (VCC −

0.4) V.

The sequencing of the power supplies will not damage

the device during power−up operation. In addition, the I/O

VCC and I/O VL pins are in the high impedance state if

either supply voltage is equal to 0 V. For optimal

performance, 0.01 to 0.1 mF decoupling capacitors should

be used on the VL and VCC power supply pins. Ceramic

capacitors are a good design choice to filter and bypass any

noise signals on the voltage lines to the ground plane of the

PCB. The noise immunity will be maximized by placing

the capacitors as close as possible to the supply and ground

pins, along with minimizing the PCB connection traces.

The NLSX5012 translators have a power down feature

that provides design flexibility. The output ports are

disabled when either power supply is off (VL or VCC = 0 V).

This feature causes all of the I/O pins to be in the power

saving high impedance state.

NLSX5012

http://onsemi.com

PACKAGE DIMENSIONS

UDFN8 1.8 x 1.2, 0.4P

CASE 517AJ−01

ISSUE O

NOTES:

1. DIMENSIONING AND TOLERANCING PER

ASME Y14.5M, 1994.

2. CONTROLLING DIMENSION: MILLIMETERS.

3. DIMENSION b APPLIES TO PLATED

TERMINAL AND IS MEASURED BETWEEN

0.15 AND 0.30 mm FROM TERMINAL TIP.

4. MOLD FLASH ALLOWED ON TERMINALS

ALONG EDGE OF PACKAGE. FLASH MAY

NOT EXCEED 0.03 ONTO BOTTOM

SURFACE OF TERMINALS.

5. DETAIL A SHOWS OPTIONAL

CONSTRUCTION FOR TERMINALS.

ÏÏ

A B

BOTTOM VIEW

BAC

CNOTE 3

0.10 C

PIN ONE

REFERENCE

TOP VIEW

0.10 C

(A3)

0.05 C

CSEATING

PLANE

SIDE VIEW

L8X

DIM MIN MAX

MILLIMETERS

A0.45 0.55

A1 0.00 0.05

A3 0.127 REF

b0.15 0.25

D1.80 BSC

E1.20 BSC

e0.40 BSC

L0.45 0.55

e/2

b2 0.30 REF

L1 0.00 0.03

L2 0.40 REF

DETAIL A

(L2)

(b2)

NOTE 5

DETAIL A

0.10

0.05 0.22

0.32

1.50

0.40 PITCH

0.66

DIMENSIONS: MILLIMETERS

MOUNTING FOOTPRINT

SOLDERMASK DEFINED

NLSX5012

http://onsemi.com

PACKAGE DIMENSIONS

SO−8

CASE 751−07

ISSUE AJ

SEATING

PLANE

X 45_

NOTES:

1. DIMENSIONING AND TOLERANCING PER

ANSI Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSION A AND B DO NOT INCLUDE

MOLD PROTRUSION.

4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)

PER SIDE.

5. DIMENSION D DOES NOT INCLUDE DAMBAR

PROTRUSION. ALLOWABLE DAMBAR

PROTRUSION SHALL BE 0.127 (0.005) TOTAL

IN EXCESS OF THE D DIMENSION AT

MAXIMUM MATERIAL CONDITION.

6. 751−01 THRU 751−06 ARE OBSOLETE. NEW

STANDARD IS 751−07.

0.10 (0.004)

DIM

MIN MAX MIN MAX

INCHES

4.80 5.00 0.189 0.197

MILLIMETERS

B3.80 4.00 0.150 0.157

C1.35 1.75 0.053 0.069

D0.33 0.51 0.013 0.020

G1.27 BSC 0.050 BSC

H0.10 0.25 0.004 0.010

J0.19 0.25 0.007 0.010

K0.40 1.27 0.016 0.050

M0 8 0 8

N0.25 0.50 0.010 0.020

S5.80 6.20 0.228 0.244

−X−

−Y−

0.25 (0.010)

−Z−

0.25 (0.010) ZSXS

____

1.52

0.060

7.0

0.275

0.6

0.024

1.270

0.050

4.0

0.155

ǒmm

inchesǓ

SCALE 6:1

*For additional information on our Pb−Free strategy and soldering

details, please download the ON Semiconductor Soldering and

Mounting Techniques Reference Manual, SOLDERRM/D.

SOLDERING FOOTPRINT*

NLSX5012

http://onsemi.com

PACKAGE DIMENSIONS

Micro8t

CASE 846A−02

ISSUE H

0.08 (0.003) A S

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSION A DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE

BURRS. MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED

0.15 (0.006) PER SIDE.

4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION.

INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER

SIDE.

5. 846A-01 OBSOLETE, NEW STANDARD 846A-02.

PIN 1 ID

8 PL

0.038 (0.0015)

−T−

SEATING

PLANE

A1 cL

*For additional information on our Pb−Free strategy and soldering

details, please download the ON Semiconductor Soldering and

Mounting Techniques Reference Manual, SOLDERRM/D.

SOLDERING FOOTPRINT*

8X 8X

6X ǒmm

inchesǓ

SCALE 8:1

1.04

0.041

0.38

0.015

5.28

0.208

4.24

0.167

3.20

0.126

0.65

0.0256

DIM

MIN NOM MAX MIN

MILLIMETERS

−− −− 1.10 −−

INCHES

A1 0.05 0.08 0.15 0.002

b0.25 0.33 0.40 0.010

c0.13 0.18 0.23 0.005

D2.90 3.00 3.10 0.114

E2.90 3.00 3.10 0.114

e0.65 BSC

L0.40 0.55 0.70 0.016

−− 0.043

0.003 0.006

0.013 0.016

0.007 0.009

0.118 0.122

0.026 BSC

0.021 0.028

NOM MAX

4.75 4.90 5.05 0.187 0.193 0.199

ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice

to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any

liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental

damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over

time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under

its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body,

or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death

may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees,

subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of

personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part.

SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.

PUBLICATION ORDERING INFORMATION

N. American Technical Support: 800−282−9855 Toll Free

USA/Canada

Europe, Middle East and Africa Technical Support:

Phone: 421 33 790 2910

Japan Customer Focus Center

Phone: 81−3−5773−3850

NLSX5012/D

LITERATURE FULFILLMENT:

Literature Distribution Center for ON Semiconductor

P.O. Box 5163, Denver, Colorado 80217 USA

Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada

Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada

Email: orderlit@onsemi.com

ON Semiconductor Website: www.onsemi.com

Order Literature: http://www.onsemi.com/orderlit

For additional information, please contact your loc

Sales Representative