MAY 2010
DSC-5301/05
1
©2010 Integrated Device Technology, Inc.
Features
◆◆
◆◆
◆128K x 36 memory configurations
◆◆
◆◆
◆Supports high system speed:
Commercial:
– 200MHz 3.1ns clock access time
Commercial and Industrial:
– 183MHz 3.3ns clock access time
– 166MHz 3.5ns clock access time
◆◆
◆◆
◆LBO input selects interleaved or linear burst mode
◆◆
◆◆
◆Self-timed write cycle with global write control (GW), byte write
enable (BWE), and byte writes (BWx)
◆◆
◆◆
◆3.3V core power supply
◆◆
◆◆
◆Power down controlled by ZZ input
◆◆
◆◆
◆3.3V I/O
◆◆
◆◆
◆Optional - Boundary Scan JTAG Interface (IEEE 1149.1
compliant)
◆◆
◆◆
◆Packaged in a JEDEC Standard 100-pin plastic thin quad
flatpack (TQFP), 119 ball grid array (BGA) and 165 fine pitch ball
grid array
Description
The IDT71V35761 are high-speed SRAMs organized as
128K x 36. The IDT71V35761 SRAMs contain write, data, address and
control registers. Internal logic allows the SRAM to generate a self-timed
write based upon a decision which can be left until the end of the write cycle.
The burst mode feature offers the highest level of performance to the
system designer, as the IDT71V35761 can provide four cycles of data for
a single address presented to the SRAM. An internal burst address
counter accepts the first cycle address from the processor, initiating the
access sequence. The first cycle of output data will be pipelined for one
cycle before it is available on the next rising clock edge. If burst mode
operation is selected (ADV=LOW), the subsequent three cycles of output
data will be available to the user on the next three rising clock edges. The
order of these three addresses are defined by the internal burst counter
and the LBO input pin.
The IDT71V35761 SRAMs utilize IDT’s latest high-performance
CMOS process and are packaged in a JEDEC standard 14mm x 20mm
100-pin thin plastic quad flatpack (TQFP) as well as a 119 ball grid array
(BGA) and 165 fine pitch ball grid array.
Pin Description Summary
A
0
-A
17
Address Inputs Input Synchronous
CE Chip E nab le Inp ut S ync hro no us
CS
0
, CS
1
Chip S e lec ts Inp ut S ync hro no us
OE Output E nable Input Asynchro nous
GW Glo bal Write E nab le Input Synchronous
BWE By te Write Enab le Inp ut S yn chro no us
BW
1
, BW
2
, BW
3
, BW
4
(1)
Indiv idual Byte Write Se le cts Input Synchrono us
CLK Clock Input N/A
ADV Burs t Ad dress Ad vanc e Input Synchrono us
ADSC Ad d re ss Status (Cache Co ntro lle r) Input Synchrono us
ADSP Address Status (Processor) Input Synchronous
LBO Linear / Interleaved Burst Order Input DC
TMS Test Mode Select Input Synchronous
TDI Te s t Data Inp ut Inp ut S ync hro no us
TCK Test Clock Input N/A
TDO Te st Data O utput Ou tp u t S y n c hr o nous
TRST J TAG Re se t (Op tio nal) Input Asynchro nous
ZZ Sleep Mode Input Asynchronous
I/O
0
-I/O
31
, I/O
P1
-I/O
P4
Data Inp ut / Outp ut I/ O S ync hrono us
V
DD
, V
DDQ
Co re P o wer, I/O Po we r Sup p ly N/A
V
SS
Ground Supply N/A
5301 tbl 01
128K x 36
3.3V Synchronous SRAMs
3.3V I/O, Pipelined Outputs
Burst Counter, Single Cycle Deselect
IDT71V35761YS/S
IDT71V35761YSA/SA
6.42
2
IDT71V35761, 128K x 36, 3.3V Synchronous SRAMs with
3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect Commercial and Industrial Temperature Ranges
Pin Definitions(1)
NOTE:
1. All synchronous inputs must meet specified setup and hold times with respect to CLK.
Symbol Pin Function I/O Active Description
A
0
-A
17
Address Inputs I N/A Synchronous Address inputs. The address register is triggered by a combination of the rising edge of CLK
and ADSC Low o r ADSP Lo w and CE Low.
ADSC Address Status
(Cache Co ntrolle r) I LOW Synchro nous Address Status from Cache Controller. ADSC i s an active LOW inp ut that is use d to lo ad the
address registers with new addresses.
ADSP Address Status
(Processor) I LOW Synchronous Address Status from Processor. ADSP i s an active LOW inp ut that is use d to lo ad the add re ss
registers with new addresses. ADSP is gated by CE.
ADV Burst Address
Advance I LOW Synchronous Address Advance. ADV is an activ e LOW inp ut that is use d to advance the inte rnal b urst
co unte r, controlling burst acce ss after the initial ad dress is lo aded. When the input is HIGH the burst counter is
not incremented; that is, there is no address advance.
BWE Byte Write Enable I LOW Synchronous byte write enable gates the byte write inputs BW
1
-BW
4
. If BWE is LOW at the rising edge of CLK
then BWx inputs are passed to the next stage in the circuit. If BWE is HIGH then the byte write inputs are
blocked and only GW can initiate a write cycle.
BW
1
-BW
4
Ind i vi d ual By te
Write Enable s I LOW Synchronous byte write enables. BW
1
controls I/O
0-7
, I/O
P1
, BW
2
controls I/O
8-15
, I/O
P2
, etc. Any active byte
write causes all outputs to be disabled.
CE Chip Enab le I LOW Synchro nous chip e nable. CE is used with CS
0
and CS
1
to e nable the IDT71V35761/781. CE also gate s
ADSP.
CLK Cl o ck I N/A This is the c lo c k i np ut. Al l ti mi ng re fe re nc e s fo r the d e v ic e are mad e wi th re s p e c t to thi s inp ut.
CS
0
Chip Select 0 I HIGH Synchrono us active HIGH chip select. CS
0
is used with CE and CS
1
to e nab le the c hip .
CS
1
Chip Select 1 I LOW Synchronous active LOW chip select. CS
1
is used with CE and CS
0
to e nab le the c hi p .
GW Glob al Write
Enable I LOW Synchronous global write enable. This input will write all four 9-bit d ata bytes when LOW on the rising edge of
CLK. GW supersedes individual byte write enables.
I/O
0
-I/O
31
I/O
P1
-I/O
P4
Data Input/Output I/O N/A Synchronous data input/output (I/O) pins. Both the data input path and data output path are registered and
triggered by the rising edge of CLK.
LBO Linear Burst Order I LOW Asynchronous burst order selection input. When LBO is HIGH, the interleaved burst sequence is selected.
When LBO is LOW the Line ar burst sequence is selected. LBO is a static inp ut and must not chang e state
while the device is operating.
OE Output Enab le I LOW Asynchro nous output e nable . When OE is LOW the data output drivers are enabled on the I/O pins if the chip
is also selected. When OE is HIGH the I/O pins are in a high-impedance state.
TMS Test ModeSelect I N/A Gives input command for TAP controller. Sampled on rising edge of TDK. This pin has an internal pullup.
TDI Te s t Data Inp u t I N/ A Serial input of registers placed be tween TDI and TDO. Sampled on rising edge of TCK. This pin has an
inte rnal pullup.
TCK Test Clock I N/A Clock input of TAP controller. Each TAP event is clocked. Test inputs are captured on rising edge of TCK,
while test outputs a re driven from the falling edge of TCK. This pin has an internal pullup.
TDO Te s t DataOutp ut O N/A Serial output of registers placed between TDI and TDO. This output is active depending on the state of the
TAP controller.
TRST JTAG Reset
(Optional) ILOW
Optional Asynchronous JTAG reset. Can be used to reset the TAP controller, but not required. JTAG reset
occurs automatically at p ower up and also resets using TMS and TCK per IEEE 1149.1. If no t used TRST can
be left floating. This pin has an inte rnal pullup. Only available in BGA package.
ZZ Sleep Mode I HIGH Asynchronous sleep mode input. ZZ HIGH will g ate the CLK inte rnally and power d own the IDT71V35761/35781
to its lowest power consumption level. Data retention is guaranteed in Slee p Mode.This pin has an internal
pull down.
V
DD
Power Supply N/A N/A 3.3V core power supply.
V
DDQ
Power Sup ply N/A N/A 3.3V I/O Supply.
V
SS
Ground N/A N/A Ground.
NC No Connect N/A N/A NC pins are not electrically connected to the device.
5301tbl 02
11
6.42
IDT71V35761, 128K x 36, 3.3V Synchronous SRAMs with
3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect Commercial and Industrial Temperature Ranges
3
Functional Block Diagram
6.42
4
IDT71V35761, 128K x 36, 3.3V Synchronous SRAMs with
3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect Commercial and Industrial Temperature Ranges
100 Pin TQFP Capacitance
(TA = +25°C, f = 1.0MHz)
Recommended Operating
Temperature and Supply Voltage
Absolute Maximum Ratings(1)
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated
in the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect reliability.
2. VDD terminals only.
3. VDDQ terminals only.
4. Input terminals only.
5. I/O terminals only.
6 . This is a steady-state DC parameter that applies after the power supplies have
ramped up. Power supply sequencing is not necessary; however, the voltage
on any input or I/O pin cannot exceed VDDQ during power supply ramp up.
7. TA is the "instant on" case temperature.
Recommended DC Operating
Conditions
NOTES:
1. VIH (max) = VDDQ + 1.0V for pulse width less than tCYC/2, once per cycle.
2. VIL (min) = -1.0V for pulse width less than tCYC/2, once per cycle.
NOTE:
1. This parameter is guaranteed by device characterization, but not production tested.
Symbol Rating Commercial &
Industrial Unit
V
TERM
(2)
Terminal Voltage with
Re sp e c t to GND -0.5 to +4.6 V
V
TERM
(3,6)
Terminal Voltage with
Re sp e c t to GND -0.5 to V
DD
V
V
TERM
(4,6)
Terminal Voltage with
Re sp e c t to GND -0. 5 to V
DD
+0.5 V
V
TERM
(5,6)
Terminal Voltage with
Re sp e c t to GND -0. 5 to V
DDQ
+0.5 V
T
A
(7)
Commercial
Operating Temperature -0 to + 70
o
C
Industrial
Operating Temperature -40 to +85
o
C
T
BIAS
Temperature
Under Bias -55 to +125
o
C
T
STG
Storage
Temperature -55 to +125
o
C
P
T
Po we r Di s sip ati o n 2. 0 W
I
OUT
DC Outp ut Curre nt 50 mA
53 01 t b l 03
Grade Temperature
(1)
V
SS
V
DD
V
DDQ
Co mme rc ial 0° C to +70° C 0V 3.3V ± 5% 3.3V± 5%
Ind ustrial -40°C to +85°C 0V 3.3V± 5% 3.3V± 5%
53 01 t b l 04
Symbol Parameter Min. Typ. Max. Uni
t
V
DD
Core Supply Vo ltage 3.135 3.3 3.465 V
V
DDQ
I/O Sup ply Voltage 3.135 3.3 3.465 V
V
SS
Supply Voltage 0 0 0 V
V
IH
Input High Voltage - Inputs 2.0
____
V
DD
+0.3 V
V
IH
Input High Voltage - I/O 2.0
____
V
DDQ
+0.3
(1)
V
V
IL
Input Low Voltage -0.3
(2) ____
0.8 V
5301 tbl 06
Symbol Parameter
(1)
Conditions Max. Unit
C
IN
Inp ut Cap acitanc e V
IN
= 3dV 5 pF
C
I/O
I/O Cap aci tanc e V
OUT
= 3dV 7 pF
5301 t bl 07
119 BGA Capacitance
(TA = +25°C, f = 1.0MHz)
Symbol Parameter
(1)
Conditions Max. Unit
C
IN
Input Cap ac i tanc e V
IN
= 3dV 7 pF
C
I/O
I/O Cap ac itance V
OUT
= 3dV 7 pF
5301 tbl 07a
NOTES:
1. TA is the "instant on" case temperature.
165 fBGA Capacitance
(TA = +25°C, f = 1.0MHz)
Symbol Parameter
(1)
Conditions Max. Unit
C
IN
Inp ut Cap acitanc e V
IN
= 3dV 7 pF
C
I/O
I/ O Capac itanc e V
OUT
= 3dV 7 pF
5301 tb l 07b
6.42
IDT71V35761, 128K x 36, 3.3V Synchronous SRAMs with
3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect Commercial and Industrial Temperature Ranges
5
Pin Configuration – 128K x 36
100 TQFP
Top View
NOTES:
1. Pin 14 can either be directly connected to VDD, or connected to an input voltage ≥ VIH, or left unconnected.
2. Pin 64 can be left unconnected and the device will always remain in active mode.
10099989796959493929190 8786858483828189 88
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
A
6
A
7
CE
CS
0
BW
4
BW
3
BW
2
BW
1
CS
1
V
DD
V
SS
CLK
GW
BWE
OE
ADSC
ADSP
ADV
A
8
A
9
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
NC
NC
LBO
A
14
A
13
A
12
A
11
A
10
V
DD
V
SS
A
0
A
1
A
2
A
3
A
4
A
5
I/O
31
I/O
30
V
DDQ
V
SS
I/O
29
I/O
28
I/O
27
I/O
26
V
SS
V
DDQ
I/O
25
I/O
24
V
SS
V
DD
I/O
23
I/O
22
V
DDQ
V
SS
I/O
21
I/O
20
I/O
19
I/O
18
V
SS
V
DDQ
I/O
17
I/O
16
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
I/O
14
V
DDQ
V
SS
I/O
13
I/O
12
I/O
11
I/O
10
V
SS
V
DDQ
I/O
9
I/O
8
V
SS
V
DD
I/O
7
I/O
6
V
DDQ
V
SS
I/O
5
I/O
4
I/O
3
I/O
2
V
SS
V
DDQ
I/O
1
I/O
0
5301drw 02
V
DD
/NC
(1)
I/O
15
I/O
P3
NC
I/O
P4
A
15
A
16
I/O
P1
NC
I/O
P2
ZZ
(2)
,
NC
NC
6.42
6
IDT71V35761, 128K x 36, 3.3V Synchronous SRAMs with
3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect Commercial and Industrial Temperature Ranges
Pin Configuration – 128K x 36, 119 BGA
Top View
NOTES:
1. R5 can either be directly connected to VDD, or connected to an input voltage ≥ VIH, or left unconnected.
2. These pins are NC for the "S" version or the JTAG signal listed for the "SA" version. Note: If NC, these pins can either be tied to VSS, VDD or left floating.
3. T7 can be left unconnected and the device will always remain in active mode.
4. TRST is offered as an optional JTAG Reset if required in the application. If not needed, can be left floating and will internally be pulled to VDD.
1234567
AV
DDQ
A
6
A
4
ADSP A
8
A
16
V
DDQ
BNC CS
0
A
3
ADSC A
9
CS
1
NC
CA
7
A
2
V
DD
A
12
A
15
NC
DI/O
16
I/O
P3
V
SS
NC V
SS
I/O
P2
I/O
15
EI/O
17
I/O
18
V
SS
CE V
SS
I/O
13
I/O
14
FV
DDQ
I/O
19
V
SS
OE V
SS
I/O
12
V
DDQ
GI/O
20
I/O
21
BW
3
ADV BW
2
I/O
11
I/O
10
HI/O
22
I/O
23
V
SS
GW V
SS
I/O
9
I/O
8
JV
DDQ
V
DD
NC V
DD
NC V
DD
V
DDQ
KI/O
24
I/O
26
V
SS
CLK V
SS
I/O
6
I/O
7
LI/O
25
I/O
27
BW
4
NC BW
1
I/O
4
I/O
5
MV
DDQ
I/O
28
V
SS
BWE V
SS
I/O
3
V
DDQ
NI/O
29
I/O
30
V
SS
A
1
V
SS
I/O
2
I/O
1
PI/O
31
I/O
P4
V
SS
A
0
V
SS
I/O
0
I/O
P1
RNC A
5
LBO V
DD
A
13
TNC NC A
10
A
11
A
14
NC ZZ
(3)
UV
DDQ
NC/TMS
(2)
NC/TDI
(2)
NC/TCK
(2)
NC/TDO
(2)
NC/TRST
(2,4)
V
DDQ
5301 drw 04
V
DD
/NC
(1)
NC
NC
,
6.42
IDT71V35761, 128K x 36, 3.3V Synchronous SRAMs with
3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect Commercial and Industrial Temperature Ranges
7
Pin Configuration – 128K x 36, 165 fBGA
NOTES:
1. H1 can either be directly connected to VDD, or connected to an input voltage ≥ VIH, or left unconnected.
2. These pins are NC for the "S" version or the JTAG signal listed for the "SA" version. Note: If NC, these pins can either be tied to VSS, VDD or left floating.
3. H11 can be left unconnected and the device will always remain in active mode.
4. Pins P11, N6, B11, A1, R2 and P2 are reserved for 9M, 18M, 36M, 72M, 144M and 288M respectively.
5. TRST is offered as an optional JTAG Reset if required in the application. If not needed, can be left floating and will internally be pulled to VDD.
1234567891011
ANC
(4)
A
7
CE
1
BW
3
BW
2
CS
1
BWE ADSC AD V A
8
NC
BNC A
6
CS
0
BW
4
BW
1
CLK GW OE ADSP A
9
NC
(4)
CI/O
P3
NC V
DDQ
V
SS
V
SS
V
SS
V
SS
V
SS
V
DDQ
NC I/O
P2
DI/O
17
I/O
16
V
DDQ
V
DD
V
SS
V
SS
V
SS
V
DD
V
DDQ
I/O
15
I/O
14
EI/O
19
I/O
18
V
DDQ
V
DD
V
SS
V
SS
V
SS
V
DD
V
DDQ
I/O
13
I/O
12
FI/O
21
I/O
20
V
DDQ
V
DD
V
SS
V
SS
V
SS
V
DD
V
DDQ
I/O
11
I/O
10
GI/O
23
I/O
22
V
DDQ
V
DD
V
SS
V
SS
V
SS
V
DD
V
DDQ
I/O
9
I/O
8
HV
DD
(1)
NC NC V
DD
V
SS
V
SS
V
SS
V
DD
NC NC ZZ
(3)
JI/O
25
I/O
24
V
DDQ
V
DD
V
SS
V
SS
V
SS
V
DD
V
DDQ
I/O
7
I/O
6
KI/O
27
I/O
26
V
DDQ
V
DD
V
SS
V
SS
V
SS
V
DD
V
DDQ
I/O
5
I/O
4
LI/O
29
I/O
28
V
DDQ
V
DD
V
SS
V
SS
V
SS
V
DD
V
DDQ
I/O
3
I/O
2
MI/O
31
I/O
30
V
DDQ
V
DD
V
SS
V
SS
V
SS
V
DD
V
DDQ
I/O
1
I/O
0
NI/O
P4
NC V
DDQ
V
SS NC/TRST
(2,5)
NC
(4)
NC V
SS
V
DDQ
NC I/O
P1
PNCNC
(4)
A
5
A
2
NC/TDI
(2)
A
1
NC/TDO
(2)
A
10
A
13
A
14
NC
(4)
RLBO NC
(4)
A
4
A
3
NC/TMS
(2)
A
0
NC/TCK
(2)
A
11
A
12
A
15
A
16
5301 tb l 1 7
6.42
8
IDT71V35761, 128K x 36, 3.3V Synchronous SRAMs with
3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect Commercial and Industrial Temperature Ranges
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range(1)
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range (VDD = 3.3V ± 5%)
Figure 2. Lumped Capacitive Load, Typical Derating
Figure 1. AC Test Load
AC Test LoadAC Test Conditions
(VDDQ = 3.3V)
NOTE:
1. The LBO, TMS, TDI, TCK & TRST pins will be internally pulled to VDD and the ZZ pin will be internally pulled to VSS if they are not actively driven in the application.
NOTES:
1. All values are maximum guaranteed values.
2. At f = fMAX, inputs are cycling at the maximum frequency of read cycles of 1/tCYC while ADSC = LOW; f=0 means no input lines are changing.
3. For I/Os VHD = VDDQ - 0.2V, VLD = 0.2V. For other inputs VHD = VDD - 0.2V, VLD = 0.2V.
V
DDQ
/2
50Ω
I/O Z
0
=50Ω
5301 d rw 06
,
1
2
3
4
20 30 50 100 200
ΔtCD
(Typical, ns)
Capacitance (pF)
80
5
6
5301 drw 07
,
Symbol Parameter Test Conditions Min. Max. Unit
|I
LI
| Inp ut Le akag e Curre nt V
DD
= Max., V
IN
= 0V to V
DD
___
5µA
|I
LZZ
|ZZ, LBO and JTAG Input Leakage Current
(1)
V
DD
= Max., V
IN
= 0V to V
DD
___
30 µA
|I
LO
| Output Leakage Current V
OUT
= 0V to V
DDQ
, Device Deselected
___
5µA
V
OL
Output Low Vo ltage I
OL
= +8mA, V
DD
= Min.
___
0.4 V
V
OH
Outp ut Hig h Voltag e I
OH
= -8mA, V
DD
= Min. 2.4
___
V
5301 tbl 08
Symbol Parameter Test Conditions
200M Hz 183M Hz 166 MH z
UnitCom'l Com'l Ind Com'l Ind
I
DD
Operating Power Supply
Current D evice S elected, Outputs Open, V
DD
= Max.,
V
DDQ
= Max., V
IN
> V
IH
or < V
IL
, f = f
MAX
(2)
360 340 350 320 330 mA
I
SB1
CMOS Standby Power
Supply Current Device Deselecte d, Outputs Open, V
DD
= Max.,
V
DDQ
= Max., V
IN
> V
HD
or < V
LD
, f = 0
(2,3)
30 30 35 30 35 mA
I
SB2
Clo c k Runni ng Po we r
Supply Current Device Deselecte d, Outputs Open, V
DD
= Max.,
V
DDQ
= Max., V
IN
> V
HD
or < V
LD
, f = f
MAX
(2,3)
130 120 130 110 120 mA
I
ZZ
Full Sleep Mode Supply
Current ZZ > V
HD,
V
DD
= Max. 30 30 35 30 35 mA
5301 tbl 09
Inp ut P ul se Le ve ls
Inp ut Ris e / Fal l Time s
Inp ut Timing Re fe re nc e Le v e ls
Output Timi ng Re fe rence Leve ls
AC Test Load
0 to 3V
2ns
1.5V
1.5V
See Figure 1
53 01 t b l 10
6.42
IDT71V35761, 128K x 36, 3.3V Synchronous SRAMs with
3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect Commercial and Industrial Temperature Ranges
9
Synchronous Truth Table(1,3)
NOTES:
1. L = VIL, H = VIH, X = Don’t Care.
2. OE is an asynchronous input.
3. ZZ = low for this table.
Operation Address
Used CE CS
0
CS
1
ADSP ADSC ADV GW BWE BWxOE
(2) CLK I/O
De se l e c te d Cy c le , P o we r Down No ne H X X X L X X X X X - HI- Z
De se l e c te d Cy c le , P o we r Down No ne L X H L X X X X X X - HI-Z
De se l e c te d Cy c le , P o we r Down No ne L L X L X X X X X X - HI-Z
De se l e c te d Cy c le , P o we r Down No ne L X H X L X X X X X - HI-Z
De se l e c te d Cy c le , P o we r Down No ne L L X X L X X X X X - HI-Z
Read Cycle, Begin Burst External L H L L X X X X X L - D
OUT
Read Cycle, Begin Burst External L H L L X X X X X H - HI-Z
Read Cycle, Begin Burst External L H L H L X H H X L - D
OUT
Read Cycle, Begin Burst External L H L H L X H L H L - D
OUT
Read Cycle, Begin Burst External L H L H L X H L H H - HI-Z
Write Cycle, Begin Burst External L H L H L X H L L X - D
IN
Write Cycle, Begin Burst External L H L H L X L X X X - D
IN
Read Cycl e, Continue Burs t Ne xt X X X H H L H H X L - D
OUT
Read Cycl e, Continue Burs t Ne xt X X X H H L H H X H - HI-Z
Read Cycl e, Continue Burs t Ne xt X X X H H L H X H L - D
OUT
Read Cycl e, Continue Burs t Ne xt X X X H H L H X H H - HI-Z
Read Cycl e, Continue Burs t Ne xt H X X X H L H H X L - D
OUT
Read Cycl e, Continue Burs t Ne xt H X X X H L H H X H - HI-Z
Read Cycl e, Continue Burs t Ne xt H X X X H L H X H L - D
OUT
Read Cycl e, Continue Burs t Ne xt H X X X H L H X H H - HI-Z
Write Cycle, Continue Burst Next X X X H H L H L L X - D
IN
Write Cycle, Continue Burst Next X X X H H L L X X X - D
IN
Write Cycle, Continue Burst Next H X X X H L H L L X - D
IN
Write Cycle, Continue Burst Next H X X X H L L X X X - D
IN
Read Cycle, Suspend Burst Current X X X H H H H H X L - D
OUT
Read Cycle, Suspend Burst Current X X X H H H H H X H - HI-Z
Read Cycle, Suspend Burst Current X X X H H H H X H L - D
OUT
Read Cycle, Suspend Burst Current X X X H H H H X H H - HI-Z
Read Cycle, Suspend Burst Current H X X X H H H H X L - D
OUT
Read Cycle, Suspend Burst Current H X X X H H H H X H - HI-Z
Read Cycle, Suspend Burst Current H X X X H H H X H L - D
OUT
Read Cycle, Suspend Burst Current H X X X H H H X H H - HI-Z
Write Cycle, Suspe nd Burst Current X X X H H H H L L X - D
IN
Write Cycle, Suspe nd Burst Current X X X H H H L X X X - D
IN
Write Cycle, Suspe nd Burst Current H X X X H H H L L X - D
IN
Write Cycle, Suspe nd Burst Current H X X X H H L X X X - D
IN
5301tbl 11
6.42
10
IDT71V35761, 128K x 36, 3.3V Synchronous SRAMs with
3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect Commercial and Industrial Temperature Ranges
Linear Burst Sequence Table (LBO=VSS)
Synchronous Write Function Truth Table(1)
Asynchronous Truth Table(1)
Interleaved Burst Sequence Table (LBO=VDD)
NOTES:
1 . L = VIL, H = VIH, X = Don’t Care.
3. Multiple bytes may be selected during the same cycle.
NOTES:
1 . L = VIL, H = VIH, X = Don’t Care.
2. Synchronous function pins must be biased appropriately to satisfy operation requirements.
NOTE:
1. Upon completion of the Burst sequence the counter wraps around to its initial state.
NOTE:
1. Upon completion of the Burst sequence the counter wraps around to its initial state.
Operation GW BWE BW
1
BW
2
BW
3
BW
4
Read HHXXXX
Read HLHHHH
Write all Byte s L X X X X X
Write all Byte s H L L L L L
Writ e B y te 1
(3)
HLLHHH
Writ e B y te 2
(3)
HLHLHH
Writ e B y te 3
(3)
HLHHLH
Writ e B y te 4
(3)
HLHHHL
5301 tbl 12
Sequence 1 Sequence 2 Sequence 3 Sequence 4
A1 A0 A1 A0 A1 A0 A1 A0
First Address 0 0 0 1 1 0 1 1
Second Address 0 1 1 0 1 1 0 0
Third Address 1 0 1 1 0 0 0 1
Fourth Address
(1)
11000110
5301 tbl 15
Sequence 1 Sequence 2 Sequence 3 Sequence 4
A1 A0 A1 A0 A1 A0 A1 A0
First Address 0 0 0 1 1 0 1 1
Second Address 0 1 0 0 1 1 1 0
Third Address 1 0 1 1 0 0 0 1
Fourth Address
(1)
11100100
5301 tbl 14
Operation
(2)
OE ZZ I/O Status Power
Re ad L L Data Out Ac tive
Read H L High-Z Active
Write X L Hig h-Z – Data In Ac ti ve
Deselected X L High-Z Standby
Sleep Mode X H High-Z Sle ep
5301 tbl 13
6.42
IDT71V35761, 128K x 36, 3.3V Synchronous SRAMs with
3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect Commercial and Industrial Temperature Ranges
11
200MHz
(5)
183MHz 166MHz
Symbol Parameter Min. Max. Min. Max. Min. Max. Unit
t
CYC
Clock Cycle Time 5 — 5.5 — 6 — ns
t
CH
(1)
Clock High Pulse Width 2 — 2.2 — 2.4 — ns
t
CL
(1)
Clock Low Pulse Width 2 — 2.2 — 2.4 — ns
Output Parameters
t
CD
Clo c k Hi g h to Valid Data — 3. 1 — 3. 3 — 3. 5 ns
t
CDC
Cl o ck Hi g h to Data Chan g e 1. 0 — 1. 0 — 1. 0 — ns
t
CLZ
(2)
Cl oc k Hi gh to O u tp u t A c ti ve 0 — 0 — 0 — n s
t
CHZ
(2)
Clo c k Hi g h to Data Hig h-Z 1. 5 3. 1 1. 5 3. 3 1. 5 3 .5 ns
t
OE
Output Enable Access Time — 3.1 — 3.3 — 3.5 ns
t
OLZ
(2)
Outp ut E nable Lo w to Outp ut A c tiv e 0 — 0 — 0 — ns
t
OHZ
(2)
Output Enable High to Output High-Z — 3.1 — 3.3 — 3.5 ns
Set Up Times
t
SA
Address Setup Time 1.2 — 1.5 — 1.5 — ns
t
SS
Ad d re ss S tatus Se tup Time 1.2 — 1.5 — 1.5 — ns
t
SD
Data In Se tup Time 1.2 — 1.5 — 1.5 — ns
t
SW
Write S etup Time 1.2 — 1.5 — 1.5 — ns
t
SAV
Address Advance Setup Time 1.2 — 1.5 — 1.5 — ns
t
SC
Chip Enable/Select Setup Time 1.2 — 1.5 — 1.5 — ns
Ho ld T imes
t
HA
Address Hold Time 0.4—0.5— 0.5— ns
t
HS
Ad d re s s S tatus Ho l d Tim e 0. 4 — 0. 5 — 0. 5 — ns
t
HD
Data In Hold Time 0.4— 0.5— 0.5— ns
t
HW
Write Hold Time 0.4— 0.5— 0.5— ns
t
HAV
Address Advance Hold Time 0.4 — 0.5 — 0.5 — ns
t
HC
Chip Enable/Select Hold Time 0.4— 0.5— 0.5— ns
S leep Mode and Co nfig urati on Pa rameter s
t
ZZPW
ZZ Pulse Width 100 — 100 — 100 — ns
t
ZZR
(3)
ZZ Re cove ry Time 100 — 100 — 100 — ns
t
CFG
(4)
Config uratio n Se t-up Time 20 — 22 — 24 — ns
5301tbl 16
AC Electrical Characteristics
(VDD = 3.3V ±5%, Commercial and Industrial Temperature Ranges)
NOTES:
1. Measured as HIGH above VIH and LOW below VIL.
2. Transition is measured ±200mV from steady-state.
3. Device must be deselected when powered-up from sleep mode.
4. tCFG is the minimum time required to configure the device based on the LBO input. LBO is a static input and must not change during normal operation.
5. Commercial temperature range only.
6.42
12
IDT71V35761, 128K x 36, 3.3V Synchronous SRAMs with
3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect Commercial and Industrial Temperature Ranges
NOTES:
1. O1 (Ax) represents the first output from the external address Ax. O1 (Ay) represents the first output from the external address Ay; O2 (Ay) represents the next output data in the burst sequence
of the base address Ay, etc. where A0 and A1 are advancing for the four word burst in the sequence defined by the state of the LBO input.
2. ZZ input is LOW and LBO is Don't Care for this cycle.
3. CS0 timing transitions are identical but inverted to the CE and CS1 signals. For example, when CE and CS1 are LOW on this waveform, CS0 is HIGH.
Timing Waveform of Pipelined Read Cycle(1,2)
t
CHZ
t
SA
t
SC
t
HS
G
W,BWE,BWx
t
SW
t
CL
t
SAV
t
HW
t
HAV
CLK
ADSC
(1)
ADDRESS
t
CYC
t
CH
t
HA
t
HC
t
OE
t
OHZ
OEt
CD
t
OLZ
O1(Ax)
DATA
OUT
t
CDC
O1(Ay)O3(Ay)O2(Ay)
O2(Ay)
t
CLZ
ADV
CE,CS
1
(Note3)
Pipelined
ReadBurstPipelinedRead
Output
Disabled
AxAy
t
SS
O1(Ay)
(Burstwrapsaround
toitsinitialstate)
O4(Ay)
5301drw08
ADSP
ADVHIGHsuspends
burst
,
6.42
IDT71V35761, 128K x 36, 3.3V Synchronous SRAMs with
3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect Commercial and Industrial Temperature Ranges
13
NOTES:
1. Device is selected through entire cycle; CE and CS1 are LOW, CS0 is HIGH.
2. ZZ input is LOW and LBO is Don't Care for this cycle.
3. O1 (Ax) represents the first output from the external address Ax. I1 (Ay) represents the first input from the external address Ay; O1 (Az) represents the first output from the external address Az; O2 (Az) represents
the next output data in the burst sequence of the base address Az, etc. where A0 and A1 are advancing for the four word burst in the sequence defined by the state of the LBO input.
Timing Waveform of Combined Pipelined Read and Write Cycles(1,2,3)
CLK
ADSP
ADDRESS
GW
ADV
OE
DATA
OUT
t
CYC
t
CH
t
CL
t
HA
t
SW
t
HW
t
CLZ
AxAyAz
t
HS
I1(Ay)
t
SD
t
HD
t
OLZ
t
CD
t
CDC
DAT
A
IN
(2)
t
OE
O1(Az)
O1(Az)
SingleReadPipelinedBurstRead
Pipelined
Write
O1(Ax)
t
OHZ
t
SS
t
SA
O3(Az)
O2(Az)
5301drw09
t
CD
,
6.42
14
IDT71V35761, 128K x 36, 3.3V Synchronous SRAMs with
3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect Commercial and Industrial Temperature Ranges
NOTES:
1. ZZ input is LOW, BWE is HIGH and LBO is Don't Care for this cycle.
2. O4 (Aw) represents the final output data in the burst sequence of the base address Aw. I1 (Ax) represents the first input from the external address Ax. I1 (Ay) represents the first input from the external
address Ay; I2 (Ay) represents the next input data in the burst sequence of the base address Ay, etc. where A0 and A1 are advancing for the four word burst in the sequence defined
by the state of the LBO input. In the case of input I2 (Ay) this data is valid for two cycles because ADV is high and has suspended the burst.
3. CS0 timing transitions are identical but inverted to the CE and CS1 signals. For example, when CE and CS1 are LOW on this waveform, CS0 is HIGH.
Timing Wa vef orm of Write Cyc le No. 1 - GW Controlled(1,2,3)
A
DDRESS
CLK
ADSP
ADSC
t
CYC
t
SS
t
HS
t
CH
t
CL
t
HA
t
SA
AxAyAz
ADV
DAT
A
OUT
OE
t
HC
t
SD
I1(Ax)I1(Az)
I2(Ay)
tHD
t
OHZ
DATA
IN
t
HAV
O3(Aw)O4(Aw)
CE,CS
1
t
HW
GW
t
SW
(Note3)
I2(Az)
BurstWrite
BurstReadBurstWrite
Single
Write
I3(Az)
I4(Ay)
I3(Ay)
I2(Ay)
t
SAV
(ADVHIGHsuspendsburst)
I1(Ay)
GWisignoredwhenADSPinitiatesacycleandissampledonthenextclockrisingedge
t
SC
5301drw10
,
6.42
IDT71V35761, 128K x 36, 3.3V Synchronous SRAMs with
3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect Commercial and Industrial Temperature Ranges
15
Timing Wa ve form of Write Cyc le No. 2 - Byte Controlled(1,2,3)
NOTES:
1. ZZ input is LOW, GW is HIGH and LBO is Don't Care for this cycle.
2. O4 (Aw) represents the final output data in the burst sequence of the base address Aw. I1 (Ax) represents the first input from the external address Ax. I1 (Ay) represents the first input from the external
address Ay; I2 (Ay) represents the next input data in the burst sequence of the base address Ay, etc. where A0 and A1 are advancing for the four word burst in the sequence defined
by the state of the LBO input. In the case of input I2 (Ay) this data is valid for two cycles because ADV is high and has suspended the burst.
3. CS0 timing transitions are identical but inverted to the CE and CS1 signals. For example, when CE and CS1 are LOW on this waveform, CS0 is HIGH.
A
DDRESS
CLK
ADSP
ADSC
t
CYC
t
SS
t
HS
t
CH
t
CL
t
HA
t
SA
AxAy
t
HW
BWx
ADV
DA
T
A
OUT
OE
t
HC
t
SD
Single
WriteBurstWrite
I1(Ax)I2(Ay)I2(Ay)
(ADVsuspendsburst)
I2(Az)
tHD
Burst
ReadExtended
BurstWrite
t
OHZ
DAT
A
IN
t
SAV
t
SW
O4(Aw)
CE,CS
1
t
HW
BWE
t
SW
(Note3)
I1(Az)
Az
I4(Ay)
I1(Ay)I4(Ay)
I3(Ay)
t
SC
BWEisignoredwhenADSPinitiatesacycleandissampledonnextclockrisingedge
BWxisignoredwhenADSPinitiatesacycleandissampledonnextclockrisingedge
I3(Az)
O3(Aw)
5301drw11
,
6.42
16
IDT71V35761, 128K x 36, 3.3V Synchronous SRAMs with
3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect Commercial and Industrial Temperature Ranges
Timing Waveform of Sleep (ZZ) and Power-Down Modes(1,2,3)
t
CYC
t
SS
t
CL
t
CH
t
HA
t
SA
t
SC
t
HC
t
OE
t
OLZ
t
HS
CLK
ADSP
ADSC
A
DDRESS
GW
CE,CS
1
ADV
DATA
OUT
OE
ZZ
SingleReadSnoozeMode
tZZPW
5301drw12
O1(Ax)
Ax
(Note4)
tZZR
Az
,
NOTES:
1. Device must power up in deselected Mode
2. LBO is Don't Care for this cycle.
3. It is not necessary to retain the state of the input registers throughout the Power-down cycle.
4. CS0 timing transitions are identical but inverted to the CE and CS1 signals. For example, when CE and CS1 are LOW on this waveform, CS0 is HIGH.
6.42
IDT71V35761, 128K x 36, 3.3V Synchronous SRAMs with
3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect Commercial and Industrial Temperature Ranges
17
CLK
ADSP
GW,BWE,BWx
CE, CS
1
CS
0
ADDRESS
ADSC
DATA
OUT
OE
Av Aw Ax Ay Az
(Av) (Aw) (Ax) (Ay)
5301 drw 14
,
Non-Burst Read Cycle Timing Waveform
NOTES:
1. ZZ input is LOW, ADV is HIGH and LBO is Don't Care for this cycle.
2. (Ax) represents the data for address Ax, etc.
3. For read cycles, ADSP and ADSC function identically and are therefore interchangable.
NOTES:
1. ZZ input is LOW, ADV and OE are HIGH, and LBO is Don't Care for this cycle.
2. (Ax) represents the data for address Ax, etc.
3. Although only GW writes are shown, the functionality of BWE and BWx together is the same as GW.
4. For write cycles, ADSP and ADSC have different limitations.
Non-Burst Write Cycle Timing Waveform
CLK
ADSP
GW
CE, CS1
CS0
ADDRESS
ADSC
DATAIN
Av Aw Ax AzAy
(Av) (Aw) (Ax) (Az)(Ay)
5301 drw 15
,
6.42
18
IDT71V35761, 128K x 36, 3.3V Synchronous SRAMs with
3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect Commercial and Industrial Temperature Ranges
JTAG Interface Specification (SA Version only)
TCK
Device Inputs
(1)
/
TDI/TMS
Device Outputs
(2)
/
TDO
TRST
(3)
t
JCD
t
JDC
t
JRST
t
JS
t
JH
t
JCYC
t
JRSR
t
JF
t
JCL
t
JR
t
JCH
M5301 drw 01
x
Symbol Parameter Min. Max. Units
t
JCYC
JTAG Clock Input Period 100
____
ns
t
JCH
JTAG Clock HIGH 40
____
ns
t
JCL
JTAG Clock Low 40
____
ns
t
JR
JTAG Clock Rise Time
____
5
(1)
ns
t
JF
JTAG Clock Fall Time
____
5
(1)
ns
t
JRST
JTAG Reset 50
____
ns
t
JRSR
JTAG Reset Recovery 50
____
ns
t
JCD
J TAG D ata O utp ut
____
20 ns
t
JDC
JTAG Data Output Ho ld 0
____
ns
t
JS
JTAG Setup 25
____
ns
t
JH
JTAG Hold 25
____
ns
I5 3 01 tb l 01
Reg i ster Nam e Bi t S i ze
Instruction (IR) 4
Bypass (BYR) 1
JTAG Identific atio n (JIDR) 32
B ound ary Scan (BS R) Note (1)
I5301 tbl 03
NOTES:
1. Device inputs = All device inputs except TDI, TMS and TRST.
2. Device outputs = All device outputs except TDO.
3. During power up, TRST could be driven low or not be used since the JTAG circuit resets automatically. TRST is an optional JTAG reset.
NOTE:
1. The Boundary Scan Descriptive Language (BSDL) file for this device is available
by contacting your local IDT sales representative.
JT A G A C Electrical
Characteristics(1,2,3,4)
Scan Register Sizes
NOTES:
1. Guaranteed by design.
2. AC Test Load (Fig. 1) on external output signals.
3. Refer to AC Test Conditions stated earlier in this document.
4. JTAG operations occur at one speed (10MHz). The base device may run at any speed specified in this datasheet.
6.42
IDT71V35761, 128K x 36, 3.3V Synchronous SRAMs with
3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect Commercial and Industrial Temperature Ranges
19
NOTES:
1. Device outputs = All device outputs except TDO.
2. Device inputs = All device inputs except TDI, TMS, and TRST.
Instruction Field Value Description
Revisio n Numb er (31:28) 0x2 Rese rved fo r version number.
IDT Device ID (27:12) 0x 23C, 0x23E Define s IDT part number 71V35761SA and 71V35781SA, resp ec tive ly.
IDT J EDEC ID (11: 1) 0x 33 A llo ws u ni q ue i d entifi c ati on o f d e vic e ve nd o r as IDT.
ID Register Indicator Bit (Bit 0) 1 Indicates the presence of an ID register.
I5301 tbl 02
JT AG Identification Register Definitions (SA Version only)
Instruction Description OPCODE
EXTEST Forces contents of the bound ary scan cells onto the device outputs
(1)
.
Plac es the bo undary scan re giste r (BSR) b etween TDI and TDO. 0000
SAMPLE/PRELOAD
Plac es the bo undary scan re giste r (BSR) b etween TDI and TDO.
SAMPLE allows data from device inputs
(2)
and outputs
(1)
to be captured
in the bo undary scan ce lls and shifted serially thro ugh TDO. PRELOAD
allow s d ata to be inp ut se rially into the b ound ary s can c ells vi a the TDI.
0001
DEVICE_ID Lo ad s the JTAG ID re g iste r (J IDR) with the v end o r ID c o d e and p lac es
the register betwee n TDI and TDO. 0010
HIGHZ Places the bypass register (BYR) between TDI and TDO. Forces all
de vice outp ut driv ers to a Hig h-Z state. 0011
RESERVED
S eve ral c o mb i natio ns a re re s er ve d . Do n o t use c od e s o the r than thos e
id en ti fie d fo r E XTES T, SAMP LE/ PRE LOA D, DEVICE_ID, HIGHZ, CLAMP,
VALIDATE and BYPASS ins truc tio ns.
0100
RESERVED 0101
RESERVED 0110
RESERVED 0111
CLAMP Uses BYR. Forces contents of the bound ary scan cells onto the device
outputs. Places the byp ass registe r (BYR) between TDI and TDO. 1000
RESERVED
Same as ab ove.
1001
RESERVED 1010
RESERVED 1011
RESERVED 1100
VALIDATE Automatically loaded into the instruction register whenever the TAP
contro lle r p asses throug h the CAPTURE-IR state. The lowe r two b its '01'
are mandate d b y the IEEE s td . 1149.1 s p ec ific atio n. 1101
RESERVED Same as ab ove. 1110
BYPASS The BYPASS instruction is us ed to truncate the b ound ary scan reg ister
as a single bit in le ngth. 1111
I5 3 01 tb l 04
Available JTAG Instructions
6.42
20
IDT71V35761, 128K x 36, 3.3V Synchronous SRAMs with
3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect Commercial and Industrial Temperature Ranges
Ordering Information
Package Information
100-Pin Thin Quad Plastic Flatpack (TQFP)
119 Ball Grid Array (BGA)
165 Fine Pitch Ball Grid Array (fBGA)
Information available on the IDT website
6.42
IDT71V35761, 128K x 36, 3.3V Synchronous SRAMs with
3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect Commercial and Industrial Temperature Ranges
21
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
Datasheet Document History
12/31/99 Created new datasheet from 71v3576 and 71v3578 datasheet.
Pg. 1, 4, 8, 11, 19 Added industrial temperature range offering from 166MHz and 183MHz
04/04/00 Pg. 18 Added 100 pin TQFP package Diagram Outline
Pg. 4 Add BGA capacitance table; Add industrial tempertaure to table; Insert note to Absolute Max
Rating and Recommended Operating Temperature tables
06/01/00 Add new package diagram outline, 13 x 15mm 165fBGA
Pg. 20 Correct BG119 Package Diagram Outline
07/15/00 Pg. 7 Add note reference to BG119 pinout
Pg. 8 Add DNU reference note to BQ165 pinout
Pg. 20 Update BG119 Package Diagram Outline Dimensions
10/25/00 Remove Preliminary status
Pg. 8 Add reference note to N5 on the BQ165 pinout, reserved for JTAG TRST
04/22/03 Pg.4 Updated 165 BGA table information from TBD to 7
06/30/03 Pg. 1,2,3,5-9 Updated datasheet with JTAG information
Pg. 5-8 Removed note for NC pins (38,39(PF package); L4, U4 (BG package) H2, N7 (BQ package))
requiring NC or connection to Vss.
Pg. 19,20 Added two pages of JTAG Specification, AC Electrical, Definitions and Instructions
Pg. 21-23 Removed old package information from the datasheet
Pg. 24 Updated ordering information with JTAG and Y stepping information. Added information
regarding packages available IDT website.
03/02/09 Pg. 21 Removed "IDT" from orderable part number
06/01/10 Pg. 1-21 Added "Restricted hazardous substance device" to the ordering information.
Removed IDT71V35781S/SA from datasheet.
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