1
®
PCM1702
BiCMOS Advanced Sign Magnitude 20-Bit
DIGITAL-TO-ANALOG CONVERTER
DESCRIPTIONFEATURES
●ULTRA LOW –96dB max THD+N
(No External Adjustment Required)
●NEAR-IDEAL LOW LEVEL OPERATION
●GLITCH-FREE OUTPUT
●120dB SNR TYP (A-Weight Method)
●INDUSTRY STD SERIAL INPUT FORMAT
●FAST (200ns) CURRENT OUTPUT
(±1.2mA)
●CAPABLE OF 16X OVERSAMPLING
●COMPLETE WITH REFERENCE
●LOW POWER (150mW typ)
49%
FPO
The PCM1702 is a precision 20-bit digital-to-analog
converter with ultra-low distortion (–96dB typ with a
full scale output). Incorporated into the PCM1702 is
an advanced sign magnitude architecture that elimi-
nates unwanted glitches and other nonlinearities around
bipolar zero. The PCM1702 also features a very low
noise (120dB typ SNR: A-weighted method) and fast
settling current output (200ns typ, 1.2mA step) which
is capable of 16X oversampling rates.
Applications include very low distortion frequency
synthesis and high-end consumer and professional
digital audio applications.
International Airport Industrial Park • Mailing Address: PO Box 11400 • Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd. • Tucson, AZ 85706
Tel: (520) 746-1111 • Twx: 910-952-1111 • Cable: BBRCORP • Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132
Reference
and
Servo
I
OUT
DCOM
LE
Data
Clock
BPO DC
Bipolar Offset
Balanced Current
Segment DAC A
Input Shift Register
and Control Logic
Balanced Current
Segment DAC B
SERV DCRF DC
ACOM
+V
CC
–V
CC
PCM1702P
PCM1702U
© 1993 Burr-Brown Corporation PDS-1175B Printed in U.S.A. June, 1995
®
SBAS026
2
®
PCM1702
SPECIFICATIONS
All specifications at 25°C, ±VCC and +VDD = ±5V unless otherwise noted.
The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes
no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change
without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant
any BURR-BROWN product for use in life support devices and/or systems.
PCM1702P/U, -J, -K
PARAMETER CONDITIONS MIN TYP MAX UNITS
RESOLUTION 20 Bits
DYNAMIC RANGE, THD + N at –60dB Referred to Full Scale, with A-weight 110 dB
DIGITAL INPUT
Logic Family TTL/CMOS Compatible
Logic Level: VIH +2.4 +VDD V
VIL 0 0.8 V
IIH VIH = +VDD ±10 µA
IIL VIL = 0V ±10 µA
Data Format Serial, MSB First, BTC(1)
Input Clock Frequency 12.5 20.0 MHz
TOTAL HARMONIC DISTORTION + N(2)
P/U VO = 0dB fS = 352.8kHz(3), f = 1002Hz(4) –92 –88 dB
VO = –20dB fS = 352.8kHz(3), f = 1002Hz(4) –82 –74 dB
VO = –60dB fS = 352.8kHz(3), f = 1002Hz(4) –46 –40 dB
P/U, -J VO = 0dB fS = 352.8kHz(3), f = 1002Hz(4) –96 –92 dB
VO = –20dB fS = 352.8kHz(3), f = 1002Hz(4) –83 –76 dB
VO = –60dB fS = 352.8kHz(3), f = 1002Hz(4) –48 –42 dB
P/U, -K VO = 0dB fS = 352.8kHz(3), f = 1002Hz(4) –100 –96 dB
VO = –20dB fS = 352.8kHz(3), f = 1002Hz(4) –84 –80 dB
VO = –60dB fS = 352.8kHz(3), f = 1002Hz(4) –50 –44 dB
ACCURACY
Level Linearity At –90dB Signal Level ±0.5 dB
Gain Error ±0.5 ±3%
Bipolar Zero Error(5) ±0.25 %
Gain Drift 0°C to 70°C±25 ppm of FSR/°C
Bipolar Zero Drift 0°C to 70°C±5 ppm of FSR/°C
Warm-up Time 1 minute
IDLE CHANNEL SNR(6) Bipolar Zero, A-weighted Filter 110 120 dB
ANALOG OUTPUT
Output Range ±1.2 mA
Output Impedance 1.0 kΩ
Settling Time (±0.003% of FSR, 1.2mA Step) 200 ns
Glitch Energy No Glitch Around Zero
POWER SUPPLY REQUIREMENTS
Supply Voltage Range: +VCC = +VDD +4.75 +5.00 +5.25 V
–VCC = –VDD –4.75 –5.00 –5.25 V
Combined Supply Current: +ICC +VCC = +VDD = +5V +5.00 +9.0 mA
Combined Supply Current: –ICC –VCC = –VDD = –5V –25.00 –41.0 mA
Power Dissipation ±VCC = ±VDD = ±5V 150 250 mW
TEMPERATURE RANGE
Operating –25 +85 °C
Storage –55 +125 °C
NOTES: (1) Binary Two’s Complement coding. (2) Ratio of (DistortionRMS + NoiseRMS) / SignalRMS. (3) D/A converter sample frequency (8 x 44.1kHz; 8x oversampling).
(4) D/A converter output frequency (signal level). (5) Offset error at bipolar zero. (6) Measured using an OPA627 and 5kΩ feedback and an A-weighted filter.
3
®
PCM1702
Power Supply Voltage ..................................................................±6.5VDC
Input Logic Voltage ........................................... DGND—0.3V~+VDD+0.3V
Operating Temperature..................................................... –25°C to +85°C
Storage Temperature ...................................................... –55°C to +125°C
Power Dissipation ..........................................................................300mW
Lead Temperature (soldering, 5s).................................................... 260°C
ABSOLUTE MAXIMUM RATINGS (SOP Package)
ABSOLUTE MAXIMUM RATINGS (DIP Package)
Power Supply Voltage ..................................................................±6.5VDC
Input Logic Voltage ........................................... DGND—0.3V~+VDD+0.3V
Operating Temperature..................................................... –25°C to +85°C
Storage Temperature ...................................................... –55°C to +125°C
Power Dissipation ..........................................................................500mW
Lead Temperature (soldering, 10s).................................................. 260°C
PIN MNEMONIC PIN MNEMONIC
1 DATA 9 +VCC
2 CLOCK 10 BPO DC
3+V
DD 11 IOUT
4 DCOM 12 ACOM
5–V
DD 13 ACOM
6 LE 14 SERV DC
7 NC 15 REF DC
8NC16–V
CC
PIN ASSIGNMENTS (DIP Package)
PACKAGE INFORMATION(1)
PACKAGE DRAWING
MODEL PACKAGE NUMBER
PCM1702P 16-Pin Plastic DIP 180
PCM1702U 20-Pin Plastic SOP 248
NOTE: (1) For detailed drawing and dimension table, please see end of data
sheet, or Appendix D of Burr-Brown IC Data Book.
PIN MNEMONIC PIN MNEMONIC
1 DATA 11 +VCC
2 CLOCK 12 BPO DC
3NC13NC
4+V
DD 14 IOUT
5 DCOM 15 ACOM
6–V
DD 16 ACOM
7 LE 17 SERV DC
8NC18NC
9 NC 19 RFE DC
10 NC 20 –VCC
PIN ASSIGNMENTS (SOP Package)
GRADE MARKING (SOP Package)
MODEL PACKAGE
PCM1702U Marked PCM1702.
PCM1702U-J Marked with white dot by pin 10.
PCM1702U-K Marked with red dot by pin 10.
CONNECTION DIAGRAM
R
NF
V
OUT
CLOCK
DATA
LE
16
15
14
11
10
9
13
12
47µF
47µF
+
2
1
6
3
4
5 +
+
+5V V
CC
+ +
–5V V
CC
+
+
47µF
100µF
22µF
–5V V
DD
+5V V
DD
47µF
47µF
= SOP
= DIP
2
1
7
4
5
6
20
19
17
14
12
11
16
15
4
®
PCM1702
TYPICAL PERFORMANCE CURVES
All specifications at 25°C, ±VA and ±VD = ±5.0V unless otherwise noted.
THD+N vs FREQUENCY
–40
–60
–100
–120
–80
20 100 1k 10k
Output Frequency (Hz)
THD+N (dB)
–60dB
–40dB
–20dB
0dB
16-BIT LEVEL LINEARITY
(Dithered Fade-to-Noise)
8
6
4
2
0
–2
–4
–6
–8
Deviation from Ideal Level (dB)
–120 Output Signal Level (dB)
–110 –100 –90 –80 –70 –60
16-BIT MONOTONICITY
8.83ms/div
1.5
1
0.5
0
–0.5
–1
–1.5
Output Voltage (mV)
–90dB SIGNAL SPECTRUM
(100Hz Bandwidth)
–80
–100
–120
–140
–160
Power Spectrum (dB)
0 4k 8k 12k 16k 20k
Frequency (Hz)
–90dB SIGNAL
(10Hz to 20kHz Bandwidth)
200
100
0
–100
–200
Output Level (µV)
0 400 800 1200 1600 2000
Time (µs)
–110dB SIGNAL
(10Hz to 20kHz Bandwidth)
40
20
0
–20
–40
Output Level (µV)
0 400 800 1200 1600 2000
Time (µs)
5
®
PCM1702
DISCUSSION OF
SPECIFICATIONS
DYNAMIC SPECIFICATIONS
Total Harmonic Distortion + Noise
The key specifications for the PCM1702 is total harmonic
distortion plus noise (THD+N).
Digital data words are read into the PCM1702 at eight times
the standard compact disk audio sampling frequency of
44.1kHz (352.8kHz) so that a sine wave output of 1002Hz
is realized.
For production testing, the output of the DAC goes to an
I to V converter, then through a 40kHz low pass filter, and
then to a programmable gain amplifier to provide gain at
lower signal output test levels before being fed into an
analog-type distortion analyzer. Figure 1 shows a block
diagram of the production THD+N test setup.
For the audio bandwidth, THD+N of the PCM1702 is
essentially flat for all frequencies. The typical performance
curve, “THD+N vs Frequency”, shows four different output
signal levels: 0dB, –20dB, –40dB, and –60dB. The test
signals are derived from a special compact test disk (the
CBS CD-1). It is interesting to note that the –20dB signal
falls only about 10dB below the full scale signal instead of
the expected 20dB. This is primarily due to the superior low
level signal performance of the advanced sign magnitude
architecture of the PCM1702.
In terms of signal measurement, THD+N is the ratio of
DistortionRMS + NoiseRMS/ SignalRMS expressed in dB. For the
PCM1702, THD+N is 100% tested at all three specified
output levels using the test setup shown in Figure 1. It is
significant to note that this test setup does not include any
output deglitching circuitry. All specifications are achieved
without the use of external deglitchers.
Dynamic Range
Dynamic range in audio converters is specified as the mea-
sure of THD+N at an effective output signal level of –60dB
referred to 0dB. Resolution is commonly used as a theoreti-
cal measure of dynamic range, but it does not take into
account the effects of distortion and noise at low signal
levels. The advanced sign magnitude architecture of the
PCM1702, with its ideal performance around bipolar zero,
provides a more usable dynamic range, even using the strict
audio definition, than any previously available D/A con-
verter.
THEORY OF OPERATION
ADVANCED SIGN MAGNITUDE
Digital audio systems have traditionally used laser-trimmed,
current-source DACs in order to achieve sufficient accuracy.
However, even the best of these suffer from potential low-
level nonlinearity due to errors at the major carry bipolar
zero transition. More recently, DACs employing a different
architecture which utilizes noise shaping techniques and
very high over-sampling frequencies, have been introduced
(“Bitstream”, “MASH”, or 1-bit DAC). These DACs over-
come the low level linearity problem, but only at the expense
of signal-to-noise performance, and often to the detriment of
channel separation and intermodulation distortion if the
succeeding circuitry is not carefully designed.
The PCM1702 is a new solution to the problem. It combines
all the advantages of a conventional DAC (excellent full
scale performance, high signal-to-noise ratio and ease of
use) with superior low-level performance. Two DACs are
combined in a complementary arrangement to produce an
extremely linear output. The two DACs share a common
reference, and a common R-2R ladder for bit current sources
by dual balanced current segments to ensure perfect tracking
under all conditions. By interleaving the individual bits of
each DAC and employing precise laser trimming of resis-
tors, the highly accurate match required between DACs is
achieved.
This new, complementary linear or advanced sign magni-
tude approach, which steps away from zero with small steps
in both directions, avoids any glitching or “large” linearity
errors and provides an absolute current output. The low level
performance of the PCM1702 is such that real 20-bit reso-
lution can be realized, especially around the critical bipolar
zero point.
Table 1 shows the conversion made by the internal logic of
the PCM1702 from binary two’s complement (BTC). Also,
the resulting internal codes to the upper and lower DACs
(see front page block diagram) are listed. Notice that only
the LSB portions of either internal DAC are changing
around bipolar zero. This accounts for the superlative per-
formance of the PCM1702 in this area of operation.
INPUT CODE LOWER DAC CODE UPPER DAC CODE
ANALOG OUTPUT (20-bit Binary Two's Complement) (19-bit Straight Binary) (19-bit Straight Binary)
+Full Scale 011...111 111...111+1LSB(1) 111...111
+Full Scale –1LSB 011...110 111...111+1LSB(1) 111...110
Bipolar Zero +2LSB 000...010 111...111+1LSB(1) 000...010
Bipolar Zero +1LSB 000...001 111...111+1LSB(1) 000...001
Bipolar Zero 000...000 111...111+1LSB(1) 000...000
Bipolar Zero –1LSB 111...111 111...111 000...000
Bipolar Zero –2LSB 111...110 111...110 000...000
–Full Scale +LSB 100...001 000...001 000...000
–Full Scale 100...000 000...000 000...000
NOTE: (1) The extra weight of 1LSB is added at this point to make the transfer function symmetrical around bipolar zero.
TABLE I. Binary Two's Complement to Sign Magnitude Conversion Chart.
6
®
PCM1702
Level Linearity
Deviation from ideal versus actual signal level is sometimes
called “level linearity” in digital audio converter testing. See
the “–90dB Signal Spectrum” plot in the Typical Perfor-
mance Curves section for the power spectrum of a PCM1702
at a –90dB output level. (The “–90dB Signal” plot shows the
actual –90dB output of the DAC). The deviation from ideal
for PCM1702 at this signal level is typically less than
±0.3dB. For the “–110dB Signal” plot in the Typical Perfor-
mance Curves section, true 20-bit digital code is used to
generate a –110dB output signal.
This type of performance is possible only with the low-
noise, near-theoretical performance around bipolar zero of
the PCM1702 advanced sign magnitude.
A commonly tested digital audio parameter is the amount of
deviation from ideal of a 1kHz signal when its amplitude is
decreased form –60dB to –120dB. A digitally dithered input
signal is applied to reach effective output levels of
–120dB using only the available 16-bit code from a special
compact disk test input. See the “16-bit Level Linearity” plot
in the Typical Performance Curves section for the results of
a PCM1702 tested using this 16-bit dithered fade-to-noise
signal. Note the very small deviation from ideal as the signal
goes from –60dB to –100dB.
DC SPECIFICATION
Idle Channel SNR
Another appropriate specification for a digital audio con-
verter is idle channel signal-to-noise ratio (idle channel
SNR). This is the ratio of noise on the DAC output at bipolar
zero in relation to the full scale range of the DAC. To make
this measurement, the digital input is continuously fed the
code for bipolar zero, while the output of the DAC is band-
limited from 20Hz to 20kHz and an A-weighted filter is
applied. The idle channel SNR for the PCM1702 is typically
greater than 120dB, making it ideal for low-noise applica-
tions.
Monotonicity
Because of the unique advanced sign magnitude architecture
of the PCM1702, increasing values of digital input will
always result in increasing values of DAC output as the
signal moves away from bipolar zero in one-LSB steps (in
either direction). The “16-bit Monotonicity” plot in the
Typical Performance Curves section was generated using
16-bit digital code from a test compact disk. The test starts
with 10 periods of bipolar zero. Next are 10 periods of
alternating 1LSBs above and below zero, and then 10
periods of alternating 2LSBs above and below zero, and so
on until 10LSBs above and below zero are reached. The
signal pattern then begins again at bipolar zero.
With PCM1702, the low-noise steps are clearly defined and
increase in near-perfect proportion. This performance is
achieved without any external adjustments. By contrast,
sigma-delta (“Bit-stream”, “MASH”, or 1-bit DAC) archi-
tectures are too noisy to even see the first 3 or 4 bits change
(at 16 bits), other than by a change in the noise level.
Absolute Linearity
Even though absolute integral and differential linearity specs
are not given for the PCM1702, the extremely low THD+N
performance is typically indicative of 17-bit integral linearity
in the DAC. The relationship between THD+N and linearity,
however, is not such that an absolute linearity specification
for every individual output code can be guaranteed.
Offset, Gain, and Temperature Drift
Although the PCM1702 is primarily meant for use in dy-
namic applications, specifications are also given for more
traditional DC parameters such as gain error, bipolar zero
offset error, and temperature gain and offset drift.
DIGITAL INPUT
Timing Considerations
The PCM1702 accepts TTL compatible logic input levels.
The data format of the PCM1702 is binary two’s comple-
ment (BTC) with the most significant bit (MSB) being first
FIGURE 1. Production THD+N Test Setup.
Timing
Logic
Binary
Counter Digital Code
(EPROM) Parallel-to-Serial
Conversion DUT
(PCM1702)
I to V
Converter
OPA627
Distortion
Analyzer
Programmable
Gain Amp
0dB to 60dB
Low-Pass Filter
40kHz 3rd Order
GIC Type
DATA
(Shiba Soku Model
725 or Equivalent)
Use 400Hz High-Pass
Filter and 30kHz
Low-Pass Filter
Meter Settings
Sampling Rate = 44.1kHz x 8(352.8kHz)
Output Frequency = 1002Hz
LE (Latch Enable)
CLOCK
7
®
PCM1702
in the serial input bit stream. Table II describes the exact
relationship of input data to voltage output coding. Any
number of bits can precede the 20 bits to be loaded, since
only the last 20 will be transferred to the parallel DAC
register after Latch Enable (Pin6 <PCM1702P>, Pin7
<PCM1702U>, LE) has gone low.
All DAC serial input data (Pin1, DATA) bit transfers are
triggered on positive clock (Pin2, CLOCK), edges. The
serial-to-parallel data transfer to the DAC occurs on the
falling edge of Latch Enable. The change in the output of the
DAC occurs at a rising edge of the 4th clock of the CLOCK
after the falling edge of Latch Enable. Refer to Figure 2 for
graphical relationships of these signals.
Maximum Clock Rate
A typical clock rate of 16.9MHz for the PCM1702 is derived
by multiplying the standard audio sample rate of 44.1kHz by
sixteen times (16X over-sampling) the standard audio word
bit length of 24 bits (44.1kHz x 16 x 24 = 16.9MHz). Note
that this clock rate accommodates a 24-bit word length, even
though only 20 bits are actually being used. The setup and
hold timing relationships are shown in Figure 3.
“Stopped Clock” Operation
The PCM1702 is normally operated with a continuous clock
input signal. If the clock is to be stopped between input data
words, the last 20 bits shifted in are not actually shifted from
the serial register to the latched parallel DAC register until
Latch Enable goes low. Latch Enable must remain low until
after the first clock cycle of the next data word to insure
proper DAC operation. In any case, the setup and hold times
for Data and LE must be observed as shown in Figure 3.
INSTALLATION
POWER SUPPLIES
Refer to CONNECTION DIAGRAM for proper connection
of the PCM1702. The PCM1702 only requires a ±5V sup-
ply. Both positive supplies should be tied together at a single
point. Similarly, both negative supplies should be connected
together. No real advantage is gained by using separate
analog and digital supplies. It is more important that both
these supplies be as “clean” as possible to reduce coupling
of supply noise to the output. Power supply decoupling
capacitors should be used at each supply pin to maximize
power supply rejection, as shown in CONNECTION DIA-
GRAM regardless of how good the supplies are. Both
commons should be connected to an analog ground plane as
close to the PCM1702 as possible.
FILTER CAPACITOR REQUIREMENTS
As shown in CONNECTION DIAGRAM, various size
decoupling capacitors can be used, with no special tolerances
being required. The size of the offset decoupling capacitor is
not critical either, with larger values (up to 100µF) giving
slightly better SNR readings. All capacitors should be as close
to the appropriate pins of the PCM1702 as possible to reduce
noise pickup from surrounding circuitry.
> 15ns > 15ns
> 40ns
LSBData Input MSB
> 20ns > 20ns
> 15ns
> One Clock Cycle > One Clock Cycle
Latch
Enable
Clock
Input
> 15ns
DIGITAL INPUT ANALOG OUTPUT CURRENT OUTPUT
1,048,576LSBs Full Scale Range 2.40000000mA
1LSB NA 2.28882054nA
7FFFFHEX +Full Scale –1.19999771mA
00000HEX Bipolar Zero –1LSB 0.00000000mA
80000HEX –Full Scale +1.20000000mA
TABLE II. Digital Input/Output Relationships. FIGURE 3. Setup and Hold Timing Diagram.
FIGURE 2. Timing Diagram.
1234 13141516171819201
MSB LSB
Data
Clock
Latch
Enable
NN-1
I
OUT
12
DATA "N"
NOTES : (1) If clock is stopped between input of 20-bit data words, "Latch" Enable (LE) must remain low until after the first clock cycle of the next 20-bit data
word stream. (2) Data format is binary two's complement (BTC). Individual data bits are clocked in on the corresponding positive clock edge. (3) Latch Enable
(LE) must remain low at least one clock cycle after going negative. (4) Latch Enable (LE) must be high for at least one clock cycle before going negative. (5)
IOUT changes on positive going edge of the 4th clock after negative going edge of Latch Enable (LE).
8
®
PCM1702
FIGURE 4. Typical Application for Stereo Audio 8X Oversampling system.
1MΩ
16.9344MHz
2
1
11
10
5
4
3
8X Interpolation
Digital Filter
17 22
3
+5V
23
100pF 14 2116
4.7µF
1
28
226
25
24
4.7µF
6
104
Digital Interface
Format Receiver
17
+5V
8
4700pF
314
5
612
15
17
0.1µF
28
4
4.7µF
Ω17.1k
+5V
(192F )
S
10pF10pF
Interleaved
Digital
Input
150Ω
φ
A
BCO
L/R
DA
Yamaha
YM3623
PCM1702P
Burr-Brown
DF1700P
8
DOR
BCO
WCK
DOL
4.7µF
+5V
+
+
+
6
BCK
DATA
GND
–5V
LE
C
42
3.3µF
+
C
44
3.3µF
+
13
12
16
14
15
C
54
100µF
+
C
48
3.3µF
+
9
+5V
BPO DC
I
OUT
C
50
100µF
+C
52
100µF
+
C
46
3.3µF
+
–5V V
CC
+5V V
CC
–5V V
CC
C
56
220p
RF
2
2.5kΩ
–5V
2
1
11
10
5
4
3
PCM1702P
+5V
6
BCK
DATA
GND
–5V
LE
C
41
3.3µF
+
C
49
3.3µF
+
13
12
16
14
15
C
54
100µF
+
C
47
3.3µF
+
9
+5V
BPO DC
I
OUT
C
49
100µF
+C
51
100µF
+
C
45
3.3µF
+
+5V V
CC
–5V V
CC
C
55
220p
RF
2
2.5kΩ
–5V
+5V V
CC
R
21
2kΩ
V
O
C
62
1000pF
Low-pass
3-pole Butterworth
f
–3dB
= 40kHz
R
13
6.04kΩR
17
4.02kΩ
R
18
4.02kΩ
C
60
1000pF
C
59
1000pF
R
19
5.36kΩ
R
20
2kΩ
V
O
C
61
1000pF
Low-pass
3-pole Butterworth
f
–3dB
= 40kHz
R
12
6.04kΩR
14
4.02kΩ
R
15
4.02kΩ
C
58
1000pF
C
57
1000pF
R
16
5.36kΩ
See Application Bulletin AB-026
for information on GIC filters.
IC3
IC3
IC4
IC4
IC1
IC2
IC1-4: OPA2604
IC2
IC1
PACKAGING INFORMATION
Orderable Device Status (1) Package
Type Package
Drawing Pins Package
Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
PCM1702P ACTIVE PDIP N 16 25 Green (RoHS &
no Sb/Br) CU NIPDAU N / A for Pkg Type
PCM1702P-J ACTIVE PDIP N 16 25 Green (RoHS &
no Sb/Br) CU NIPDAU N / A for Pkg Type
PCM1702P-JG4 ACTIVE PDIP N 16 25 Green (RoHS &
no Sb/Br) CU NIPDAU N / A for Pkg Type
PCM1702P-K ACTIVE PDIP N 16 25 Green (RoHS &
no Sb/Br) CU NIPDAU N / A for Pkg Type
PCM1702P-KG4 ACTIVE PDIP N 16 25 Green (RoHS &
no Sb/Br) CU NIPDAU N / A for Pkg Type
PCM1702PG4 ACTIVE PDIP N 16 25 Green (RoHS &
no Sb/Br) CU NIPDAU N / A for Pkg Type
PCM1702U ACTIVE SO NS 20 38 Pb-Free
(RoHS) CU SNBI Level-2-260C-1 YEAR
PCM1702U-J ACTIVE SO NS 20 38 Pb-Free
(RoHS) CU SNBI Level-2-260C-1 YEAR
PCM1702U-J/2KE6 ACTIVE SO NS 20 TBD Call TI Call TI
PCM1702U-JE6 ACTIVE SO NS 20 38 Pb-Free
(RoHS) CU SNBI Level-2-260C-1 YEAR
PCM1702U-K ACTIVE SO NS 20 38 Pb-Free
(RoHS) CU SNBI Level-2-260C-1 YEAR
PCM1702U-K/2KE6 ACTIVE SO NS 20 TBD Call TI Call TI
PCM1702U-KE6 ACTIVE SO NS 20 38 Pb-Free
(RoHS) CU SNBI Level-2-260C-1 YEAR
PCM1702U/2K ACTIVE SO NS 20 2000 Pb-Free
(RoHS) CU SNBI Level-2-260C-1 YEAR
PCM1702U/2KE6 ACTIVE SO NS 20 2000 Pb-Free
(RoHS) CU SNBI Level-2-260C-1 YEAR
PCM1702UE6 ACTIVE SO NS 20 38 Pb-Free
(RoHS) CU SNBI Level-2-260C-1 YEAR
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
PACKAGE OPTION ADDENDUM
www.ti.com 20-Mar-2008
Addendum-Page 1
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
PACKAGE OPTION ADDENDUM
www.ti.com 20-Mar-2008
Addendum-Page 2
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