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L6574
September 2003
■HIGH VOLTAG E RAIL UP TO 600V
■dV/dt IMMUNI TY ± 50 V /ns IN FULL
TEMPERATURE RANGE
■DRIVER CURRENT CAPABILITY:
250mA SOURCE
450mA SINK
■SWITCHING TIM ES 80/40ns RISE/FAL L
■WITH 1nF LOA D
■CMOS SHUT DOWN INPUT
■UNDER VOLTAGE LOCK OUT
■PREHEAT AND FREQUENCY SHIFTING
TIMING
■SENSE OP AMP FOR CLOSED LOOP
CONTROL OR PRO TECTION FEATURES
■HIGH ACCURACY CURRE NT CONTROLLED
OSCILLATOR
■INTEGRATED BOOTSTRAP DIODE
■CLAMPING ON VS.
■SO16, DIP 16 PACKAGES
DESCRIPTION
In order to ensure voltage ratings in excess of
600V, the L6574 is manufactured with BCD OFF
LINE technology, which makes it well suited for
lamp ballast applications.
The device is intended to drive two power MOS-
FETS, in the classical hal f bridge topology, ensur-
ing all the features needed to drive and properly
control a fluorescent bulb.
A dedicated timing section in the L6574 allows the
user set the necessary par ameters for proper pre-
heat and ignition of the lamp.
Also, an OP AMP is available to implement closed
loop control of the lamp current during normal
lamp burning.
An in teg ra ted b oots tr ap sec tio n, el imin at in g th e nor-
mally required bootstrap diode and the zener clamp-
ing on Vs, makes the L6574 well suited for low cost
applications where few additional components are
needed to build a high performance ballast.
SO16N DIP16
ORDERING NUMBERS:
L6574D L6574
CFL/TL BALLAST DRIVER PREHEAT AND DIM MING
BLOCK DIAGRAM
GND
VREF
Imin
RING
VCO
EN1
VTHE
VTHE
EN2
VS
VBOOT
OUT
CBOOT
LOAD
H.V.
LVG
UV
DETECTION
VS
HVGBOOTSTRAP
DRIVER HVG
DRIVER
LVG DRIVER
Vthpre
Ifs
CPRE
VREF
Imax
RPRE
Cf
OP AMP +
-
OPOUT
OPIN-
OPIN+
DEAD
TIME DRIVING
LOGIC
CONTROL
LOGIC
+
-
Ipre
+
-
+
-
+
-
LEVEL
SHIFTER
D97IN493A
L6574
2/10
PIN CONNECTION (top view)
THE RMAL DA TA
Symbol Parameter DIP16 SO16N Unit
R
th j-amb
Thermal Resistance Junction to ambient Max. 80 120 °C/W
PIN DESCRIPTION
N° Pin Function
1 CPRE Preheat Timing Ca pacitor. The ca pacitor C PRE sets the prehea ting a nd the frequ ency shift tim e,
according to the relations: tPRE = KPRE · CPRE and tSH = KFS · CPRE (typ. KPRE = 1.5s/µF, KFS =
0.15s/µF). This feature is obtained by charging CPRE with two different currents. During tPRE
this current is independent of the external components, so CPRE is charged up to 3.5V (preheat
timing co mparator thr eshold). D uring tSH the c urrent dep ends on RPRE valu e (i.e. on the differ-
ence between fPRE and fIGN). In this way tSH is always set at 0.1tPRE. In steady state the voltage
at pin 1 is 5V.
2 RPRE Maximum Oscillation Frequency Setting. The resistance connected between this pin and ground
sets the fPRE value, fixing the differen ce between fPRE and fIGN (f PRE > f IGN). At the end of the
Start -up proce dure, the effect current drow n from RPRE is over. Th e voltage at this pin is fixed at
VREF =2V.
3 CF Oscillator Frequency Setting. The capacitor CF, along with to RPRE and RIGN, sets fPRE and fING.
In normal operation this pin shows a triangular wave.
4 RIGN Minimum O scilla tion Fre quen cy Set ting. Th e resis tance con nect ed betw een th is pin a nd grou nd
sets the fIGN value. The voltage at this pin is fixed at VREF =2V.
5 OPout Out of the operational amplifier. To implement a feedback control loop this pin can be connected
to the RIGN pin by means an appropriate circuitry.
6 OPin- Inverting Input of the operational amplifier.
7 OPin+ Non Inverting Input of the operational amplifier.
8 EN1 Enable 1. This pin (active high), forces the device in a latched shutdown state (like in the under
voltage conditions). There are two ways to resume normal operation:
– the first is to reduce the supply voltage below the undervoltage threshold and then
increase it again until the valid supply is recognised.
– the second is activating EN2 input.
The enable 1 is especially designed for strong fault (e.g. in case of lamp disconnection).
CPRE
RPRE
CF
RING
OPOUT
OPIN+
OPIN-
1
3
2
4
5
6
7 GND
VS
LVG
N.C.
OUT
HVG
VBOOT16
15
14
13
12
10
11
D97IN492
EN1 8 EN29
3/10
L6574
ABSOLUTE MAXIMUM RATINGS
(*) The device has an i nternal Clamping Zener between GND and the V
CC
pin, i t must not be supplied by
a Low Impedance Voltage Source.
Note: ESD i mmunity for pins 14, 15 and 16 is guarant eed up to 900V (Human Body Model)
9 EN2 Enable 2. EN2 input (active high) restarts the start-up procedure (preheating and ignition
sequence). This features is useful if the lamp does not turn-on after the first ignition sequence .
10 GND Ground.
11 LVG Low Side Driver Output. This pin must be connected to the low side power MOSFET gate of the
half bridge. A resistor connected between this pin and the power MOS gate can be used to
reduce the peak current.
12 VS Supply Voltage. This pin, connected to the supply filter capacitor, is internally clamped (15.6V
typical).
13 N.C. Non Connec ted. Thi s pin set a distance between the pins rela ted to the HV and those rela ted to
the LV side.
14 OUT High Side Driver Floating Reference. This pin must be connected close to the source of the high
side power MOS or IGBT.
15 HVG High Side Driver Output. This pin must be connected to the high side power MOSFET gate of the
half bridge. A resistor connected between this pin and the power MOS gate can be used to
reduce the peak current.
16 VBOOT Bootstrapped Supply Voltage. Between this pin and VS must be connected the bootstrap capac-
itor. A patented integrated circuitry replaces the external bootstrap diode, by means of a high
voltage DMOS, synchronously driven with the low side power MOSFET.
Symbol Parameter Value Unit
I
S
Supply Current (*) 25 mA
V
LVG
Low Side Output -0.3 to Vs +0.3 V
V
OUT
High Side Reference -1 to VBOOT -18 V
V
HVG
High Side Output -1 to VBOOT V
V
BOOT
Floating Supply Voltage -1 to 618 V
dV
BOOT
/dt V
BOOT
pin Slew rate (repetitive) ±50 V/ns
dV
OUT
/dt OUT pin Slew Rate (repetitive) ±50 V/ns
V
ir
Forced Input Voltage (pins Ring, Rpre) -0.3 to 5 V
V
ic
Forced Input Voltage (pins Cpre, Cf) -0.3 to 5 V
V
EN1
, V
EN2
Enable Input Voltage -0.3 to 5 V
I
EN1
, I
EN2
Enable Input Current ±3mA
V
opc
Sense Op Amp Common Mode Range -0.3 to 5 V
V
opd
Sense Op Amp Differential Mode Range ±5V
V
opo
Sense Op Amp Output Voltage (forced) 4.6 V
T
stg
, T
j
Storage Temperature -40 to +150 °C
T
amb
Ambient Temperature -40 to +125 °C
PIN DESCRIPTION (co ntinued)
N° Pin Function
L6574
4/10
RECOMMENDED OPERATING CONDITIONS
(*) If the conditi on Vboot - Vo ut < 1 8 i s guaranteed, Vo ut can range f rom -3 to 580V.
Symbol Parameter Value Unit
V
S
Supply Voltage 10 to V
CL
V
V
OUT
(*) High Side Reference -1 to V
BOOT
-V
CL
V
V
BOOT
(*) Floating Supply Voltage 500 V
ELECTRICAL CHARACTERISTCS
(V
S
= 12V; V
BOOT
-V
OUT
= 12V; T
amb
= 25°C)
Symbo l Pin Pa rameter Test Condition Min. Typ. M ax. Unit
Supply Voltage
V
suvp
12 V
s
Turn On Threshold 9.5 10.2 10.9 V
V
suvn
V
s
Turn Off Threshold 7.3 8 8.7 V
V
suvh
Supply Voltage Under Voltage
Hysteresys 2.2 V
V
cl
Supply Voltage Clamping 14.6 15.6 16.6 V
I
su
Start Up Current V
S
< V
suvn
250 µA
I
q
Quiescent Current, fout = 60kHz,
no load. V
S
> V
supv
2mA
High voltage Section
I
bootleak
16 BOOT pin leakage current V
BOOT
= 580V 5 µA
I
outleak
14 OUT pin Leakage Current V
OUT
= 562V 5 µA
High/Low Side Drivers
I
hvgso
15 High Side Driver Source Current V
HVG
-V
OUT
= 0 170 250 mA
I
hvgsi
15 High Side Driver Sink Current V
HVG
-V
BOOT
= 0 300 450 mA
I
hvgso
11 Low Side Drive Source Current VLVG-GND = 0 170 250 mA
I
lvgsi
11 Low Side Drive Source Current V
LVG
-V
S
= 0 300 450 mA
t
rise
15,
11 Low/High Side Output Rise Time C
load
= 1nF 80 120 ns
t
fall
Low/High Side Output Fall Time C
load
= 1nF 50 80 ns
Oscillator
DC14 Output Duty Cycle 48 50 52 %
f
ing
14 Minimum Output Oscillatio n
Frequency C
F
= 470pF;
R
ing
= 50kΩ58.2 60 61.8 kHz
f
pre
14 Maximum Output Oscillation
Frequency C
F
= 470pF;
R
ing
= 50kΩ;
R
pre
= 47kΩ
114 120 126 kHz
V
ref
2,4 Voltage to current converters
threshold 1.9 2 2.1 V
I
Vref
2,4 Reference Current 0 120 µA
t
d
14 Dead Time between Low and
High Side Conduction 0.8 1.25 1.7 µs
5/10
L6574
High/Low Side Driving Section:
High and low side driving sections pro vide the proper drive to the e xternal power MOSFET. A high sink/
source driving current (450/250 mA typical) ensures fast switching times when a size 4 external power
MOSFE T needs to be driven.
Boo ts tr ap S e ct io n:
A patent ed i nte grated bootstrap section replaces an external boo tstra p di ode. This section tog ether wit h
a bootstrap capacitor provides the bootstrap voltage to drive the high side power MOSFET. This function
is achieved using a high voltage DMOS driver which is driven synchronou sly with the low side external
power MOSFET.
For a saf e operation, current flow int o the Vboot pi n is inhibited, even though ZVS opera tion m ay n ot be
ensured.
Tim in g S ec tio n:
To set the proper preheat time (tpre=kpre*Cpre) for the bulb, a capacitor is connected to the Cpre pin
which is charged with a fixed current. During tpre, the output is switching at fpre (see Oscillator Section).
When the t pre expires, the Cpre capacitor is discharged and then recharged wi th a different current. This
sets a second time interv al tsh (0.1 times the sele cted preheat time tp re) during which frequency shifting
from fpre to fing is perf ormed to ensure lamp ignition.
Timing Section
k
pre
1 Pre Heat Timing constan t C
pre
= 330nF 1.15 1.5 1.85 s/µF
k
fs
Frequency Shift Timing Constant C
pre
= 330nF 0.115 0.15 0.185 s/µF
V
thpre
Pre Heat Timing Compar ator
Threshold 3.3 3.5 3.7 V
Sense OP AMP
l
ib
6,7 Input Bias current 0.1 µA
V
io
Input Offset Voltage -10 10 mV
R
out
5 Ouput Resistance 200 300 Ω
I
out +
Sink Output Current V
out
= 0.2V 0.5 mA
I
out -
Source Output Current V
out
= 4.5V 0.5 mA
V
ic
6,7 Common Mode Input Range -0.2 3 V
GBW Sense Op Amp Gain Band Width
Product 1MHz
Gdc DC Open Loop Gain 80 dB
Comparators
V
the
8,9 Enabling Comparators Thres hold 0.56 0.6 0.64 V
V
hy
e Enabling Compar ators Hyste resis 20 100 mV
t
pulse
Minimum Pulse lenght 200 ns
ELECTRICAL CHARACTERISTCS (continued)
(V
S
= 12V; V
BOOT
-V
OUT
= 12V; T
amb
= 25°C)
Symbo l Pin Pa rameter Test Condition Min. Typ. M ax. Unit
L6574
6/10
Oscillator Section:
A voltage c ontrolled oscill ato r, wi th the s elected frequenci es fpre and fing, drives t he output ha lf bridge.
Independently selected, fpre is effec tive during tpre and fing is effective during normal lamp burning. When
working open loop, fpre and fing are the highest and lowest allowed oscillation frequencies.
Closed loop control of the lamp current under norma l operation can be achiev ed with the L6 574. This is
accomplished by automatic adjust ment of the osc illator frequency. The OP AMP out put is fed through a
resistor diode network to the Ring pin. See AN 993.
OP AMP Sec tion :
The integrated OP AMP offers low output imped ance, wide bandwidth, hi gh input impedance and wide
common mode r ange. I t can be read ily us ed to implement c losed l oop c ontr ol (s ee Os c illa tor S ec tion) of
the lamp current.
EN1, EN2 Comparators:
Two CMOS comparators, with thresholds set at 0.6 V (t ypical ) are available to implement protection meth-
ods (such as overvoltage, lamp rem oval, etc.). Short pulses (>200nsec) at the comparator inputs are rec-
ognized.
The E N1 input (a ctive hig h) forc es the L6574 i n the shut do wn stat e (e.g. L VG l ow, HV G low , osc illator
stopped) in the event of an undervoltage condition. Normal operating condition is resumed after a power-
off power-on sequence or when EN2 input is high.
The EN2 input (active high) also restarts a preheat sequence (see timing diagram s).
TIMING DIAGRAMS
VCC
LVG
HVG
EN1
VSUVP
D97IN490
V
CC
t
PRE
t
PRE
t
SH
t
SH
f
PRE
f
ING
EN2
f
OUT
V
SUVP
D97IN491B
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L6574
Figure 1. f
ING
vs. R
ING
.
Figure 2. ∆f vs. R
PRE
, with R
ING
= 33kΩ
Figure 3. ∆f vs. R
PRE
, with R
ING
= 50kΩ
Figure 4. ∆f vs. R
PRE
, with R
ING
= 100kΩ
Figure 5. f
ING
vs. t empera tur e.
Figure 6. f
PRE
vs. temperature.
20 40 60 80 100 RING(KΩ)
20
40
60
80
100
fING
(KHz)
D98IN867
20 40 60 80 100 RPRE(KΩ)
20
40
60
80
∆f
(KHz)
D98IN868
RING=33KΩ
20 40 60 80 100 RPRE(KΩ)
20
40
60
80
100
∆f
(KHz)
D98IN869
RING=50KΩ
20 40 60 80 100RPRE(KHΩ)
20
40
60
80
100
∆f
(KHz)
D98IN870
RING=100KΩ
-50 0 50 100
40
50
60
70
D98IN871
T
(
˚C
)
fING
(KHz)
-50 0 50 100
100
110
120
130
D98IN872
T
(
˚C
)
fPRE
(KHz)
L6574
8/10
SO16 Narrow
DIM. mm inch
MIN. TYP. MAX. MIN. TYP. MAX.
A 1.75 0.069
a1 0.1 0.25 0.004 0.009
a2 1.6 0.063
b 0.35 0.46 0.014 0.018
b1 0.19 0.25 0.007 0.010
C 0.5 0.020
c1 45˚ (typ.)
D (1) 9.8 10 0.386 0.394
E 5.8 6.2 0.228 0.244
e 1.27 0.050
e3 8.89 0.350
F (1) 3.8 4 0.150 0.157
G 4.6 5.3 0.181 0.209
L 0.4 1.27 0.016 0.050
M 0.62 0.024
S
(1) D and F do not include mold flash or protrusions. Mold flash or potrusions shall not exceed 0.15mm (.006inch).
OUTLINE AND
MECHANICAL DATA
8˚(max.)
0016020
Weight: 0.20gr
9/10
L6574
DIP16
DIM. mm inch
MIN. TYP. MAX. MIN. TYP. MAX.
a1 0.51 0.020
B 0.77 1.65 0.030 0.065
b 0.5 0.020
b1 0.25 0.010
D 20 0.787
E 8.5 0.335
e 2.54 0.100
e3 17.78 0.700
F 7.1 0.280
I 5.1 0.201
L 3.3 0.130
Z 1.27 0.050
OUTLINE AND
MECHANICAL DATA
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no r esponsibility for the consequences
of use of such information nor for any inf ringement of patents or other rights of third parties which may result from its use. No license is granted
by i m pl i cation or oth erwise under any pat ent or paten t rights of STMi croelectronic s. Specifications m entioned in this publicati on are subject
to change without notice. This publication supersedes and replaces all information previous ly supplied. STMicroelectronics products ar e not
authorized f or use as c ri tical com ponents in lif e support devices or systems wi t hout exp ress writ ten approval of STM i croelectronics.
Th e ST logo is a register ed tradem ark of STM i croel ectronic s.
All o th er names are the propert y of their re spectiv e owners
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L6574
