MAX7500–MAX7504
Shutdown
Set bit D0 in the configuration register to 1 to place the
MAX7500–MAX7504 in shutdown mode and reduce
supply current to 3µA.
Power-Up and Power-Down
The MAX7500–MAX7504 power up to a known state, as
indicated in Table 2. Some of these settings are sum-
marized below:
• Comparator mode
•T
OS = +80°C
•T
HYST = +75°C
• OS active low
• Pointer = 00
Internal Registers
The MAX7500–MAX7504s’ pointer register selects
between four data registers. See Figure 5. At power-up,
the pointer is set to read the temperature register at
address 00. The pointer register latches the last loca-
tion to which it was set. All registers are read and write,
except the temperature register, which is read only.
Write to the configuration register by writing an address
byte, a data pointer byte, and a data byte. If 2 data
bytes are written, the second data byte overrides the
first. If more than 2 data bytes are written, only the first
2 bytes are recognized while the remaining bytes are
ignored. The TOS and THYST registers require 1
address byte and 1 pointer byte and 2 data bytes. If
only 1 data byte is written, it is saved in bits D15–D8 of
the respective register. If more than 2 data bytes are
written, only the first 2 bytes are recognized while the
remaining bytes are ignored.
Read from the MAX7500–MAX7504 in one of two ways.
If the location latched in the pointer register is set from
the previous read, the new read consists of an address
byte, followed by retrieving the corresponding number
of data bytes. If the pointer register needs to be set to a
new address, perform a read operation by writing an
address byte, pointer byte, repeat start, and another
address byte.
An inadvertent 8-bit read from a 16-bit register, with the
D7 bit low, can cause the MAX7500–MAX7504 to stop
in a state where the SDA line is held low. Ordinarily, this
would prevent any further bus communication until the
master sends nine additional clock cycles or SDA goes
high. At that time, a stop condition resets the device.
With the MAX7500/MAX7501/MAX7502, if the additional
clock cycles are not generated by the master, the bus
resets and unlocks after the bus timeout period has
elapsed.
The MAX750–MAX7504 can be reset by pulsing RESET
low.
Bus Timeout
Communication errors sometimes occur due to noise
pickup on the bus. In the worst case, such errors can
cause the slave device to hold the data line low, there-
by preventing other devices from communicating over
the bus. The MAX7500/MAX7501/MAX7502s’ internal
bus timeout circuit resets the bus and releases the data
line if the line is low for more than 250ms. When the bus
timeout is active, the minimum serial clock frequency is
limited to 6Hz.
RESET
The RESET input on the MAX7503/MAX7504 provides a
way to reset the I2C bus and all the internal registers to
their initial POR values. To reset, apply a low pulse with
a duration of at least 1µs to the RESET input.
Digital Temperature Sensors and Thermal
Watchdog with Bus Lockup Protection
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