C165
16-Bit Single-Chip Microcontroller
Never stop thinking.
Microcontrollers
Data Sheet, V2.0, Dec. 2000
Edition 200 0-12
Published by Infineon Technologies AG,
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© Infineon Technologies AG 2000.
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Microcontrollers
Data Sheet, V2.0, Dec. 2000
Never stop thinking.
C165
16-Bit Single-Chip Microcontroller
C165
Revision History: 2000-12 V2.0
Previous Version: 1998-12 Update 0.5µ technology
01.96 3 Volt Addendum
07.95 25 MHz Addendum
09.94 Data Sheet
Page Subjects (major changes since last revision)
All Converted to Infineon layout
2ROM derivatives removed, 25-MHz derivatives and 3 V derivatives
included
6ff Pin numbers for TQFP added
14 Address window arbitration and master/slave mode introduced
32 New standard layout for section “Absolute Maximum Ratings”
33 Section “Operat ing Co nditions” added
34f Parameter “RSTIN pullup” replaced by “RSTIN current”
36f DC Characteristics for reduced supply voltage added
38f Separate specification for power consumption with greatly improved values
40ff Description of clock generation improved
45, 55, 65 Timing adapted to 25 MHz
48, 58, 66 Timing for reduced supply voltage added
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Data Sheet 1 V2.0, 2000-12
C16516-Bit Single-Chip Microcontroller
C166 Family
C165
• High Performance 16-bit CPU with 4-Stage Pipeline
– 80 ns Instruction Cycle Time at 25 MHz CPU Clock
– 400 ns Multiplication (16 × 16 bit), 800 ns Division (32 / 16 bit)
– Enhanced Boolean Bit Manipulation Facilities
– Additional Instructions to Support HLL and Operating Systems
– Register-Based Design with Multiple Variable Register Banks
– Single-Cycle Context Switching Support
– 16 MBytes Total Linear Address Space for Code and Data
– 1024 Bytes On-Chip Special Function Register Area
• 16-Priority-Level Interrupt System with 28 Sources, Sample-Rate down to 40 ns
• 8-Channel Interrupt-Driven Single-Cycle Data Transfer Facilities via
Peripheral Event Controller (PEC)
• Clock Generation via prescaler or via direct clock input
• On-Chip Memory Modules
– 2 KBytes On-Chip Internal RAM (IRAM)
• On-Chip Peripheral Modules
– Two Multi-Functional General Purpose Timer Units with 5 Timers
– Two Serial Channels (Synchronous/Asynchronous and High-Speed-Synchronous)
• Up to 16 MBytes External Address Space for Code and Data
– Programmable External Bus Characteristics for Different Address Ranges
– Multiplexed or Demultiplexed External Address/Data Buses with 8-Bit or 16-Bit
Data Bus Width
– Five Programmable Chip-Select Signals
– Hold- and Hold-Acknowledge Bus Arbitration Support
• Idle and Power Down Modes
• Programmable Watchdog Timer
• Up to 77 General Purpose I/O Lines,
partly with Selectable Input Thresholds and Hysteresis
• Power Supply: the C165 can operate from a 5 V or a 3 V power supply
• Supported by a Large Range of Development Tools like C-Compilers,
Macro-Assembler Packages, Emulators, Evaluation Boards, HLL-Debuggers,
Simulators, Logic Analyzer Disassemblers, Programming Boards
• On-Chip Bootstrap Loader
• 100-Pin MQFP Package (0.65 mm pitch)
• 100-Pin TQFP Package (0.5 mm pitch)
C165
Data Sheet 2 V2.0, 2000-12
This document describes several derivatives of the C165 group. Table 1 enumerates
these derivatives and summarizes the differences. As this document refers to all of these
derivatives, some descriptions may not apply to a specific product.
For simplicity all versions are referred to by the term C165 throughout this document.
Ordering Information
The ordering code for Infineon microcontrollers provides an exact reference to the
required product. This ordering code identifies:
• the derivative itself, i.e. its function set, the temperature range, and the supply voltage
• the package and the type of delivery.
For the available ordering codes for the C165 please refer to the “Product Catalog
Microcontrollers”, which summarizes all available microcontroller variants.
Note: The ordering codes for Mask-ROM versions are defined for each product after
verification of the respective ROM code.
Table 1 C165 Derivative Synopsis
Derivative1)
1) This Data Sheet is valid for dev ic es start ing with and including design st ep H A.
Max. Operating
Frequency Operating
Voltage Package
SAF-C165-LM 20 MHz 4.5 to 5.5 V MQFP-100
SAB-C165-LM 20 MHz 4.5 to 5.5 V MQFP-100
SAF-C165-L25M 25 MHz 4.5 to 5.5 V MQFP-100
SAB-C165-L25M 25 MHz 4.5 to 5.5 V MQFP-100
SAF-C165-LF 20 MHz 4.5 to 5.5 V TQFP-100
SAB-C165-LF 20 MHz 4.5 to 5.5 V TQ FP-100
SAF-C165-L25F 25 MHz 4.5 to 5.5 V TQFP-100
SAB-C165-L25F 25 MHz 4.5 to 5.5 V TQ FP-100
SAF-C165-LM3V 20 MHz 3.0 to 3.6 V MQFP-100
SAB-C165-LM3V 20 MHz 3.0 to 3.6 V MQFP-100
SAF-C165-LF3V 20 MHz 3.0 to 3.6 V TQFP-100
SAB-C165-LF3V 20 MHz 3.0 to 3.6 V TQ FP-100
C165
Data Sheet 3 V2.0, 2000-12
Introduction
The C165 is a deriv ative of the Infineon C1 66 Fami ly o f full fea tured single -chi p CMO S
microco ntrol lers . It co mbin es high CPU perfo rman ce (up to 12 .5 million instruc tions per
second) with peripheral functionality and enhanced IO-capabilities. The C165 is
especially suited for cost sensitive applications.
Figure 1 Logic Symbol
MCL04824
XTAL1
XTAL2
RSTOUT
ALE
NMI
RD
RSTIN
Port 0
16 Bit
16 Bit
Port 1
8 Bit
Port 2
15 Bit
Port 3
8 Bit
Port 4
V
DD SS
V
WR/WRL
Port 5
6 Bit
Port 6
8 Bit
EA
READY
C165
C165
Data Sheet 4 V2.0, 2000-12
Pin Configuration TQFP Package
(top view)
Figure 2
P3.10/TxD0 P1L.0/A0
P4.4/A20 P5.10/T6EUD
P3.9/MTSR
P3.8/MRST
P3.7/T2IN
P3.6/T3IN
P3.5/T4IN
P3.4/T3EUD
P3.3/T3OUT
P3.2/CAPIN
P3.1/T6OUT
P3.0
XTAL2
XTAL1
P5.15/T2EUD
P5.14/T4EUD
P5.13/T5IN
P5.12/T6IN
P5.11/T5EUD
P4.5/A21
P4.6/A22
P4.7/A23
RD
WR/WRL
READY
ALE
EA
V
P0L.0/AD0
P0L.1/AD1
P0L.2/AD2
P0L.3/AD3
P0L.4/AD4
P0L.5/AD5
P0L.6/AD6
P0L.7/AD7
P1L.1/A1
P1L.2/A2
P1L.3/A3
P1L.4/A4
P1L.5/A5
P1L.6/A6
P1L.7/A7
P1H.0/A8
P1H.1/A9
P1H.2/A10
P1H.3/A11
P1H.4/A12
P1H.5/A13
P1H.6/A14
P1H.7/A15
P2.15/EX7IN
P2.14/EX6IN
P2.13/EX5IN
P2.12/EX4IN
P2.11/EX3IN
P2.10/EX2IN
P2.9/EX1IN
P2.8/EX0IN
P6.7/BREQ
P6.6/HLDA
P6.5/HOLD
P6.4/CS4
P6.3/CS3
P6.2/CS2
P6.1/CS1
P6.0/CS0
NMI
RSTOUT
RSTIN
100
181
5031
80
DD
SS
V
51
30
P0H.7/AD15
P0H.6/AD14
P0H.5/AD13
P0H.4/AD12
P0H.3/AD11
P0H.2/AD10
P0H.1/AD9
P0H.0/AD8
P3.11/RxD0
P3.12/BHE/WRH
P3.13/SCLK
P3.15/CLKOUT
P4.0/A16
P4.1/A17
P4.2/A18
P4.3/A19
MCP02216
V
SS
DD
V
V
DD
SS
V
V
DD
SS
V
V
DD
SS
V
V
DD
V
SS
2928
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76777879
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49
828384858687888990919293949596979899
N.C.
C165
C165
Data Sheet 5 V2.0, 2000-12
Pin Configuration MQFP Package
(top view)
Figure 3
P3.10/TxD0 P1L.0/A0
P4.4/A20 P5.10/T6EUD
P3.9/MTSR
P3.8/MRST
P3.7/T2IN
P3.6/T3IN
P3.5/T4IN
P3.4/T3EUD
P3.3/T3OUT
P3.2/CAPIN
P3.1/T6OUT
P3.0
XTAL2
XTAL1
P5.15/T2EUD
P5.14/T4EUD
P5.12/T6IN
P5.11/T5EUD
P4.5/A21
P4.6/A22
P4.7/A23
RD
WR/WRL
READY
ALE
EA
V
P0L.0/AD0
P0L.1/AD1
P0L.2/AD2
P0L.3/AD3
P0L.4/AD4
P0L.5/AD5
P0L.6/AD6
P0L.7/AD7
P1L.1/A1
P1L.2/A2
P1L.3/A3
P1L.4/A4
P1L.5/A5
P1L.6/A6
P1L.7/A7
P1H.0/A8
P1H.1/A9
P1H.2/A10
P1H.3/A11
P1H.4/A12
P1H.5/A13
P1H.6/A14
P1H.7/A15
P2.15/EX7IN
P2.14/EX6IN
P2.13/EX5IN
P2.12/EX4IN
P2.11/EX3IN
P2.10/EX2IN
P2.9/EX1IN
P2.8/EX0IN
P6.7/BREQ
P6.6/HLDA
P6.5/HOLD
P6.4/CS4
P6.3/CS3
P6.2/CS2
P6.1/CS1
P6.0/CS0
NMI
RSTOUT
RSTIN
181
5031
80
DD
SS
V
51
30
P0H.7/AD15
P0H.6/AD14
P0H.5/AD13
P0H.4/AD12
P0H.3/AD11
P0H.2/AD10
P0H.1/AD9
P0H.0/AD8
P3.11/RxD0
P3.12/BHE/WRH
P3.13/SCLK
P3.15/CLKOUT
P4.0/A16
P4.1/A17
P4.2/A18
P4.3/A19
MCP02144
V
SS
DD
V
V
DD
SS
V
V
DD
SS
V
V
DD
SS
V
V
DD
V
SS
P5.13/T5IN
29
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82100
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
4948
47
4645
44
43
4241
403938373635343332
N.C.
C165
C165
Data Sheet 6 V2.0, 2000-12
Table 2 Pin Definitions and Functions
Symbol Pin Nr
TQFP Pin Nr
MQFP Input
Outp. Function
XTAL1
XTAL2
5
6
7
8
I
O
XTAL1: Input to the oscillator amplifier and input
to the internal clock generator
XTAL2: Output of the oscillator amplifier circuit.
To clock the device from an external source, drive
XTAL1, while leaving XTAL2 unconnected.
Minimum and maximum high/low and rise/fall times
specified in the AC Characteristics must be
observed.
P3
P3.0
P3.1
P3.2
P3.3
P3.4
P3.5
P3.6
P3.7
P3.8
P3.9
P3.10
P3.11
P3.12
P3.13
P3.15
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
IO
O
I
O
I
I
I
I
I/O
I/O
O
I/O
O
O
I/O
O
Port 3 is a 15-bit bidirectional I/O port. It is bit-wise
programmable for input or output via direction bits.
For a pin configured as input, the output driver is put
into high-impedance state. Port 3 outputs can be
configured as push/pull or open drain drivers. The
Port 3 pins serve for following alternate functions:
T6OUT GPT2 Timer T6 Toggle Latch Output
CAPIN GPT2 Register CAPREL Capture Input
T3OUT GPT1 Timer T3 Toggle Latch Output
T3EUD GPT1 Timer T3 Ext. Up/Down Ctrl Input
T4IN GPT1 Timer T4
Count/Gate/Reload/Capture Input
T3IN GPT1 Timer T3 Count/Gate Input
T2IN GPT1 Timer T2
Count/Gate/Reload/Capture Input
MRST SSC Master-Receive/Slave-Transmi t
Input/Output
MTSR SSC Master-Transmit/Slave-Receive
Output/Input
TxD0 ASC0 Clock/Data Output (Asyn./Sync.)
RxD0 ASC0 Data Inp. (Asyn.) or In/Out (Sync)
BHE Ext. Memory High Byte Enable Signal,
WRH Ext. Memory High Byte Write Strobe
SCLK SSC Master Cl. Output / Slave Cl. Input
CLKOUT System Clock Output (= CPU Clock)
C165
Data Sheet 7 V2.0, 2000-12
P4
P4.0
P4.1
P4.2
P4.3
P4.4
P4.5
P4.6
P4.7
23
24
25
26
29
30
31
32
25
26
27
28
31
32
33
34
IO
O
O
O
O
O
O
O
O
Port 4 is an 8-bit bidirectional I/O port. It is bit-wise
programmable for input or output via direction bits.
For a pin configured as input, the output driver is put
into high-impedance state. Port 4 can be used to
output the segment address lines:
A16 Least Significant Segment Address Line
A17 Segment Addres s Li ne
A18 Segment Addres s Li ne
A19 Segment Addres s Li ne
A20 Segment Addres s Li ne
A21 Segment Addres s Li ne
A22 Segment Addres s Li ne
A23 Most Significant Segment Address Line
RD 33 35 O External Memory Read Strobe. RD is activated for
every external instruction or data read access.
WR/
WRL 34 36 O External Memory Write Strobe. In WR-mode this pin
is activated for every external data write access. In
WRL-mode this pin is activated for low byte data
write accesses on a 16-bit bus, and for every data
write access on an 8-bit bus. See WRCFG in register
SYSCON for mode selection.
READY 35 37 I Ready Input. When the Ready function is enabled, a
high level at this pin during an external memory
access will force the insertion of memory cycle
waitstates until the pin returns to a low level.
An internal pullup device holds this pin high when
nothing is driving it.
ALE 36 38 O Address Latch Enable Output. Can be used for
latching the address into external memory or an
address latch in the multiplexed bus modes.
EA 37 39 I External Access Enable pin. A low level at this pin
during and after Reset forces the C165 to begin
instruction execution out of external memory. A high
level forces execution out of the internal program
memory.
“ROMless” versions must have this pin tied to ‘0’.
Table 2 Pin Definitions and Functions (cont’d)
Symbol Pin Nr
TQFP Pin Nr
MQFP Input
Outp. Function
C165
Data Sheet 8 V2.0, 2000-12
NC 40 42 – This pin is not connected in the C165.
No connection to the PCB is required.
PORT0
P0L.0-7
P0H.0-7
41-48
51-58
43-50
53-60
IO PORT0 consists of the two 8-bit bidirectional I/O
ports P0L and P0H. It is bit-wise programmable for
input or output via direction bits. For a pin configured
as input, the output driver is put into high-impedance
state. In case of an external bus configuration,
PORT0 serves as the address (A) and address/data
(AD) bus in multiplexed bus modes and as the data
(D) bus in demultiplexed bus modes.
Demultiplexed bus modes:
Data Path Width: 8-bit 16-bit
P0L.0 – P0L.7: D0 – D7 D0 – D7
P0H.0 – P0H.7: I/O D8 – D15
Multiplexed bus modes:
Data Path Width: 8-bit 16-bit
P0L.0 – P0L.7: AD0 – AD7 AD0 – AD7
P0H.0 – P0H.7: A8 – A15 AD8 – AD15
PORT1
P1L.0-7
P1H.0-7
59-66
67,68,
71-76
61-68
69-70,
73-78
IO PORT1 consists of the two 8-bit bidirectional I/O
ports P1L and P1H. It is bit-wise programmable for
input or output via direction bits. For a pin configured
as input, the output driver is put into high-impedance
state. PORT1 is used as the 16-bit address bus (A)
in demultiplexed bus modes and also after switching
from a demultiplexed bus mode to a multiplexed bus
mode.
Table 2 Pin Definitions and Functions (cont’d)
Symbol Pin Nr
TQFP Pin Nr
MQFP Input
Outp. Function
C165
Data Sheet 9 V2.0, 2000-12
RSTIN 79 81 I/O Reset Input with Schmitt-Trigger characteristics. A
low level at this pin while the oscillator is running
resets the C165. An internal pullup resistor permits
power-on reset using only a capacitor connected to
VSS. A spike filter suppresses input pulses < 10 ns.
Input pulses >100 ns safely pass the filter. The
minimum duration for a safe recognition should be
100 ns + 2 CPU clock cycles.
In bidirectional reset mode (enabled by setting bit
BDRSTEN in register SYSCON) the RSTIN line is
internally pulled low for the duration of the internal
reset sequence upon any reset (HW, SW, WDT).
See note below this table.
Note: To let the reset configuration of PORT0 settle
a reset duration of ca. 1 ms is recommended.
RST
OUT 80 82 O Internal Reset Indication Output. This pin is set to a
low level when the part is executing either a
hardware-, a software- or a watchdog timer reset.
RSTOUT remains low until the EINIT (end of
initialization) instruction is executed.
NMI 81 83 I Non-Maskable Interrupt Input. A high to low
transition at this pin causes the CPU to vector to the
NMI trap routine. When the PWRDN (power down)
instruction is executed, the NMI pin must be low in
order to force the C165 to go into power down mode.
If NMI is high, when PWRDN is exec uted, the part
will continue to run in normal mode.
If not used, pin NMI should be pulled high externally.
Table 2 Pin Definitions and Functions (cont’d)
Symbol Pin Nr
TQFP Pin Nr
MQFP Input
Outp. Function
C165
Data Sheet 10 V2.0, 2000-12
P6
P6.0
P6.1
P6.2
P6.3
P6.4
P6.5
P6.6
P6.7
82
83
84
85
86
87
88
89
84
85
86
87
88
89
90
91
IO
O
O
O
O
O
I
I/O
O
Port 6 is an 8-bit bidirectional I/O port. It is bit-wise
programmable for input or output via direction bits.
For a pin configured as input, the output driver is put
into high-impedance state. Port 6 outputs can be
configured as push/pull or open drain drivers.
The Port 6 pins also serve for alternate functions:
CS0 Chip Select 0 Output
CS1 Chip Select 1 Output
CS2 Chip Select 2 Output
CS3 Chip Select 3 Output
CS4 Chip Select 4 Output
HOLD External Master Hold Request Input
HLDA Hold Acknowledge Outp.(master mode)
or Input (slave mode)
BREQ Bus Request Output
P2
P2.8
P2.9
P2.10
P2.11
P2.12
P2.13
P2.14
P2.15
90
91
92
93
94
95
96
97
92
93
94
95
96
97
98
99
IO
I
I
I
I
I
I
I
I
Port 2 is an 8-bit bidirectional I/O port. It is bit-wise
programmable for input or output via direction bits.
For a pin configured as input, the output driver is put
into high-impedance state. Port 2 outputs can be
configured as push/pull or open drain drivers. The
following Port 2 pins serve for alternate functions:
EX0IN Fast External Interrupt 0 Input
EX1IN Fast External Interrupt 1 Input
EX2IN Fast External Interrupt 2 Input
EX3IN Fast External Interrupt 3 Input
EX4IN Fast External Interrupt 4 Input
EX5IN Fast External Interrupt 5 Input
EX6IN Fast External Interrupt 6 Input
EX7IN Fast External Interrupt 7 Input
P5
P5.10
P5.11
P5.12
P5.13
P5.14
P5.15
98
99
100
1
2
3
100
1
2
3
4
5
I
I
I
I
I
I
I
Port 5 is a 6-bit input-only port with Schmitt-Trigger
ch ar. The pi ns of P ort 5 also serv e as timer inpu ts:
T6EUD GPT2 Timer T6 Ext. Up/Down Ctrl Input
T5EUD GPT2 Timer T5 Ext. Up/Down Ctrl Input
T6IN GPT2 Timer T6 Count Input
T5IN GPT2 Timer T5 Count Input
T4EUD GPT1 Timer T4 Ext. Up/Down Ctrl Input
T2EUD GPT1 Timer T2 Ext. Up/Down Ctrl Input
Table 2 Pin Definitions and Functions (cont’d)
Symbol Pin Nr
TQFP Pin Nr
MQFP Input
Outp. Function
C165
Data Sheet 11 V2.0, 2000-12
Note: The following behavioural differences must be observed when the bidirectional
reset is active:
• Bit BDRSTEN in register SYSCON cannot be changed after EINIT and is cleared
automatically after a reset.
• The reset indication flags always indicate a long hardware reset.
• The PORT0 c onfigurati on is tr eated like on a ha rdware res et. Espe ciall y the bo otstra p
loader may be activated when P0L.4 is low.
•Pin RSTIN
may only be connected to external reset devices with an open drain output
driver.
• A short hardware reset is extended to the duration of the internal reset sequence.
VDD 7, 28,
38,
49,
69, 78
9, 30,
40, 51,
71, 80
– Digital Supply Voltage:
+ 5 V or + 3 V during normal operation and idle
mode.
≥ 2.5 V during power down mode.
VSS 4, 27,
39,
50,
70, 77
6, 29,
41, 52,
72, 79
– Digital Ground.
Table 2 Pin Definitions and Functions (cont’d)
Symbol Pin Nr
TQFP Pin Nr
MQFP Input
Outp. Function
C165
Data Sheet 12 V2.0, 2000-12
Functional Description
The architecture of the C165 combines advantages of both RISC and CISC processors
and of advanced peripheral subsystems in a very well-balanced way. In addition the
on-chip memory blocks allow the design of compact systems with maximum
performance.
The following block diagram gives an overview of the different on-chip components and
of the advanced, high bandwidth internal bus structure of the C165.
Note: All time specifications refer to a CPU clock of 25 MHz
(see definition in the AC Characteristics section).
Figure 4 Block Diagram
The program memory, the internal RAM (IRAM) and the set of generic peripherals are
connected to the CPU via separate buses. A fourth bus, the XBUS, connects external
resources as well as additional on-chip resoures, the X-Peripherals (see Figure 4).
C166-Core
CPU
Port 2
Interrupt Bus
XTAL
Osc
WDT
32
16
Interrupt Controller 16-Level
Priority
PEC
External Instr. / Data
GPT
T2
T3
T4
T5
T6
SSC
BRGen
(SPI)
ASC0
BRGen
(USART)
EBC
XBUS Control
External Bus
Control
IRAM
Dual Port
Internal
RAM
2 KByte
ProgMem
Internal
ROM
Area
Data
Data
16
16
16
Instr. / Data
Port 0
Port 6
8
8
Port 1
16 6
16
Port 5Port 3
15
Port 4
8
Peripheral Data Bus
16
On-Chip XBUS (16-Bit Demux)
C165
Data Sheet 13 V2.0, 2000-12
Memory Organization
The memory space of the C165 is configured in a Von Neumann architecture which
means that code memory, data memory, registers and I/O ports are organized within the
same linear address space which includes 16 MBytes. The entire memory space can be
accessed bytewise or wordwise. Particular portions of the on-chip memory have
additionally been made directly bitaddressable.
The C165 is prepared to incorporate on-chip program memory (not in the ROM-less
derivatives, of course) for code or constant data. The internal ROM area can be mapped
either to segment 0 or segment 1.
2 KBytes of on-chip Internal RAM (IRAM) are provided as a storage for user defined
variables, for the system stack, general purpose register banks and even for code. A
register bank can consist of up to 16 wordwide (R0 to R15) and/or bytewide (RL0, RH0,
…, RL7, RH7) so-called General Purpose Registers (GPRs).
1024 byte s (2 ×512 by tes) of the address space are rese rved for the Specia l Func tion
Register area s (SFR space and ESFR space). SFRs are wordwide regist ers which are
used for controlling and monitoring functions of the different on-chip units. Unused SFR
addresses are reserved for future members of the C166 Family.
In order to meet the need s of designs w he re m ore m emo ry is required than is p r ovi ded
on chip, up to 16 MBytes of external RAM and/or ROM can be connected to the
microcontroller.
C165
Data Sheet 14 V2.0, 2000-12
External Bus Controller
All of the external memory accesses are performed by a particular on-chip External Bus
Controller (EBC). It can be programmed either to Single Chip Mode when no external
memory is required, or to one of four different external memory access modes, which are
as follows:
– 16-/18-/20-/24-bit Addresses, 16-bit Data, Demultiplexed
– 16-/18-/20-/24-bit Addresses, 16-bit Data, Multiplexed
– 16-/18-/20-/24-bit Addresses, 8-bit Data, Multiplexed
– 16-/18-/20-/24-bit Addresses, 8-bit Data, Demultiplexed
In the demultiplexed bus modes, addresses are output on PORT1 and data is input/
output on PORT0 or P0L, respectively. In the multiplexed bus modes both addresses
and data use PORT0 for input/output.
Important timing characteristics of the external bus interface (Memory Cycle Time,
Memory Tri-State Time, Length of ALE and Read Write Delay) have been made
programmable to allow the user the adaption of a wide range of different types of
memories and external peripherals.
In addition, up to 4 independent address windows may be defined (via register pairs
ADDRSELx / BUSCONx) which control the access to diff erent resources with different
bus characteristics. These address windows are arranged hierarchically where
BUSCON4 overrides BUSCON3 and BUSCON2 overrides BUSCON1. All accesses to
locations not covered by these 4 address windows are controlled by BUSCON0.
Up to 5 e xte rnal CS signa ls (4 wi ndow s plus default) can be g enera t ed i n orde r to s ave
external glue logic. The C165 offers the possibility to switch the CS outputs to an
unlatched m ode. In this m ode the intern al filter logic is switc hed off and the CS signals
are directly gene ra ted from the address . The u nlatch ed CS mod e is enabled by set ting
CSCFG (SYSCON.6).
Access to v ery sl ow m emories or me morie s wi th va rying a ccess times is sup ported via
a particular ‘Ready’ function.
A HOLD/HLDA protocol is available for bus arbitration and allows to share external
resource s with other bus ma sters. The bus arbitra tion is enabl ed by setting bit HLD EN
in register PSW. After setting HLDEN once, pins P6.7 … P6.5 (BREQ, HLDA, HOLD)
are automati cal ly c on t rolle d b y th e EBC. In Mas ter M ode (default afte r rese t) the H LDA
pin is an outp ut. By s etting bit DP6.7 to ‘1 ’ th e Sla ve Mod e is s elec ted w here pin HLD A
is switched to input. This allows to directly connect the slave controller to another master
controller wi thout glue logic.
For applications which require less than 16 MBytes of external memory space, this
address space can be restricted to 1 MByte, 256 KByte, or to 64 KByte. In this case
Port 4 outputs four, two, or no address lines at all. It outputs all 8 address lines, if an
address space of 16 MBytes is used.
C165
Data Sheet 15 V2.0, 2000-12
Central Processing Unit (CPU)
The mai n core of the CPU cons ists of a 4 -stage i nstructi on pipe line, a 16-b it arithme tic
and logic unit (ALU) and dedicated SFRs. Additional hardware has been spent for a
separate multiply and divide unit, a bit-mask generator and a barrel shifter.
Based on the se hardware prov isions, most of the C165’s ins tructions can b e executed
in just one machine cycle which requires 80 ns at 25 MHz CPU clock. For example, shift
and ro tate ins tructions are al ways proce ssed du ring one m achine c ycle in dep endent of
the number of bits to be shifted. All multiple-cycle instructions have been optimized so
that they can be executed very fast as well: branches in 2 cycles, a 16 ×16 bit
multiplication in 5 cycles and a 32-/16 bit division in 10 cycles. Another pipeline
optimization, the so-called ‘Jump Cache’, allows reducing the execution time of
repeatedly performed jumps in a loop from 2 cycles to 1 cycle.
Figure 5 CPU Block Diagram
MCB02147
CPU
SP
STKOV
STKUN
Instr. Reg.
Instr. Ptr.
Exec. Unit
4-Stage
Pipeline
MDH
MDL
PSW
SYSCON Context Ptr.
Mul/Div-HW
R15
R0
General
Purpose
Registers
Bit-Mask Gen
Barrel - Shifter
ALU (16-bit)
Data Page Ptr. Code Seg. Ptr.
Internal
RAM
R15
R0
ROM
16
16
32
BUSCON 0
BUSCON 1
BUSCON 2
BUSCON 3
BUSCON 4 ADDRSEL 4
ADDRSEL 3
ADDRSEL 2
ADDRSEL 1
C165
Data Sheet 16 V2.0, 2000-12
The CPU has a register context consisting of up to 16 wo rdwide GPRs at its disposal.
These 16 GPRs are physically allocated within the on-chip RAM area. A Context Pointer
(CP) register determines the base address of the active register bank to be accessed by
the CPU at any time. The number of register banks is only restricted by the available
internal RAM space. For easy parameter passing, a register bank may overlap others.
A system stack of up to 1024 words is provided as a storage for temporary data. The
system stack is allocated in the on-chip RAM area, and it is accessed by the CPU via the
stack pointer (SP) register. Two separate SFRs, STKOV and STKUN, are implicitly
compared against the stack pointer value upon each stack access for the detection of a
stack over flow or underflow .
The high performance offered by the hardware implementation of the CPU can efficiently
be utili zed by a programme r via the high ly efficient C165 instru ction set whic h includes
the following instruction classes:
– Arithmetic Instructions
– Logical Instructions
– Boolean Bit Manipulation Instructions
– Compare and Loop Control Instructions
– Shift and Rotate Instructions
– Prioritize Instruction
– Data Movement Instructions
– System Stack Instructions
– Jump and Call Instructions
– Return Instructions
– System Control Instructions
– Miscellaneous Instructions
The basic instruction length is either 2 or 4 bytes. Possible operand types are bits, bytes
and words. A v ariety of direc t, indirect or i mmediat e addressin g modes are pro vided to
specify the required operands.
C165
Data Sheet 17 V2.0, 2000-12
Interrupt System
With an interrupt resp onse time w ithin a ran ge fro m just 5 to 12 CPU cl ocks (in case of
internal program execution), the C165 is capable of reacting very fast to the occurrence
of non-deterministic events.
The architecture of the C165 supports several mechanisms for fast and flexible response
to service requests that can be generated from various sources internal or external to the
microcontroller. Any of these interrupt requests can be programmed to being serviced by
the Interrupt Controller or by the Peripheral Event Controller (PEC).
In contrast to a standard interrupt service where the current program execution is
suspended and a branch to the interrupt vector table is performed, just one cycle is
‘stolen’ from the current CPU activity to perform a PEC service. A PEC service implies a
single byte or word data transfe r between an y two memory loca tions with an add itional
increment of either the PEC source or the destination pointer. An individual PEC transfer
counter is implicity decremented for each PEC service except when performing in the
continuous transfer mode. When this counter reaches zero, a standard interrupt is
performed to the corresponding source related vector location. PEC services are very
well suit ed, for example, for sup porting the transmission or recep tion of blocks of data.
The C165 has 8 PEC channels each of which offers such fast interrupt-driven data
transfer capabilities.
A separate contro l register w hich con tains an interrupt requ est flag, an interrupt ena ble
flag and an interrupt priority bitfield exists for each of the possible interrupt sources. Via
its related regi ster, each sou rce can be progra mmed to one of six teen interrupt pri ority
levels. Once having been accepted by the CPU, an interrupt service can only be
interrupted by a higher prioritized service request. For the standard interrupt processing,
each of the possible interrupt sources has a dedicated vector location.
Fast external interrupt inputs are provided to service external interrupts with high
precision requirements. These fast interrupt inputs feature programmable edge
detection (rising edge, falling edge or both edges).
Software interrupts are supported by means of the ‘TRAP’ instruction in combination with
an individual trap (interrupt) number.
Table 3 shows all of the possible C165 interrupt sources and the corresponding
hardware-related interrupt flags, vectors, vector locations and trap (interrupt) numbers.
Note: Interrupt nodes which are not used by associated peripherals, may be used to
generate software controlled interrupt requests by setting the respective interrupt
request bit (xIR).
C165
Data Sheet 18 V2.0, 2000-12
Table 3 C165 Interrupt Nodes
Source of Interrupt or
PEC Service Request Request
Flag Enable
Flag Interrupt
Vector Vector
Location Trap
Number
External Interrupt 0 CC8IR CC8IE CC8INT 00’0060H18H
External Interrupt 1 CC9IR CC9IE CC9INT 00’0064H19H
External Inte rrupt 2 C C10IR CC10IE CC10INT 00’0068H1AH
External Inte rrupt 3 C C11IR CC11IE CC11INT 00’006CH1BH
External Inte rrupt 4 C C12IR CC12IE CC12INT 00’0070H1CH
External Inte rrupt 5 C C13IR CC13IE CC13INT 00’0074H1DH
External Inte rrupt 6 C C14IR CC14IE CC14INT 00’0078H1EH
External Inte rrupt 7 C C15IR CC15IE CC15INT 00’007CH1FH
GPT1 Timer 2 T2IR T2IE T2INT 00’0088H22H
GPT1 Timer 3 T3IR T3IE T3INT 00’008CH23H
GPT1 Timer 4 T4IR T4IE T4INT 00’0090H24H
GPT2 Timer 5 T5IR T5IE T5INT 00’0094H25H
GPT2 Timer 6 T6IR T6IE T6INT 00’0098H26H
GPT2 CAPREL Reg. CRIR CRIE CRINT 00’009CH27H
ASC0 Transmit S0TIR S0TIE S0TINT 00’00A8H2AH
ASC0 Transmit Buffer S0TBIR S0TBIE S0TBINT 00’011CH47H
ASC0 Receive S0R IR S 0RIE S0RINT 00’00A CH2BH
ASC0 Error S0EIR S0EIE S0EINT 00’00B0H2CH
SSC Transmit SCTIR SCTIE SCTINT 00’00B4H2DH
SSC Receive SCRIR SCRIE SCRINT 00’00B8H2EH
SSC Error SCEIR SCEIE SCEINT 00’00BCH2FH
Unassign ed node XP0IR XP0IE XP0INT 00’0100H40H
Unassign ed node XP1IR XP1IE XP1INT 00’0104H41H
Unassign ed node XP2IR XP2IE XP2INT 00’0108H42H
Unassign ed node XP3IR XP3IE XP3INT 00’010CH43H
Unassi gn ed node CC29IR C C 29 IE CC29INT 00’01 10H44H
Unassi gn ed node CC30IR C C 30 IE CC30INT 00’01 14H45H
Unassi gn ed node CC31IR C C 31 IE CC31INT 00’01 18H46H
C165
Data Sheet 19 V2.0, 2000-12
The C1 65 also provide s an excellen t mechanis m to identify a nd to proces s exceptions
or error conditions that arise during run-time, so-called ‘Hardware Traps’. Hardware
traps cause immediate non-maskable system reaction which is similar to a standard
interrupt service (branching to a dedicated vector table location). The occurence of a
hardware tra p is add itionally signified by a n i ndi vid ual bit i n t he trap fla g regis t er (TFR).
Except when anot her higher prioritized trap service is in progress, a hardware trap will
interrupt any actual program execution. In turn, hardware trap services can normally not
be interrupted by standard or PEC interrupts.
Table 4 shows all of the possible exceptions or error conditions that can arise during run-
time:
Table 4 Hardware Trap Summary
Exception Condition Trap
Flag Trap
Vector Vector
Location Trap
Number Trap
Priority
Reset Functions:
– H ardware Re set
– Software Reset
– W-dog Timer Overflow
–RESET
RESET
RESET
00’0000H
00’0000H
00’0000H
00H
00H
00H
III
III
III
Class A Hardware Traps:
– Non-Maskab le Interru pt
– Stack Overflow
– Stack Underflow
NMI
STKOF
STKUF
NMITRAP
STOTRAP
STUTRAP
00’0008H
00’0010H
00’0018H
02H
04H
06H
II
II
II
Class B Hardware Traps:
– Undefined Opc ode
– Protected Instruction
Fault
– Illegal Word Operand
Access
– Illegal Instruction
Access
– Illegal External Bus
Access
UNDOPC
PRTFLT
ILLOPA
ILLINA
ILLBUS
BTRAP
BTRAP
BTRAP
BTRAP
BTRAP
00’0028H
00’0028H
00’0028H
00’0028H
00’0028H
0AH
0AH
0AH
0AH
0AH
I
I
I
I
I
Reserved – – [2CH –
3CH][0BH –
0FH]–
Software Traps
– TRAP Instruction – – Any
[00’0000H –
00’01FCH]
in steps
of 4H
Any
[00H –
7FH]
Current
CPU
Priority
C165
Data Sheet 20 V2.0, 2000-12
General Purpose Timer (GPT) Unit
The GPT unit represents a very flexible multifunctional timer/counter structure which
may be used for many different time related tasks such as event timing and counting,
pulse width and duty cycle measurements, pulse generation, or pulse multiplication.
The GPT unit incorporates five 16-bit timers which are organized in two separate
modules, GPT1 and G PT2. Eac h time r in eac h mod ule may op erate inde pend ently in a
number of different modes, or may be concatenated with another timer of the same
module.
Each of the three timers T2 , T3, T4 o f module GP T1 c an be c onfigu red i ndivi duall y for
one of four basic modes of operation, which are Timer, Gated Timer, Counter, and
Incremental Interface Mode. In Timer Mode, the input clock for a timer is derived from
the CPU clock, divided by a programmable prescaler, while Counter Mode allows a timer
to be clocked in reference to external events.
Pulse width or duty cycle measurement is supported in Gated Timer Mode, where the
operation of a timer is controlled by the ‘gate’ level on an external input pin. For these
purpose s, each t imer has o ne a ssocia ted p ort pin (TxIN ) whic h serves as gate or clock
input. The maximum resolution of the timers in module GPT1 is 16 TCL.
The count direction (up/down) for each timer is programmable by software or may
additionally be altered dynamically by an external signal on a port pin (TxEUD) to
facilitate e.g. position tracking.
In Increme ntal Interface Mod e the GPT1 timers (T2, T3, T4 ) can be dire ctly connected
to the i ncremental p osition se nsor signal s A and B via their respec tive input s TxIN and
TxEUD. Directi on and cou nt signa ls are internally derived from these two in put signa ls,
so the contents of the respective ti mer Tx co rresp onds to the sensor p osi tion . The third
position sensor signal TOP0 can be connected to an interrupt input.
Timer T3 has an output toggle latch (T3OTL) which changes its state on each timer over-
flow/underflow. The state of this latch may be output on pin T3OUT e.g. for time out
monitoring of ex ternal hardwa re components , or may be used in ternally to clo ck timers
T2 and T4 for measuring long time periods with high resolution.
In addition to their basic operating modes, timers T2 and T4 may be configured as reload
or capture registers for timer T3. When used as capture or reload registers, timers T2
and T4 are stopped. The contents of timer T3 is captured into T2 or T4 in response to a
signal at their associated input pins (TxIN). Timer T3 is reloaded with the contents of T2
or T4 triggered either by an external signal or by a selectable state transition of its toggle
latch T3OTL. When bot h T2 a nd T4 are con figu r ed to alte rnately re loa d T3 on o pposite
state trans itions of T3OT L with the low and hig h tim es of a PWM sign al, th is signa l can
be constantly generated without software intervention.
C165
Data Sheet 21 V2.0, 2000-12
Figure 6 Block Diagram of GPT1
With its maximum resolution of 8 TCL, the GPT2 module provides precise event control
and time measurement. It includes two timers (T5, T6) and a capture/reload register
(CAPREL). Both timers can be clocked with an input clock which is derived from the CPU
clock. The count direction (up/down) for each timer is programmable by software.
Concatenation of the timers is supported via the output toggle latch (T6OTL) of timer T6,
which changes its state on each timer overflow/underflow.
The state of this latch may be used to clock timer T5 and/or it may be output on pin
T6OUT. The overflows/underflows of timer T6 can cause a reload from the CAPREL
register. The CAPREL register may capture the contents of timer T5 based on an
external signal transition on the corresponding port pin (CAPIN), and timer T5 may
optionally be cleared after the capture procedure. This allows the C165 to measure
absolute time differences or to perform pulse multiplication without software overhead.
T3
Mode
Control
2n : 1fCPU
2n : 1fCPU T2
Mode
Control
GPT1 Timer T2
Reload
Capture
2n : 1fCPU
T4
Mode
Control GPT1 Timer T4
Reload
Capture
GPT1 Timer T3 T3OTL
U/D
T2EUD
T2IN
T3IN
T3EUD
T4IN
T4EUD
T3OUT
Toggle FF
U/D
U/D
Interrupt
Request
Interrupt
Request
Interrupt
Request
Other
Timers
MCT02141
n = 3 … 10
C165
Data Sheet 22 V2.0, 2000-12
The capture trigger (timer T5 to CAPREL) may also be generated upon transitions of
GPT1 timer T3’ s inputs T3 IN and/or T3 EUD. This is especiall y advantag eous when T3
operates in Incremental Interface Mode.
Figure 7 Block Diagram of GPT2
MUX
2n : 1fCPU T5
Mode
Control
2n : 1fCPU
T6
Mode
Control
T6OTL
T5EUD
T5IN
T3
CAPIN
T6IN
T6EUD
T6OUT
U/D
U/D
Interrupt
Request
Interrupt
Request
Interrupt
Request
Other
Timers
Clear
Capture
CT3
MCB03999
GPT2 Timer T5
GPT2 CAPREL
GPT2 Timer T6
n = 2 … 9
C165
Data Sheet 23 V2.0, 2000-12
Serial Channels
Serial communication with other microcontrollers, processors, terminals or external
peripheral components is provided by two serial interfaces with different functionality, an
Asynchronous/Synchronous Serial Channel (ASC0) and a High-Speed Synchronous
Serial Channel (SSC).
The ASC0 is upward compatible with the serial ports of the Infineon 8-bit microcontroller
families and supports full-duplex asynchronous communication at up to 781 KBaud and
half-duplex synchronous communication at up to 3.1 MBaud (@ 25 MHz CPU clock).
A dedicated baud rate generator allows to set up all standard baud rates without
oscillator tuning. For transmission, reception and error handling 4 separate interrupt
vectors are provi ded . In asyn chro nou s mode, 8- or 9- bit data f rame s are trans mit ted or
received, preceded by a start bit and terminated by one or two stop bits. For
multiprocessor communication, a mechanism to distinguish address from data bytes has
been included (8-bit data plus wake up bit mode).
In synchronous mode, the ASC0 transmits or receives bytes (8 bits) synchronously to a
shift clock which is generated by the ASC0. The ASC0 always shifts the LSB first. A loop
back option is available for testing purposes.
A number of optional hardware error detection capabilities has been included to increase
the reliability of data transfers. A parity bit can automatically be generated on
transmission or be checked on reception. Framing error detection allows to recognize
data frames with missing stop bits. An overrun error will be generated, if the last
character received has not been read out of the receive buffer register at the time the
reception of a new character is complete.
The SSC supports full-duplex synchronous communication at up to 6.25 MBaud
(@ 25 MHz CPU clock). It may be configured so it interfaces with serially linked
peripheral components. A dedicated baud rate generator allows to set up all standard
baud rates without oscillator tuning. For transmission, reception, and error handling three
separate interrupt vectors are provided.
The SSC transmits or receives characters of 2 … 16 bits length synchronously to a shift
clock which can be generated by the SSC (master mode) or by an external master (slave
mode). The SSC can start shifting with the LSB or with the MSB and allows the selection
of shifting and latching clock edges as well as the clock polarity.
A number of optional hardware error detection capabilities has been included to increase
the reliability of data transfers. Transmit and receive error supervise the correct handling
of the data buffer. Phase and baudrate error detect incorrect serial data.
C165
Data Sheet 24 V2.0, 2000-12
Watchdog Timer
The Watchdog Timer represents one of the fail-safe mechanisms which have been
implemented to prevent the controller from malfunctioning for longer periods of time.
The Watchdog Timer is always enabled after a reset of the chip, and can only be
disabled in the time interval until the EINIT (end of initialization) instruction has been
executed. Thus, the chip’s start-up procedure is always monitored. The software has to
be designed to service the Watchdog Timer before it overflows. If, due to hardware or
software related failures, the software fails to do so, the Watchdog Timer overflows and
generates an internal hardware reset and pulls the RSTOUT pin low in order to allow
external hardware components to be reset.
The Watch dog Timer is a 16-bit timer, cloc ked with th e system cloc k divided by 2/ 128.
The high b yte of the Watchdog Time r register ca n b e s et to a p r esp eci fied rel oad va lue
(stored in WDTREL) in order to allow further variation of the monitored time interval.
Each time it is serviced by the application software, the high byte of the Watchdog Timer
is reloaded. Thus, time intervals between 20 µs and 336 ms can be monitored
(@ 25 MHz).
The default Watchdog Timer interval after reset is 5.24 ms (@ 25 MHz).
Parallel Ports
The C165 provides up to 77 I/O lines which are organized into six input/output ports and
one input port. All port lines are bit-addressable, and all input/output lines are individually
(bit-wise) programmable as inputs or outputs via direction registers. The I/O ports are
true bidirectional ports whi ch are switch ed to high impe danc e state when con figu re d as
inputs. T he output d rivers of thre e I/O ports can be con figured (pin by pin) for pu sh/pull
operation or open-drain operation via control registers. During the internal reset, all port
pins are configured as inputs.
All port lines have programmable alternate input or output functions associated with
them. All port lines that are not used for these alternate functions may be used as general
pu rpos e IO lines .
PORT0 and PORT1 may be used as address and data lines when accessing external
memory, wh ile Port 4 outputs the additiona l segment a ddress bits A23/19/17 … A16 in
systems where segmentation is enabled to access more than 64 KBytes of memory.
Port 6 provides optional chip select signals.
Port 3 includes alternate functions of timers, serial interfaces, the optional bus control
signal BHE/WRH, and the system clock output CLKOUT.
Port 5 is used for timer control signals.
C165
Data Sheet 25 V2.0, 2000-12
Instruction Set Summary
Table 5 lists the instr uctions of the C165 in a condensed way.
The various addressing modes that can be used with a specific instruction, the operation
of the instructions, parameters for conditional execution of instructions, and the opcodes
for each instruction can be found in the “C166 Family Instruction Set Manual”.
This document also provides a detailed description of each instruction.
Table 5 Instruction Set Summary
Mnemonic Description Bytes
ADD(B) Add word (byte) operands 2 / 4
ADDC(B) Add word (byte) operands with Carry 2 / 4
SUB(B) Subtract word (byte) operands 2 / 4
SUBC(B) Subtract word (byte) operands with Carry 2 / 4
MUL(U) (Un)Signed multiply direct GPR by direct GPR (16-16-bit) 2
DIV(U) (Un)Signed divide register MDL by direct GPR (16-/16-bit) 2
DIVL(U) (Un)Signed long divide reg. MD by direct GPR (32-/16-bit) 2
CPL(B) Complement direct word (byte) GPR 2
NEG(B) N egate direct word (byte) GPR 2
AND(B) Bitwise AND, (word/byte operands) 2 / 4
OR(B) Bitwise OR, (word/byte operands) 2 / 4
XOR(B) Bitwise XOR, (word/byte operands) 2 / 4
BCLR Clear direct bit 2
BSET Set direct bit 2
BMOV(N) Move (negated) direct bit to direct bit 4
BAND, BOR,
BXOR AND/OR/XOR direct bit wit h direct bit 4
BCMP Compare direct bit to direct bit 4
BFLDH/L Bitwise modify masked high/low byte of bit-addressable
direct word memory with immediate data 4
CMP(B) Compare word (byte) operands 2 / 4
CMPD1/2 Compare word data to GPR and decrement GPR by 1/2 2 / 4
CMPI1/2 Compare word data to GPR and increment GPR by 1/2 2 / 4
PRIOR Determine number of shift cycles to normalize direct
word GPR and store result in direct word GPR 2
SHL / SHR Shift left/right direct word GPR 2
ROL / ROR Rotate left/right direct word GPR 2
ASHR Arithmetic (sign bit) shift right direct word GPR 2
C165
Data Sheet 26 V2.0, 2000-12
MOV(B) Move word (byte) data 2 / 4
MOVBS Move byte operand to word operand with sign extension 2 / 4
MOVBZ Move byte operand to word operand. with zero extension 2 / 4
JMPA, JMPI,
JMPR Jump absolute/indirect/relative if condition is met 4
JMPS Jump absolute to a code segment 4
J(N)B Jump relative if direct bit is (not) set 4
JBC Jump relative and clear bit if direct bit is set 4
JNBS Jump relative and set bit if direct bit is not set 4
CALLA, CALLI,
CALLR Call absolute/indirect/relative subroutine if condition is met 4
CA LLS Call absolute subroutine in any code segment 4
PCALL Push direct word register onto system stack and call
absolute subroutine 4
TRAP Call interrupt service routine via immediate trap number 2
PUSH, POP Push/pop direct word register onto/from system stack 2
SCXT Push direct word register onto system stack und update
register with word operand 4
RET Return from intra-segment subroutine 2
RETS Return from inter-segment subroutine 2
RETP Return from intra-segment subroutine and pop direct
word register from system stack 2
RETI Return from interrupt service subroutine 2
SRST Software Reset 4
IDLE Enter Idle Mode 4
PWRDN Enter Power Down Mode (supposes NMI-pin being low) 4
SRVWDT Service Watchdog Timer 4
DISWDT Disable Watchdog Timer 4
EINIT Signify End-of-Initialization on RSTOUT-pin 4
ATOMIC Begin ATOMIC sequence 2
EXTR Begin EXTended Register sequence 2
EXTP(R) Begin EXTended Page (and Register) sequence 2 / 4
EXTS(R) Begin EXTended Segment (and Register) sequence 2 / 4
NOP Null operation 2
Table 5 Instruction Set Summary (cont’d)
Mnemonic Description Bytes
C165
Data Sheet 27 V2.0, 2000-12
Special Function Registers Overview
The following table lists all SFRs which are implemented in the C165 in alphabetical
order.
Bit-addressable SFRs are marked with the letter “b” in column “Name”. SFRs within the
Extended SFR-Space (ESFRs) are marked with the letter “E” in column “Physical
Address”. Registers within on-chip X-peripherals are marked with the letter “X” in column
“Physical Address”.
An SFR can be spec ified via its in div idu al mn emonic name . Depending on the s elec ted
addressing mode, an SFR can be accessed via its physical address (using the Data
Page Pointers), or via its short 8-bit address (without using the Data Page Pointers).
Table 6 C165 Registers, Ordered by Name
Name Physical
Address 8-Bit
Addr. Description Reset
Value
ADDRSEL1 FE18H0CHAddress Select Register 1 0000H
ADDRSEL2 FE1AH0DHAddress Select Register 2 0000H
ADDRSEL3 FE1CH0EHAddress Select Register 3 0000H
ADDRSEL4 FE1EH0FHAddress Select Register 4 0000H
BUSCON0 b FF0CH86HBus Configuration Register 0 0XX0H
BUSCON1 b FF14H8AHBus Configuration Register 1 0000H
BUSCON2 b FF16H8BHBus Configuration Register 2 0000H
BUSCON3 b FF18H8CHBus Configuration Register 3 0000H
BUSCON4 b FF1AH8DHBus Configuration Register 4 0000H
CAPREL FE4AH25HGPT2 Capture/Reload Register 0000H
CC10IC b FF8CHC6HEX2IN Interrupt Control Register 0000H
CC11IC b FF8EHC7HEX3IN Interrupt Control Register 0000H
CC12IC b FF90HC8HEX4IN Interrupt Control Register 0000H
CC13IC b FF92HC9HEX5IN Interrupt Control Register 0000H
CC14IC b FF94HCAHEX6IN Interrupt Control Register 0000H
CC15IC b FF96HCBHEX7IN Interrupt Control Register 0000H
CC29IC b F184HEC2HSoftware Interrupt Control Register 0000H
CC30IC b F18CHEC6HSoftware Interrupt Control Register 0000H
CC31IC b F194HECAHSoftware Interrupt Control Register 0000H
CC8IC b FF88HC4HEX0IN Interrupt Control Register 0000H
CC9IC b FF8AHC5HEX1IN Interrupt Control Register 0000H
C165
Data Sheet 28 V2.0, 2000-12
CP FE10H08HCPU Context Pointer Register FC00H
CRIC b FF6AHB5HGPT2 CAPREL Interrupt Ctrl. Reg. 0000H
CSP FE08H04HCPU Code Seg. Pointer Reg. (read only) 0000H
DP0H b F102HE81HP0H Direction Control Register 00H
DP0L b F100HE80HP0L Direction Control Register 00H
DP1H b F106HE83HP1H Direction Control Register 00H
DP1L b F104HE82HP1L Direction Control Register 00H
DP2 b FFC2HE1HPort 2 Direction Control Register 0000H
DP3 b FFC6HE3HPort 3 Direction Control Register 0000H
DP4 b FFCAHE5HPort 4 Direction Control Register 00H
DP6 b FFCEHE7HPort 6 Direction Control Register 00H
DPP0 FE00H00HCPU Data Page Pointer 0 Reg. (10 bits) 0000H
DPP1 FE02H01HCPU Data Page Pointer 1 Reg. (10 bits) 0001H
DPP2 FE04H02HCPU Data Page Pointer 2 Reg. (10 bits) 0002H
DPP3 FE06H03HCPU Data Page Pointer 3 Reg. (10 bits) 0003H
EXICON b F1C0HEE0HExternal Interrupt Control Register 0000H
IDCHIP F07CHE3EHIdentifier 05XXH
IDMANUF F07EHE3FHIdentifier 1820H
IDMEM F07AHE3DHIdentifier 0000H
IDMEM2 F076HE3BHIdentifier 0000H
IDPROG F078HE3CHIdentifier 0000H
MDC b FF0EH87HCPU Multiply Div ide Control Register 0000H
MDH FE0CH06HCPU Multiply Div ide Reg. – High Word 0000H
MDL FE0EH07HCPU Multiply Divide Reg. – Low Word 0000H
ODP2 b F1C2HEE1HPort 2 Open Drain Control Register 0000H
ODP3 b F1C6HEE3HPort 3 Open Drain Control Register 0000H
ODP6 b F1CEHEE7HPort 6 Open Drain Control Register 00H
ONES b FF1EH8FHCons tant Value 1’s Registe r (read only) FFFFH
P0H b FF02H81HPort 0 High Reg. (Upper half of PORT0) 00H
P0L b FF00H80HPort 0 Low Reg. (Lower half of PORT0) 00H
Table 6 C165 Registers, Ordered by Name (cont’d)
Name Physical
Address 8-Bit
Addr. Description Reset
Value
C165
Data Sheet 29 V2.0, 2000-12
P1H b FF06H83HPort 1 High Reg. (Upper half of PORT1) 00H
P1L b FF04H82HPort 1 Low Reg.(Lower hal f of PORT1) 00H
P2 b FFC0HE0HPort 2 Register 0000H
P3 b FFC4HE2HPort 3 Register 0000H
P4 b FFC8HE4HPort 4 Register (8 bits) 00H
P5 b FFA2HD1HPort 5 Register (read only) XXXXH
P6 b FFCCHE6HPort 6 Register (8 bits) 00H
PECC0 FEC0H60HPEC Channel 0 Control Register 0000H
PECC1 FEC2H61HPEC Channel 1 Control Register 0000H
PECC2 FEC4H62HPEC Channel 2 Control Register 0000H
PECC3 FEC6H63HPEC Channel 3 Control Register 0000H
PECC4 FEC8H64HPEC Channel 4 Control Register 0000H
PECC5 FECAH65HPEC Channel 5 Control Register 0000H
PECC6 FECCH66HPEC Channel 6 Control Register 0000H
PECC7 FECEH67HPEC Channel 7 Control Register 0000H
PSW b FF10H88HCPU Program Status Word 0000H
RP0H b F108HE84HSystem Startup Config. Reg. (Rd. only) XXH
S0BG FEB4H5AHSerial Channel 0 Baud Rate Generator
Reload Register 0000H
S0CON b FFB0HD8HSerial Channel 0 Control Register 0000H
S0EIC b FF70HB8HSerial Channel 0 Error Interrupt Ctrl. Reg 0000H
S0RBUF FEB2H59HSerial Channel 0 Receive Buffer Reg.
(read only) XXH
S0RIC b FF6EHB7HSerial Channel 0 Receive Interrupt
Control Register 0000H
S0TBIC b F19CHECEHSerial Channel 0 Transmit Buffer
Interrupt Control Register 0000H
S0TBUF FEB0H58HSerial Channel 0 Transmit Buffer
Register (write only) 00H
S0TIC b FF6CHB6HSerial Channel 0 Transmit Interrupt
Control Register 0000H
Table 6 C165 Registers, Ordered by Name (cont’d)
Name Physical
Address 8-Bit
Addr. Description Reset
Value
C165
Data Sheet 30 V2.0, 2000-12
SP FE12H09HCPU System Stack Pointer Register FC00H
SSCBR F0B4HE5AHSSC Baudrate Registe r 0000H
SSCCON b FFB2HD9HSSC Co ntrol Regis t er 0000 H
SSCEIC b FF76HBBHSSC Error Interrupt Control Register 0000H
SSCRB F0B2HE59HSSC Receive Buffer XXXXH
SSCRIC b FF74HBAHSSC Receive Interrupt Control Register 0000H
SSCTB F0B0HE58HSSC Transmit Buffer 0000H
SSCTIC b FF72HB9HSSC Transmit Interrupt Control Register 0000H
STKOV FE14H0AHCPU Stack Overflo w Pointer Regi ster FA00H
STKUN FE16H0BHCPU Stack Underflo w Pointer Regi ster FC00H
SYSCON b FF12H89HCPU System Configuration Register 1)0XX0H
T2 FE40H20HGPT1 Timer 2 Register 0000H
T2CON b FF40HA0HGPT1 Timer 2 Control Register 0000H
T2IC b FF60HB0HGPT1 Timer 2 Interrupt Control Register 0000H
T3 FE42H21HGPT1 Timer 3 Register 0000H
T3CON b FF42HA1HGPT1 Timer 3 Control Register 0000H
T3IC b FF62HB1HGPT1 Timer 3 Interrupt Control Register 0000H
T4 FE44H22HGPT1 Timer 4 Register 0000H
T4CON b FF44HA2HGPT1 Timer 4 Control Register 0000H
T4IC b FF64HB2HGPT1 Timer 4 Interrupt Control Register 0000H
T5 FE46H23HGPT2 Timer 5 Register 0000H
T5CON b FF46HA3HGPT2 Timer 5 Control Register 0000H
T5IC b FF66HB3HGPT2 Timer 5 Interrupt Control Register 0000H
T6 FE48H24HGPT2 Timer 6 Register 0000H
T6CON b FF48HA4HGPT2 Timer 6 Control Register 0000H
T6IC b FF68HB4HGPT2 Timer 6 Interrupt Control Register 0000H
TFR b FFACHD6HTrap Flag Register 0000H
WDT FEAEH57HWatchdog Timer Register (read only) 0000H
WDTCON b FFAEHD7HWatchdog Timer Control Register 2)00XXH
XP0IC b F186HEC3HSoftware Interrupt Control Register 0000H
Table 6 C165 Registers, Ordered by Name (cont’d)
Name Physical
Address 8-Bit
Addr. Description Reset
Value
C165
Data Sheet 31 V2.0, 2000-12
XP1IC b F18EHEC7HSoftware Interrupt Control Register 0000H
XP2IC b F196HECBHSoftware Interrupt Control Register 0000H
XP3IC b F19EHECFHSoftware Interrupt Control Register 0000H
ZEROS b FF1CH8EHConstant Value 0’s Register (read only) 0000H
1) The system configuration is selected during reset.
2) The reset va lue depends on the indicated reset so urc e.
Table 6 C165 Registers, Ordered by Name (cont’d)
Name Physical
Address 8-Bit
Addr. Description Reset
Value
C165
Data Sheet 32 V2.0, 2000-12
Absolute Maximum Ratings
Note: Stresses above those listed under “Absolute Maximum Ratings” may cause
permanent damage to the device. This is a stress rating only and functional
opera tion o f th e dev ice a t t hese or any ot her con ditions a bove those indica ted in
the operational sections of this specificati on is n ot implied . Exposure to abso lute
maximum rating conditions for extended periods may affect device reliability.
During absolute maximum rating overload conditions (
V
IN
>
V
DD
or
V
IN
<
V
SS
) the
voltage on
V
DD
pins with respect to ground (
V
SS
) must not exceed the values
defined by the absolute maximum ratings.
Table 7 Absolute Maximum Rating Parameters
Parameter Symbol Limit Values Unit Notes
min. max.
Storage temperature TST - 65 150 °C–
Junction temperature TJ- 40 150 °C under bias
Voltage on VDD pins with
respect to ground (VSS)VDD -0.5 6.5 V –
Voltage on any pin with
respect to ground (VSS)VIN -0.5 VDD +0.5 V –
Input current on any pin
during overload condition – - 10 10 mA –
Absolute sum of all input
currents during overlo ad
condition
–– |100|mA–
Power dissipation PDISS –1.5W–
C165
Data Sheet 33 V2.0, 2000-12
Operating Conditions
The following operating conditions must not be exceeded in order to ensure correct
operation of the C165. All parameters specified in the following sections refer to these
operating conditions, unless otherwise noticed.
Table 8 Operating Condition Parameters
Parameter Symbol Limit Values Unit Notes
min. max.
Standard
digital supply voltage
(5 V versions)
VDD 4.5 5.5 V Active mode,
fCPUmax = 25 MHz
2.51)
1) Output v olt ages and output currents will be reduced when VDD leaves the ran ge defined for activ e mo de.
5.5 V PowerDown mode
Reduced
digital supply voltage
(3 V versions)
VDD 3.0 3.6 V Active mode,
fCPUmax = 20 MHz
2.51) 3.6 V PowerDown mode
Digital ground voltage VSS 0 V Reference voltage
Overload current IOV –±5mAPer pin
2)3)
2) Overload conditions occur if the standard operatings conditions are exceeded, i.e. the voltage on any pin
exceeds the specified range (i.e. VOV >VDD + 0.5 V or VOV <VSS – 0.5 V). The absolute sum of input overload
currents on all pins may not exc eed 50 mA. The supp ly volt age must remain w ith in t he s pec if ied limits.
Proper ope ration is not guaran teed if overload c onditions occur on f unctional pins suc h as XTAL1, RD, WR ,
etc.
3) Not 100% t es t ed, guaranteed by des ign and charac te riz at ion.
Absolute sum of overload
currents Σ|IOV|–50mA
3)
External Load
Capacitance CL– 100 pF –
Ambient temperature TA070
°C SAB-C165 …
-40 85 °C SAF-C165 …
- 40 125 °C SAK-C165 …
C165
Data Sheet 34 V2.0, 2000-12
Parameter Interpretation
The parameters listed in the following partly represent the characteristics of the C165
and partly its de mand s on the sy stem . To aid in inte rpreting the parameters rig ht, w hen
evaluating them for a design, they are marked in column “Symbol”:
CC (Controller Characteristics):
The logic of the C165 will provide signals with the respective timing characteristics.
SR (System Requirement):
The external system must provide signals with the respective timing characteristics to
the C165.
DC Characteristics (Standard Supply Voltage Range)
(Operating Conditions appl y)1)
Parameter Symbol Limit Values Unit Test Condition
min. max.
Input low voltage (TTL,
all except XTAL1) VIL SR – 0.5 0.2 VDD
– 0.1 V–
Input low voltage XTAL1 VIL2 SR – 0.5 0.3 VDD V–
Input high voltage (TTL,
all except RSTIN and XTAL1) VIH SR 0.2 VDD
+ 0.9 VDD +
0.5 V–
Input high voltage RSTIN
(when operated as input) VIH1 SR 0.6 VDD VDD +
0.5 V–
Input high voltage XTAL1 VIH2 SR 0.7 VDD VDD +
0.5 V–
Output low voltage
(PORT0, PORT1, Port 4, ALE,
RD, WR, BHE, RSTOUT,
RSTIN2))
VOL CC – 0.45 V IOL = 2.4 mA
Output low voltage
(all other outputs) VOL1 CC – 0.45 V IOL = 1.6 mA
Output high voltage3)
(PORT0, PORT1, Port 4, ALE,
RD, WR, BHE, RSTOUT)
VOH CC 2.4 – V IOH = - 2.4 mA
0.9 VDD –VIOH = - 0.5 mA
Output high voltage3)
(all other outputs) VOH1CC 2.4 – V IOH = - 1.6 mA
0.9 VDD –VIOH = - 0.5 mA
Input leakage current (Port 5) IOZ1 CC – ±200 nA 0 V < VIN < VDD
Input leakage current (all other) IOZ2 CC – ±500 nA 0.45 V < VIN < VDD
RSTIN inactive current4) IRSTH5) –-10µAVIN = VIH1
C165
Data Sheet 35 V2.0, 2000-12
RSTIN active current4) IRSTL6) -100 –µAVIN = VIL
READY/RD/WR inact. current7) IRWH5) –-40
µAVOUT = 2.4 V
READY/RD/WR active current7) IRWL6) -500 – µAVOUT = VOLmax
ALE inactive current7) IALEL5) –40
µAVOUT = VOLmax
ALE active current7) IALEH6) 500 – µAVOUT = 2.4 V
Port 6 inactive current7) IP6H5) –-40
µAVOUT = 2.4 V
Port 6 active current7) IP6L6) -500 – µAVOUT = VOL1max
PORT0 configuration current8) IP0H5) –-10
µAVIN = VIHmin
IP0L6) -100 – µAVIN = VILmax
XTAL1 input current IIL CC – ±20 µA0 V < VIN < VDD
Pin capacitance9)
(digital inputs/outputs) CIO CC – 10 pF f = 1 MHz
TA = 25 °C
1) Keeping signal levels w ithin the leve ls specified in t his table, ensure s operation without overload conditions.
For signal lev els outside thes e sp ec if ic at ions als o ref er to the specific at ion of the overload cur rent IOV.
2) Valid in bidirectional rese t mode only.
3) This specif ication is not valid for out puts which are switche d to open drain mod e. In this case the respec tive
output w ill flo at and t he v olt age results from the ex t ernal circuitry.
4) These parameters desc ribe the RSTIN pul lup, wh ic h equals a resistanc e of ca . 50 to 25 0 kΩ.
5) The max im um current may be drawn while the re sp ec ti ve sig nal line remains in ac tive.
6) The minimum current mu st be drawn in order to driv e th e res pective signal line active.
7) This specif ication is valid durin g Reset and duri ng Hold-mo de or Adapt-mod e. During Hold- mode Port 6 pins
are only affected , if the y are us ed (c onfig ured) fo r CS o utput and the op en d rain fu nction is not e nabled. The
READY-pullup is alway s act iv e, except for Powerdo w n mode.
8) This spe cific at ion is valid during Re se t an d during Adapt-m ode.
9) Not 100% t es t ed, guaranteed by des ign and charac te riz at ion.
DC Characteristics (Standard Supply Voltage Range) (cont’d)
(Operating Conditions appl y)1)
Parameter Symbol Limit Values Unit Test Condition
min. max.
C165
Data Sheet 36 V2.0, 2000-12
DC Characteristics (Reduced Supply Voltage Range)
(Operating Conditions appl y)1)
Parameter Symbol Limit Values Unit Test Condition
min. max.
Input low voltage (TTL,
all except XTAL1) VIL SR - 0.5 0.8 V –
Input low voltage XTAL1 VIL2 SR - 0.5 0.3 VDD V–
Input high voltage (TTL,
all except RSTIN and XTAL1) VIH SR 1.8 VDD +
0.5 V–
Input high voltage RSTIN
(when operated as input) VIH1 SR 0.6 VDD VDD +
0.5 V–
Input high voltage XTAL1 VIH2 SR 0.7 VDD VDD +
0.5 V–
Output low voltage
(PORT0, PORT1, Port 4, ALE,
RD, WR, BHE, RSTOUT,
RSTIN2))
VOL CC – 0.45 V IOL = 1.6 mA
Output low voltage
(all other outputs) VOL1 CC – 0.45 V IOL = 1.0 mA
Output high voltage3)
(PORT0, PORT1, Port 4, ALE,
RD, WR, BHE, RSTOUT)
VOH CC 0.9 VDD –VIOH = - 0.5 mA
Output high voltage3)
(all other outputs) VOH1CC 0.9 VDD –VIOH = - 0.25 mA
Input leakage current (Port 5) IOZ1 CC – ±20 0 nA 0 V < VIN < VDD
Input leakage current (all other) IOZ2 CC – ±500 nA 0.45 V < VIN < VDD
RSTIN inactive current4) IRSTH5) –- 10µAVIN = VIH1
RSTIN active current4) IRSTL6) - 100 – µAVIN = VIL
READY/RD/WR inact. current7) IRWH5) –-10µAVOUT = 2.4 V
READY/RD/WR active current7) IRWL6) - 500 – µAVOUT = VOLmax
ALE inactive current7) IALEL5) –20µAVOUT = VOLmax
ALE active current7) IALEH6) 500 – µAVOUT = 2.4 V
Port 6 inactive current7) IP6H5) –-10µAVOUT = 2.4 V
Port 6 active current7) IP6L6) - 500 – µAVOUT = VOL1max
C165
Data Sheet 37 V2.0, 2000-12
PORT0 configuration current8) IP0H5) –-5
µAVIN = VIHmin
IP0L6) - 100 – µAVIN = VILmax
XTAL1 input current IIL CC – ±20 µA0 V < VIN < VDD
Pin capacitance9)
(digital inputs/outputs) CIO CC – 10 pF f = 1 MHz
TA = 25 °C
1) Keeping signal levels w ithin the leve ls specified in t his table, ensure s operation without overload conditions.
For signal lev els outside thes e sp ec if ic at ions als o ref er to the specific at ion of the overload cur rent IOV.
2) Valid in bidirectional rese t mode only.
3) This specif ication is not valid for out puts which are switche d to open drain mod e. In this case the respec tive
output w ill flo at and t he v olt age results from the ex t ernal circuitry.
4) These parameters desc ribe the RSTIN pul lup, wh ic h equals a resistanc e of ca . 50 to 25 0 kΩ.
5) The max im um current may be drawn while the re sp ec ti ve sig nal line remains in ac tive.
6) The minimum current mu st be drawn in order to driv e th e res pective signal line active.
7) This specif ication is valid durin g Reset and duri ng Hold-mo de or Adapt-mod e. During Hold- mode Port 6 pins
are only affected , if the y are us ed (c onfig ured) fo r CS o utput and the op en d rain fu nction is not e nabled. The
READY-pullup is alway s act iv e, except for Powerdo w n mode.
8) This spe cific at ion is valid during Re se t an d during Adapt-m ode.
9) Not 100% t es t ed, guaranteed by des ign and charac te riz at ion.
DC Characteristics (Reduced Supply Voltage Range) (cont’d)
(Operating Conditions appl y)1)
Parameter Symbol Limit Values Unit Test Condition
min. max.
C165
Data Sheet 38 V2.0, 2000-12
Power Consumption C165 (Standard Supply Voltage Range)
(Operating Conditions appl y)
Parameter Symbol Limit Values Unit Test Condition
min. max.
Power supply current (active)
with all peripherals active IDD5 – 15 +
1.8 × fCPU
mA RSTIN = VIL
fCPU in [MHz]1)
Idle mode supply current
with all peripherals active IIDX5 –2 +
0.4 × fCPU
mA RSTIN = VIH1
fCPU in [MHz]1)
Power-down mod e suppl y
current IPDO5 –50 µAVDD = VDDmax2)
1) The supply c urrent is a function of th e operating frequency. This dependency is illust rat ed in Figure 8.
These parameters are tested at VDDmax and maximum CPU clock with all outputs disconnected and all inputs
at VIL or VIH.
2) This param eter is tested including leakage currents . All inputs (including pins conf igured as inputs) at 0 V to
0.1 V or at VDD – 0.1 V to VDD, all outputs (including pins configured as outputs) disconnected.
Power Consumption C165 (Reduced Supply Voltage Range)
(Operating Conditions appl y)
Parameter Symbol Limit Values Unit Test Condition
min. max.
Power supply current (active)
with all peripherals active IDD3 –3 +
1.3 ×fCPU
mA RSTIN = VIL
fCPU in [MHz]1)
1) The supply c urrent is a function of th e operating frequency. This dependency is illust rat ed in Figure 8.
These parameters are tested at VDDmax and maximum CPU clock with all outputs disconnected and all inputs
at VIL or VIH.
Idle mode supply current
with all peripherals active IIDX3 –1 +
0.4 × fCPU
mA RSTIN = VIH1
fCPU in [MHz]1)
Power-down mod e suppl y
current IPDO3 –30 µAVDD = VDDmax2)
2) This param eter is tested includ ing leakage cur rents. All inputs (includ ing pins confi gured as inputs) at 0 V to
0.1 V or at VDD – 0.1 V to VDD, all outputs (including pins configured as outputs) disconnected.
C165
Data Sheet 39 V2.0, 2000-12
Figure 8 Supply/Idle Current as a Function of Operating Frequency
I [mA]
fCPU [MHz]
10 20 30 40
IDD5max
IDD5typ
IIDX5max
IIDX5typ
20
40
60
80
100
IDD3typ
IIDX3max
IIDX3typ
IDD3max
C165
Data Sheet 40 V2.0, 2000-12
AC Characteristics
Definition of Internal Timing
The internal operation of the C165 is controlled by the internal CPU clock fCPU. Both
edges of the CPU clock can trigger internal (e.g. pip eline) or external (e.g. bus cycles)
operations.
The specification of the external timing (AC Characteristics) therefore depends on the
time between two consecutive edges of the CPU clock, called “TCL” (see Figure 9).
Figure 9 Generation Mechanisms for the CPU Clock
The CPU clock signal fCPU can be generated from the oscillator clock signal fOSC via
different mechanisms. The duration of TCLs and their variation (and also the derived
external timing) depends on the used mechanism to generate fCPU. This influence must
be regarded when calculating the timings for the C165.
The use d mechanism to generate the basic CP U clock is selected by bitfield C LKCFG
in register RP0H.7-5. Upon a long hardware reset register RP0H is loaded with the logic
levels present on the upper half of PORT0 (P0H), i.e. bitfield CLKCFG represents the
logic levels on pins P0.15-13 (P0H.7-5).
Table 9 associates the combinations of these three bits with the respective clock
generation mode.
MCT04826
fOSC
fCPU
Direct Clock Drive
fOSC
fCPU
Prescaler Operation TCL
TCL
TCL
TCL
C165
Data Sheet 41 V2.0, 2000-12
Prescaler Operation
When prescaler operation is configured (CLKCFG = 1XXB) the CPU clock is derived
from the internal oscillator (input clock signal) by a 2:1 prescaler.
The frequency of fCPU is half the frequency of fOSC and the high and low time of fCPU (i.e.
the duration of an individual TCL) is defined by the period of the input clock fOSC.
The timings listed in the AC Characteristics that refer to TCLs therefore can be
calculated using the period of fOSC for any TCL.
Direct Drive
When direct drive is configured (CLKCFG = 0XXB) the on-chip phase locked loop is
disabled and the CPU clock is directly driven from the internal oscillator with the input
clock signal.
The frequency of fCPU directly follows the frequency of fOSC so the high and low time of
fCPU (i.e. the duration of an individual TCL) is defined by the duty cycle of the input clock
fOSC.
The timings listed below that refer to TCLs therefore must be calculated using the
minimum TCL that is possible under the respective circumstances. This minimum value
can be calculated via the following formula:
TCLmin = 1/fOSC × DCmin (DC = duty cycle)
For two consecutive TCLs the deviation caused by the duty cycle of fOSC is compensated
so the d uration of 2TCL i s always 1/ fOSC. The minim um value TCLmin therefo re has to
be used only once for timings that require an odd number of TCLs (1, 3, …). Timings that
require an even number of TCLs (2, 4, …) may use the formula 2TCL = 1/fOSC.
Table 9 C165 Clock Generation Modes
CLKCFG
(P0H.7-5) CPU Frequency
fCPU = fOSC × FExternal Clock
Input Range1)
1) The exte rnal clock input range refers to a CPU c loc k range of 10 … 25 MHz (PLL operation).
Notes
0XX fOSC × 1 1 to 25 MHz Direct drive2)
2) The max im um frequency depends on the duty c ycle of the external clo c k signal.
1XX fOSC / 2 2 to 50 MHz CPU clock via prescaler
C165
Data Sheet 42 V2.0, 2000-12
AC Characteristics
Table 10 External Clock Drive XTAL1 (Standard Supply Voltage Range)
(Operating Conditions apply)
Parameter Symbol Direct Drive
1:1 Prescaler
2:1 Unit
min. max. min. max.
Oscillator period tOSC SR 40 –20–ns
High time1)
1) The cloc k inp ut sig nal m us t r eac h t he defined levels VIL2 and VIH2.
t1SR 202)
2) The min imum high an d low time refers to a duty cycle of 50% . The maximum operating frequen cy (fCPU) in
direct driv e m ode depends on the duty cycle of the c loc k input signal.
–6–ns
Low time1) t2SR 202) –6–ns
Rise ti me 1) t3SR–10–6ns
Fall time1) t4SR–10–6ns
Table 11 External Clock Drive XTAL1 (Reduced Supply Voltage Range)
(Operating Conditions apply)
Parameter Symbol Direct Drive
1:1 Prescaler
2:1 Unit
min. max. min. max.
Oscillator period tOSC SR 50 – 25 – ns
High time1)
1) The cloc k inp ut sig nal m us t r eac h t he defined levels VIL2 and VIH2.
t1SR 252)
2) The min imum high an d low time refers to a duty cycle of 50% . The maximum operating frequen cy (fCPU) in
direct driv e m ode depends on the duty cycle of the c loc k input signal.
–8–ns
Low time1) t2SR 252) –8–ns
Rise ti me 1) t3SR–10–6ns
Fall time1) t4SR–10–6ns
C165
Data Sheet 43 V2.0, 2000-12
Figure 10 External Clock Drive XTAL1
Note: If the on-c hip oscillator is use d toge ther with a crystal, th e oscillator frequenc y is
limited to a range of 4 MHz to 40 MHz.
It is strongly recommended to measure the oscillation allowance (or margin) in the
final target system (layout) to determine the optimum parameters for the oscillator
operation. Please refer to the limits specified by the crystal supplier.
When driven by an external clock signal it will accept the specified frequency
range. Operation at lower input frequencies is possible but is guaranteed by
design only (not 100% tested).
MCT02534
3
t
4
t
V
IH2
V
IL
V
DD
0.5
1
t
2
t
OSC
t
C165
Data Sheet 44 V2.0, 2000-12
Testing Waveforms
Figure 11 Input Output Waveforms
Figure 12 Float Waveforms
MCA04414
2.4 V
0.45 V
1.8 V
0.8 V
1.8 V
0.8 V
Test Points
AC inputs during testing are driven at 2.4 V for a logic 1’ and 0.45 V for a logic 0’.
Timing measurements are made at
IH
V
min for a logic 1’ and
V
IL
max for a logic 0’.
’’’’
MCA00763
- 0.1 V
+ 0.1 V
+ 0.1 V
- 0.1 V
Reference
For timing purposes a port pin is no longer floating when a 100 mV change from load voltage occurs,
but begins to float when a 100 mV change from the loaded
OH
V
Timing
Points
Load
V
V
Load
OH
V
V
OL
/
V
OL
level occurs (
I
OH OL
I
/ = 20 mA).
C165
Data Sheet 45 V2.0, 2000-12
Memory Cycle Variables
The timing tables below use three variables which are derived from the BUSCONx
registers and represent the special characteristics of the programmed memory cycle.
The following table describes, how these variables are to be computed.
Note: Please respect the maximum operating frequency of the respective derivative.
AC Characteristics
Table 12 Memory Cycle Variables
Description Symbol Values
ALE Extension tATCL × <ALECTL>
Memory Cycle Time Waitstates tC2TCL × (15 - <MCTC>)
Memory Tristate Time tF2TCL × (1 - <MTTC>)
Multiplexed Bus (Standard Supply Voltage Range)
(Operating Conditions appl y)
ALE cyc le time = 6 TCL + 2tA + tC + tF (120 ns at 25 MHz CPU clock without waitstates)
Parameter Symbol Max. CPU Clock
= 25 MHz Variable CPU Clock
1 / 2TCL = 1 to 25 MHz Unit
min. max. min. max.
ALE high time t5CC 10 + tA–TCL - 10
+ tA
–ns
Address setup to ALE t6CC 4 + tA–TCL - 16
+ tA
–ns
Address hold after ALE t7CC 10 + tA–TCL - 10
+ tA
–ns
ALE falling edge to RD,
WR (with RW-del ay) t8CC 10 + tA–TCL - 10
+ tA
–ns
ALE falling edge to RD,
WR (no RW-delay) t9CC - 10 + tA– - 10 + tA–ns
Address float after RD,
WR (with RW-del ay) t10 CC–6–6ns
Address float after RD,
WR (no RW-delay) t11 CC – 26 – TCL + 6 ns
RD, WR low time
(with RW-delay) t12 CC 30 + tC– 2TCL - 10
+ tC
–ns
C165
Data Sheet 46 V2.0, 2000-12
RD, WR low time
(no RW-delay) t13 CC 50 + tC– 3TCL - 10
+ tC
–ns
RD to valid data in
(with RW-delay) t14 SR – 20 + tC–2TCL - 20
+ tC
ns
RD to valid data in
(no RW-delay) t15 SR – 40 + tC–3TCL - 20
+ tC
ns
ALE low to valid data in t16 SR – 40 + tA
+ tC
–3TCL - 20
+ tA + tC
ns
Address to valid data in t17 SR – 50 + 2tA
+ tC
–4TCL - 30
+ 2tA + tC
ns
Data hold after RD
rising edge t18 SR0–0–ns
Data float after RD t19 SR – 26 + tF–2TCL - 14
+ tF
ns
Data valid to WR t22 CC 20 + tC– 2TCL - 20
+ tC
–ns
Data hold after WR t23 CC 26 + tF– 2TCL - 14
+ tF
–ns
ALE rising edge after RD,
WR t25 CC 26 + tF– 2TCL - 14
+ tF
–ns
Address hold after RD,
WR t27 CC 26 + tF– 2TCL - 14
+ tF
–ns
ALE falling edge to CS1) t38 CC - 4 - tA10 - tA-4 - tA10 - tAns
CS low to Valid Data In1) t39 SR – 40
+ tC+2tA
–3TCL - 20
+ tC + 2tA
ns
CS hold after RD, WR1) t40 CC 46 + tF– 3TCL - 14
+ tF
–ns
ALE fall. edge to RdCS,
WrCS (with RW delay) t42 CC 16 + tA– TCL - 4
+ tA
–ns
ALE fall. edge to RdCS,
WrCS (no RW delay) t43 CC - 4 + tA–-4
+ tA
–ns
Multiplexed Bus (Standard Supply Voltage Range) (cont’d)
(Operating Conditions appl y)
ALE cyc le time = 6 TCL + 2tA + tC + tF (120 ns at 25 MHz CPU clock without waitstates)
Parameter Symbol Max. CPU Clock
= 25 MHz Variable CPU Clock
1 / 2TCL = 1 to 25 MHz Unit
min. max. min. max.
C165
Data Sheet 47 V2.0, 2000-12
Address float after RdCS,
WrCS (with RW delay) t44 CC –0–0ns
Address float after RdCS,
WrCS (no RW delay) t45 CC – 20 – TCL ns
RdCS to Valid Data In
(with RW delay) t46 SR – 16 + tC–2TCL - 24
+ tC
ns
RdCS to Valid Data In
(no RW delay) t47 SR – 36 + tC–3TCL - 24
+ tC
ns
RdCS, Wr CS Low Time
(with RW delay) t48 CC 30 + tC– 2TCL - 10
+ tC
–ns
RdCS, Wr CS Low Time
(no RW delay) t49 CC 50 + tC– 3TCL - 10
+ tC
–ns
Data valid to WrCS t50 CC 26 + tC– 2TCL - 14
+ tC
–ns
Data hold after RdCS t51 SR0–0–ns
Data float after RdCS t52 SR – 20 + tF–2TCL - 20
+ tF
ns
Address hold after
RdCS, Wr CS t54 CC 20 + tF– 2TCL - 20
+ tF
–ns
Data hold after WrCS t56 CC 20 + tF– 2TCL - 20
+ tF
–ns
1) These parameters refer to the latched chip select signals (CSxL). The early chip select signals (CSxE) are
specifie d to get her with the addre s s an d signal BHE (see figure s below ).
Multiplexed Bus (Standard Supply Voltage Range) (cont’d)
(Operating Conditions appl y)
ALE cyc le time = 6 TCL + 2tA + tC + tF (120 ns at 25 MHz CPU clock without waitstates)
Parameter Symbol Max. CPU Clock
= 25 MHz Variable CPU Clock
1 / 2TCL = 1 to 25 MHz Unit
min. max. min. max.
C165
Data Sheet 48 V2.0, 2000-12
AC Characteristics
Multiplexed Bus (Reduced Supply Voltage Range)
(Operating Conditions appl y)
ALE cyc le time = 6 TCL + 2tA + tC + tF (150 ns at 20 MHz CPU clock without waitstates)
Parameter Symbol Max. CPU Clock
= 20 MHz Variable CPU Clock
1 / 2TCL = 1 to 20 MHz Unit
min. max. min. max.
ALE high time t5CC 11 + tA–TCL - 14
+ tA
–ns
Address setup to ALE t6CC 5 + tA–TCL - 20
+ tA
–ns
Address hold after ALE t7CC 15 + tA–TCL - 10
+ tA
–ns
ALE falling edge to RD,
WR (with RW-del ay) t8CC 15 + tA–TCL - 10
+ tA
–ns
ALE falling edge to RD,
WR (no RW-delay) t9CC - 10 + tA–-10 + tA–ns
Address float after RD,
WR (with RW-del ay) t10 CC–6–6ns
Address float after RD,
WR (no RW-delay) t11 CC – 31 – TCL + 6 ns
RD, WR low time
(with RW-delay) t12 CC 34 + tC– 2TCL - 16
+ tC
–ns
RD, WR low time
(no RW-delay) t13 CC 59 + tC– 3TCL - 16
+tC
–ns
RD to valid data in
(with RW-delay) t14 SR – 22 + tC–2TCL - 28
+ tC
ns
RD to valid data in
(no RW-delay) t15 SR – 47 + tC–3TCL - 28
+ tC
ns
ALE low to valid data in t16 SR – 45 + tA
+ tC
–3TCL - 30
+ tA + tC
ns
Address to valid data in t17 SR – 57 + 2tA
+ tC
–4TCL - 43
+ 2tA + tC
ns
Data hold after RD
rising edge t18 SR0–0–ns
C165
Data Sheet 49 V2.0, 2000-12
Data float after RD t19 SR –36 + tF–2TCL - 14
+ tF
ns
Data valid to WR t22 CC 24 + tC– 2TCL - 26
+ tC
–ns
Data hold after WR t23 CC 36 + tF– 2TCL - 14
+ tF
–ns
ALE rising edge after RD,
WR t25 CC 36 + tF– 2TCL - 14
+ tF
–ns
Address hold after RD,
WR t27 CC 36 + tF– 2TCL - 14
+ tF
–ns
ALE falling edge to CS1) t38 CC - 8 - tA10 - tA- 8 - tA10 - tAns
CS low to Valid Data In1) t39 SR – 47+ tC
+ 2tA
–3TCL - 28
+ tC + 2tA
ns
CS hold after RD, WR1) t40 CC 57 + tF– 3TCL - 18
+ tF
–ns
ALE fall. edge to RdCS,
WrCS (with RW delay) t42 CC 19 + tA– TCL - 6
+ tA
–ns
ALE fall. edge to RdCS,
WrCS (no RW delay) t43 CC - 6 + tA–- 6
+ tA
–ns
Address float after RdCS,
WrCS (with RW delay) t44 CC–0–0ns
Address float after RdCS,
WrCS (no RW delay) t45 CC – 25 – TCL ns
RdCS to Valid Data In
(with RW delay) t46 SR – 20 + tC–2TCL - 30
+ tC
ns
RdCS to Valid Data In
(no RW delay) t47 SR – 45 + tC–3TCL - 30
+ tC
ns
RdCS, Wr CS Low Time
(with RW delay) t48 CC 38 + tC– 2TCL - 12
+ tC
–ns
RdCS, Wr CS Low Time
(no RW delay) t49 CC 63 + tC– 3TCL - 12
+ tC
–ns
Multiplexed Bus (Reduced Supply Voltage Range) (con t’d)
(Operating Conditions appl y)
ALE cyc le time = 6 TC L + 2tA + tC + tF (150 ns at 20 MHz CPU clock without waitstates)
Parameter Symbol Max. CPU Clock
= 20 MHz Variable CPU Clock
1 / 2TCL = 1 to 20 MHz Unit
min. max. min. max.
C165
Data Sheet 50 V2.0, 2000-12
Data valid to WrCS t50 CC 28 + tC– 2TCL - 22
+ tC
–ns
Data hold after RdCS t51 SR0–0–ns
Data float after RdCS t52 SR – 30 + tF–2TCL - 20
+ tF
ns
Address hold after
RdCS, Wr CS t54 CC 30 + tF– 2TCL - 20
+ tF
–ns
Data hold after WrCS t56 CC 30 + tF– 2TCL - 20
+ tF
–ns
1) These parameters refer to the latched chip select signals (CSxL). The early chip select signals (CSxE) are
specifie d to get her with the addre s s an d signal BHE (see figure s below ).
Multiplexed Bus (Reduced Supply Voltage Range) (con t’d)
(Operating Conditions appl y)
ALE cyc le time = 6 TC L + 2tA + tC + tF (150 ns at 20 MHz CPU clock without waitstates)
Parameter Symbol Max. CPU Clock
= 20 MHz Variable CPU Clock
1 / 2TCL = 1 to 20 MHz Unit
min. max. min. max.
C165
Data Sheet 51 V2.0, 2000-12
Figure 13 External Memory Cycle:
Multiplexed Bus, With Read/Write Delay, Normal ALE
A23-A16
(A15-A8)
BHE, CSxE
Data In
Data OutAddress
Address
t38
t44
t10
Address
ALE
CSxL
BUS
Read Cycle
RD
RdCSx
BUS
Write Cycle
WR,
WRL,
WRH
WrCSx
t5t16
t17
t6t7
t39 t40
t25
t27
t18
t19
t14
t46
t12
t48
t10 t22
t23
t44 t12
t48
t8
t42
t42
t8
t50
t51
t54
t52
t56
C165
Data Sheet 52 V2.0, 2000-12
Figure 14 External Memory Cycle:
Multiplexed Bus, With Read/Write Delay, Extended ALE
Data OutAddress
Data InAddress
t38
t4
t10
Address
ALE
CSxL
A23-A16
(A15-A8)
BHE, CSxE
BUS
Read Cycle
RD
RdCSx
BUS
Write Cycle
WR,
WRL,
WRH
WrCSx
t5t16
t17
t6t7
t39 t40
t25
t27
t18
t19
t14
t46
t12
t48
t10 t22
t23
t44 t12
t48
t8
t42
t42
t8
t50
t51
t54
t52
t56
C165
Data Sheet 53 V2.0, 2000-12
Figure 15 External Memory Cycle:
Multiplexed Bus, No Read/Write Delay, Normal ALE
Data OutAddress
Address Data In
t38
Address
ALE
CSxL
A23-A16
(A15-A8)
BHE, CSxE
BUS
Read Cycle
RD
RdCSx
BUS
Write Cycle
WR,
WRL,
WRH
WrCSx
t5t16
t17
t6t7
t39 t40
t25
t27
t18
t19
t15
t47
t13
t49
t22
t23
t13
t49
t9
t43
t43
t9t11
t45
t11
t45 t50
t51
t54
t52
t56
C165
Data Sheet 54 V2.0, 2000-12
Figure 16 External Memory Cycle:
Multiplexed Bus, No Read/Write Delay, Extended ALE
Data OutAddress
Data InAddress
t38
Address
ALE
CSxL
A23-A16
(A15-A8)
BHE, CSxE
BUS
Read Cycle
RD
RdCSx
BUS
Write Cycle
WR,
WRL,
WRH
WrCSx
t5t16
t17
t6t7
t39 t40
t25
t27
t18
t19
t15
t47
t13
t49
t22
t23
t13
t49
t9
t43
t43
t9t11
t45
t11
t45 t50
t51
t54
t52
t56
C165
Data Sheet 55 V2.0, 2000-12
AC Characteristics
Demultiplexed Bus (Standard Supply Voltage Range)
(Operating Conditions appl y)
ALE cycle time = 4 TCL + 2tA + tC + tF (80 ns at 25 MHz CPU clock without waitstates)
Parameter Symbol Max. CPU Clock
= 25 MHz Variable CPU Clock
1 / 2TCL = 1 to 25 MHz Unit
min. max. min. max.
ALE high time t5CC 10 + tA–TCL - 10
+ tA
–ns
Address setup to ALE t6CC 4 + tA–TCL - 16
+ tA
–ns
ALE falling edge to RD,
WR (with RW-del ay) t8CC 10 + tA–TCL - 10
+ tA
–ns
ALE falling edge to RD,
WR (no RW-delay) t9CC - 10 + tA–- 10
+ tA
–ns
RD, WR low time
(with RW-delay) t12 CC 30 + tC–2TCL - 10
+ tC
–ns
RD, WR low time
(no RW-delay) t13 CC 50 + tC–3TCL - 10
+ tC
–ns
RD to valid data in
(with RW-delay) t14 SR – 20 + tC–2TCL - 20
+ tC
ns
RD to valid data in
(no RW-delay) t15 SR – 40 + tC–3TCL - 20
+ tC
ns
ALE low to valid data in t16 SR – 40 +
tA + tC
–3TCL - 20
+ tA + tC
ns
Address to valid data in t17 SR – 50 +
2tA + tC
–4TCL - 30
+ 2tA + tC
ns
Data hold after RD
rising edge t18 SR 0 – 0 – ns
Data float after RD rising
edge (with RW-delay1))t20 SR – 26 +
2tA + tF1) –2TCL - 14
+ 22tA
+ tF1)
ns
Data float after RD rising
edge (no RW-delay1))t21 SR – 10 +
2tA + tF1) –TCL - 10
+ 22tA
+ tF1)
ns
C165
Data Sheet 56 V2.0, 2000-12
Data valid to WR t22 CC 20 + tC–2TCL - 20
+ tC
–ns
Data hold after WR t24 CC 10 + tF–TCL - 10
+ tF
–ns
ALE rising edge after
RD, WR t26 CC - 10 + tF–-10 + tF–ns
Address hold after WR2) t28 CC 0 + tF–0 + tF–ns
ALE falling edge to CS3) t38 CC - 4 - tA10 - tA-4 - tA10 - tAns
CS low to Valid Data In3) t39 SR – 40 +
tC + 2tA
–3TCL - 20
+ tC + 2tA
ns
CS hold after RD, WR3) t41 CC 6 + tF–TCL - 14
+ tF
–ns
ALE falling edge to
RdCS, Wr CS (with RW-
delay)
t42 CC 16 + tA–TCL - 4
+ tA
–ns
ALE falling edge to
RdCS, Wr CS (no RW-
delay)
t43 CC - 4 + tA–-4
+ tA
–ns
RdCS to Valid Data In
(with RW-delay) t46 SR – 16 + tC–2TCL - 24
+ tC
ns
RdCS to Valid Data In
(no RW-delay) t47 SR – 36 + tC–3TCL
- 24
+ tC
ns
RdCS, Wr CS Low Time
(with RW-delay) t48 CC 30 + tC–2TCL - 10
+ tC
–ns
RdCS, Wr CS Low Time
(no RW-delay) t49 CC 50 + tC–3TCL - 10
+ tC
–ns
Data valid to WrCS t50 CC 26 + tC–2TCL - 14
+ tC
–ns
Data hold after RdCS t51 SR 0 – 0 – ns
Demultiplexed Bus (Standard Supply Voltage Range) (cont’d)
(Operating Conditions appl y)
ALE cycle time = 4 TCL + 2tA + tC + tF (80 ns at 25 MHz CPU clock without waitstates)
Parameter Symbol Max. CPU Clock
= 25 MHz Variable CPU Clock
1 / 2TCL = 1 to 25 MHz Unit
min. max. min. max.
C165
Data Sheet 57 V2.0, 2000-12
Data float after RdCS
(with RW-delay)1) t53 SR – 20 + tF–2TCL - 20
+ 2tA + tF
1)
ns
Data float after RdCS
(no RW-delay)1) t68 SR – 0 + tF–TCL - 20
+ 2tA + tF
1)
ns
Address hold after
RdCS, Wr CS t55 CC - 6 + tF–-6 + tF–ns
Data hold after WrCS t57 CC 6 + tF–TCL - 14
+ tF
–ns
1) RW-delay and tA refer to the next following bus cycle (in c luding an access to an on-c hip X-Peripheral).
2) Read data are latched with the same clock edge that triggers the address change and the rising RD edge.
Therefore address cha nges before the end of RD have no impact on read cycles.
3) These parameters refer to the latched chip select signals (CSxL). The early chip select signals (CSxE) are
specifie d to get her with the addre s s an d signal BHE (see figure s below ).
Demultiplexed Bus (Standard Supply Voltage Range) (cont’d)
(Operating Conditions appl y)
ALE cycle time = 4 TCL + 2tA + tC + tF (80 ns at 25 MHz CPU clock without waitstates)
Parameter Symbol Max. CPU Clock
= 25 MHz Variable CPU Clock
1 / 2TCL = 1 to 25 MHz Unit
min. max. min. max.
C165
Data Sheet 58 V2.0, 2000-12
AC Characteristics
Demultiplexed Bus (Reduced Supply Voltage Range)
(Operating Conditions appl y)
ALE cycle time = 4 TCL + 2tA + tC + tF (100 ns at 20 MHz CPU clock without waitstates)
Parameter Symbol Max. CPU Clock
= 20 MHz Variable CPU Clock
1 / 2TCL = 1 to 20 MHz Unit
min. max. min. max.
ALE high time t5CC 11 + tA–TCL - 14
+ tA
–ns
Address setup to ALE t6CC 5 + tA–TCL - 20
+ tA
–ns
ALE falling edge to RD,
WR (with RW-del ay) t8CC 15 + tA–TCL - 10
+ tA
–ns
ALE falling edge to RD,
WR (no RW-delay) t9CC - 10 + tA–- 10
+ tA
–ns
RD, WR low time
(with RW-delay) t12 CC 34 + tC–2TCL - 16
+ tC
–ns
RD, WR low time
(no RW-delay) t13 CC 59 + tC–3TCL - 16
+ tC
–ns
RD to valid data in
(with RW-delay) t14 SR – 22 + tC–2TCL - 28
+ tC
ns
RD to valid data in
(no RW-delay) t15 SR – 47 + tC–3TCL - 28
+ tC
ns
ALE low to valid data in t16 SR – 45 +
tA + tC
–3TCL - 30
+ tA + tC
ns
Address to valid data in t17 SR – 57 +
2tA + tC
–4TCL - 43
+ 2tA + tC
ns
Data hold after RD
rising edge t18 SR 0 – 0 – ns
Data float after RD rising
edge (with RW-delay1))t20 SR – 36 +
2tA + tF1) –2TCL - 14
+ 22tA
+ tF1)
ns
Data float after RD rising
edge (no RW-delay1))t21 SR – 15 +
2tA + tF1) –TCL - 10
+ 22tA
+ tF1)
ns
C165
Data Sheet 59 V2.0, 2000-12
Data valid to WR t22 CC 24 + tC–2TCL - 26
+ tC
–ns
Data hold after WR t24 CC 15 + tF–TCL - 10
+ tF
–ns
ALE rising edge after
RD, WR t26 CC - 12 + tF–-12 + tF–ns
Address hold after WR2) t28 CC 0 + tF–0 + tF–ns
ALE falling edge to CS3) t38 CC - 8 - tA10 - tA-8 - tA10 - tAns
CS low to Valid Data In3) t39 SR – 47 +
tC + 2tA
–3TCL - 28
+ tC + 2tA
ns
CS hold after RD, WR3) t41 CC 9 + tF–TCL - 16
+ tF
–ns
ALE falling edge to
RdCS, Wr CS (with RW-
delay)
t42 CC 19 + tA–TCL - 6
+ tA
–ns
ALE falling edge to
RdCS, Wr CS (no RW-
delay)
t43 CC - 6 + tA–-6
+ tA
–ns
RdCS to Valid Data In
(with RW-delay) t46 SR – 20 + tC–2TCL - 30
+ tC
ns
RdCS to Valid Data In
(no RW-delay) t47 SR – 45 + tC–3TCL
- 30
+ tC
ns
RdCS, Wr CS Low Time
(with RW-delay) t48 CC 38 + tC–2TCL - 12
+ tC
–ns
RdCS, Wr CS Low Time
(no RW-delay) t49 CC 63 + tC–3TCL - 12
+ tC
–ns
Data valid to WrCS t50 CC 28 + tC–2TCL - 22
+ tC
–ns
Data hold after RdCS t51 SR 0 – 0 – ns
Demultiplexed Bus (Reduced Supply Voltage Range) (cont’d)
(Operating Conditions appl y)
ALE cycle time = 4 TCL + 2tA + tC + tF (100 ns at 20 MHz CPU clock without waitstates)
Parameter Symbol Max. CPU Clock
= 20 MHz Variable CPU Clock
1 / 2TCL = 1 to 20 MHz Unit
min. max. min. max.
C165
Data Sheet 60 V2.0, 2000-12
Data float after RdCS
(with RW-delay)1) t53 SR – 30 + tF–2TCL - 20
+ 2tA + tF
1)
ns
Data float after RdCS
(no RW-delay)1) t68 SR – 5 + tF–TCL - 20
+ 2tA + tF
1)
ns
Address hold after
RdCS, Wr CS t55 CC - 16 + tF–- 16 + tF–ns
Data hold after WrCS t57 CC 9 + tF–TCL - 16
+ tF
–ns
1) RW-delay and tA refer to the next follow ing bus cycle (including an access t o an on-chip X-Perip heral).
2) Read data are latched with the same clock edge that triggers the address change and the rising RD edge.
Therefore address cha nges before the end of RD have no impact on read cycles.
3) These parameters refer to the latched chip select signals (CSxL). The early chip select signals (CSxE) are
specifie d to get her with the addre s s an d signal BHE (see figure s below ).
Demultiplexed Bus (Reduced Supply Voltage Range) (cont’d)
(Operating Conditions appl y)
ALE cycle time = 4 TCL + 2tA + tC + tF (100 ns at 20 MHz CPU clock without waitstates)
Parameter Symbol Max. CPU Clock
= 20 MHz Variable CPU Clock
1 / 2TCL = 1 to 20 MHz Unit
min. max. min. max.
C165
Data Sheet 61 V2.0, 2000-12
Figure 17 External Memory Cycle:
Demultiplexed Bus, With Read/Write Delay, Normal ALE
Data Out
Data In
t38
Address
ALE
CSxL
A23-A16
A15-A0
BHE, CSxE
BUS
(D15-D8)
D7-D0
Read Cycle
RD
RdCSx
Write Cycle
WrCSx
t5t16
t17
t6
t39 t41
t26
t28
t18
t20
t14
t46
t12
t48
t22
t24
t12
t48
t8
t42
t42
t8
t50
t51
t55
t53
t57
BUS
(D15-D8)
D7-D0
WR,
WRL,
WRH
C165
Data Sheet 62 V2.0, 2000-12
Figure 18 External Memory Cycle:
Demultiplexed Bus, With Read/Write Delay, Extended ALE
Data Out
Data In
t38
Address
ALE
CSxL
A23-A16
A15-A0
BHE,
CSxE
Read Cycle
RD
RdCSx
Write Cycle
WrCSx
t5t16
t17
t6
t39 t41
t26
t28
t18
t20
t14
t46
t12
t48
t22
t24
t12
t48
t8
t42
t42
t8
t50
t51
t55
t53
t57
BUS
(D15-D8)
D7-D0
BUS
(D15-D8)
D7-D0
WR,
WRL,
WRH
C165
Data Sheet 63 V2.0, 2000-12
Figure 19 External Memory Cycle:
Demultiplexed Bus, No Read/Write Delay, Normal ALE
Data Out
Data In
t38
Address
ALE
CSxL
A23-A16
A15-A0
BHE, CSxE
Read Cycle
RD
RdCSx
Write Cycle
WrCSx
t5t16
t17
t6
t39 t41
t26
t28
t18
t21
t15
t47
t13
t49
t22
t24
t13
t49
t9
t43
t43
t9
t50
t51
t55
t68
t57
BUS
(D15-D8)
D7-D0
BUS
(D15-D8)
D7-D0
WR,
WRL,WRH
C165
Data Sheet 64 V2.0, 2000-12
Figure 20 External Memory Cycle:
Demultiplexed Bus, No Read/Write Delay, Extended ALE
Data Out
Data In
t38
Address
ALE
CSxL
A23-A16
A15-A0
BHE,CSxE
Read Cycle
RD
RdCSx
Write Cycle
WR,
WRL, WRH
WrCSx
t5t16
t17
t6
t39 t41
t26
t28
t18
t21
t15
t47
t13
t49
t22
t24
t13
t49
t9
t43
t43
t9
t50
t51
t55
t68
t57
BUS
(D15-D8)
D7-D0
BUS
(D15-D8)
D7-D0
C165
Data Sheet 65 V2.0, 2000-12
AC Characteristics
CLKOU T and READY (Standard Supply Voltage)
(Operating Conditions appl y)
Parameter Symbol Max. CPU Clock
= 25 MHz Variable CPU Clock
1 / 2TCL = 1 to 25 MHz Unit
min. max. min. max.
CLKOUT cycle time t29 CC 40 40 2TCL 2TCL ns
CLKOUT high time t30 CC 14 –TCL - 6– ns
CLKOUT low time t31 CC 10 – TCL - 10 – ns
CLKOUT rise time t32 CC–4–4ns
CLKOUT fall time t33 CC–4–4ns
CLKOUT rising edge to
ALE falling edge t34 CC 0 + tA10 + tA0 + tA10 + tAns
Synchronous READY
setup time to CLKOUT t35 SR 14 – 14 – ns
Synchronous READY
hold time after CLKOUT t36 SR4–4–ns
Asynchronous READY
low time t37 SR 54 – 2TCL + t58 –ns
Asynchronous READY
setup time1)
1) These timings are given fo r test purposes only, in order to assure recognition at a specif ic clock edge.
t58 SR 14 – 14 – ns
Asynchronous READY
hold time1) t59 SR4–4–ns
Async. READY hold time
after RD, WR high
(Demultiplexed Bus)2)
2) Demultiplexed bus is the worst case. For multiplexed bus 2TCL are to be added to the maximum values. This
adds even more time for deactivating READY.
The 2tA and tC refer to the ne xt fo llow ing bus cycle, tF refers to the current bus cycle.
The max im um limit for t60 must be fulfilled if the next following bus cycle is READY controlled.
t60 SR 0 0
+ 2tA +
tC
+ tF2)
0TCL - 20
+ 2tA + tC
+ tF2)
ns
C165
Data Sheet 66 V2.0, 2000-12
AC Characteristics
CLKOU T and READY (Reduced Supply Voltage)
(Operating Conditions appl y)
Parameter Symbol Max. CPU Clock
= 20 MHz Variable CPU Clock
1 / 2TCL = 1 to 20 MHz Unit
min. max. min. max.
CLKOUT cycle time t29 CC 50 50 2TCL 2TCL ns
CLKOUT high time t30 CC 15 – TCL - 10 – ns
CLKOUT low time t31 CC 13 – TCL - 12 – ns
CLKOUT rise time t32 CC – 12 – 12 ns
CLKOUT fall time t33 CC–8–8ns
CLKOUT rising edge to
ALE falling edge t34 CC 0 + tA8 + tA0 + tA8 + tAns
Synchronous READY
setup time to CLKOUT t35 SR 18 – 18 – ns
Synchronous READY
hold time after CLKOUT t36 SR4–4–ns
Asynchronous READY
low time t37 SR 68 – 2TCL + t58 –ns
Asynchronous READY
setup time1)
1) These timings are given fo r test purposes only, in order to assure recognition at a specif ic clock edge.
t58 SR 18 – 18 – ns
Asynchronous READY
hold time1) t59 SR4–4–ns
Async. READY hold time
after RD, WR high
(Demultiplexed Bus)2)
2) Demultiplexed bus is the worst case. For multiplexed bus 2TCL are to be added to the maximum values. This
adds even more time for deactivating READY.
The 2tA and tC refer to the nex t following bus cycle , tF refers to the current bus cycle.
The max im um limit for t60 must be fulfilled if the next following bus cycle is READY controlled.
t60 SR 0 0
+ 2tA +
tC
+ tF2)
0TCL – 25
+ 2tA + tC
+ tF2)
ns
C165
Data Sheet 67 V2.0, 2000-12
Figure 21 CLKOUT and READY
Notes
1) Cycle as programmed, including MCTC waitstates (Example shows 0 MCTC WS).
2) The lead ing edge of the respe ctiv e c om mand depends on RW-dela y.
3) READY s am pled HIGH at this sa mp ling point generates a READY cont rolled waitstate ,
READY s am pled LOW at this sam pling point term inates the current ly running bus cycle.
4) READY may be deactivated in response to the trailing (rising) edge of the corresponding command (RD or
WR).
5) If the Asynchronous READY signal does not fulfill the indicated setup and hold times with respect to CLKOUT
(e.g. because CLKOUT is not enabled), it must fulfill t37 in order to be safely synchronized. This is guaranteed,
if READY is removed in response to the command (see Note 4)).
6) Multiplexed bus modes have a MUX waitstate added after a bus cycle, and an additional MTTC waitstate may
be inserted here.
For a multiplexed bus with MTTC waitstate this delay is 2 CLKOUT cycles, for a demultiplexed bus without
MTTC waitstate this delay is zero.
7) The next external bus cycl e ma y start here.
MCT04447
t32
CLKOUT
ALE
Command
RD, WR
Sync
READY
Async
READY
t33
t29
t30
t31
t34
7)
2)
3)
3)
t35
t36 t35
t36
t58
t59
3)
t58
t59
3)
t37 5)
t60 4)
see 6)
Running Cycle 1) READY
Waitstate MUX/Tristate 6)
C165
Data Sheet 68 V2.0, 2000-12
AC Characteristics
External Bus Arbitration (Standard Supply Voltage)
(Operating Conditions appl y)
Parameter Symbol Max. CPU Clock
= 25 MHz Variable CPU Clock
1 / 2TCL = 1 to 25 MHz Unit
min. max. min. max.
HOLD input setup time
to CLKOUT t61 SR 20 –20 – ns
CLKOUT to HLDA high
or BREQ low delay t62 CC – 20 – 20 ns
CLKOUT to HLDA low
or BREQ high delay t63 CC – 20 – 20 ns
CSx release t64 CC – 20 – 20 ns
CSx drive t65 CC - 4 24 - 4 24 ns
Other signals release t66 CC – 20 – 20 ns
Other signals driv e t67 CC - 4 24 - 4 24 ns
External Bus Arbitration (Reduced Supply Voltage)
(Operating Conditions appl y)
Parameter Symbol Max. CPU Clock
= 20 MHz Variable CPU Clock
1 / 2TCL = 1 to 20 MHz Unit
min. max. min. max.
HOLD input setup time
to CLKOUT t61 SR 30 – 30 – ns
CLKOUT to HLDA high
or BREQ low delay t62 CC – 20 – 20 ns
CLKOUT to HLDA low
or BREQ high delay t63 CC – 20 – 20 ns
CSx release t64 CC – 20 – 20 ns
CSx drive t65 CC - 4 3 0 - 4 30 ns
Other signals release t66 CC – 20 – 20 ns
Other signals driv e t67 CC - 4 30 - 4 30 ns
C165
Data Sheet 69 V2.0, 2000-12
Figure 22 External Bus Arbitration, Releasing the Bus
Notes
1) The C165 will complete the currently run ning bus cycle before granting bus access.
2) This is the fir st pos s ibility for BREQ to get active.
3) The CS outputs will be resistive high (pullup) after t64.
MCT04448
t61
t62
CLKOUT
HOLD
HLDA
BREQ
CSx
(On P6.x)
Other
Signals
t63
t64
t66
see1)
3)
1)
2)
C165
Data Sheet 70 V2.0, 2000-12
Figure 23 External Bus Arbitration, (Regaining the Bus)
Notes
1) This is the las t chance for BREQ to trigg er th e indicated regain-s equence.
Even if BREQ is ac tivated earlier, the r egain-sequen ce is initiated by HOLD goin g high.
Please note that HOLD may also be deactivated without the C165 requesting the bus.
2) The next C1 65 driv en bus cycle may s ta rt he re.
MCT04449
t61
t62
t62 t62 t63
t65
t67
CLKOUT
HOLD
HLDA
BREQ
CSx
(On P6.x)
Other
Signals
2)
1)
C165
Data Sheet 71 V2.0, 2000-12
Package Outlines
P-MQFP-100 (SMD)
(Plastic Metric Quad Flat Package)
GPR05365
Sorts of Packing
Package outlines for tubes, trays etc. are contained in our
Data Book “Package Information”. Dimensions in mm
SMD = Surface Mounted Device
C165
Data Sheet 72 V2.0, 2000-12
P-TQFP-100 (SMD)
(Plastic Thin Metric Quad Flat Package)
GPP05614
Sorts of Packing
Package outlines for tubes, trays etc. are contained in our
Data Book “Package Information”. Dimensions in mm
SMD = Surface Mounted Device
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