SiHD9N60E www.vishay.com Vishay Siliconix E Series Power MOSFET FEATURES * Low figure-of-merit (FOM) Ron x Qg D * Low input capacitance (Ciss) DPAK (TO-252) * Reduced switching and conduction losses * Ultra low gate charge (Qg) D G G * Avalanche energy rated (UIS) * Material categorization: for definitions of compliance please see www.vishay.com/doc?99912 S S APPLICATIONS N-Channel MOSFET * Server and telecom power supplies * Switch mode power supplies (SMPS) PRODUCT SUMMARY VDS (V) at TJ max. RDS(on) typ. () at 25 C * Power factor correction power supplies (PFC) 650 VGS = 10 V * Lighting 0.320 Qg max. (nC) 52 - High-intensity discharge (HID) Qgs (nC) 6 - Fluorescent ballast lighting Qgd (nC) 13 Configuration * Industrial Single - Welding - Induction heating - Motor drives - Battery chargers - Renewable energy - Solar (PV inverters) ORDERING INFORMATION Package DPAK (TO-252) Lead (Pb)-free and halogen-free SiHD9N60E-GE3 ABSOLUTE MAXIMUM RATINGS (TC = 25 C, unless otherwise noted) PARAMETER SYMBOL LIMIT Drain-source voltage VDS 600 Gate-source voltage VGS 30 Continuous drain current (TJ = 150 C) VGS at 10 V TC = 25 C TC = 100 C Pulsed drain current a ID IDM Linear derating factor UNIT V 9 6 A 22 0.63 W/C Single pulse avalanche energy b EAS 111 mJ Maximum power dissipation PD 78 W TJ, Tstg -55 to +150 C Operating junction and storage temperature range Drain-source voltage slope TJ = 125 C Reverse diode dV/dt d Soldering recommendations (peak temperature) c For 10 s dV/dt 70 40 300 V/ns C Notes a. Repetitive rating; pulse width limited by maximum junction temperature. b. VDD = 140 V, starting TJ = 25 C, L = 28.2 mH, Rg = 25 , IAS = 2.8 A. c. 1.6 mm from case. d. ISD ID, dI/dt = 100 A/s, starting TJ = 25 C. S17-0286-Rev. A, 27-Feb-17 Document Number: 91967 1 For technical questions, contact: hvm@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 SiHD9N60E www.vishay.com Vishay Siliconix THERMAL RESISTANCE RATINGS PARAMETER SYMBOL TYP. MAX. Maximum Junction-to-Ambient RthJA - 62 Maximum Junction-to-Case (Drain) RthJC - 1.6 UNIT C/W SPECIFICATIONS (TJ = 25 C, unless otherwise noted) PARAMETER SYMBOL TEST CONDITIONS MIN. TYP. MAX. UNIT Static Drain-source breakdown voltage VDS temperature coefficient Gate-source threshold voltage (N) Gate-source leakage Zero gate voltage drain current VDS VGS = 0 V, ID = 250 A 600 - - V VDS/TJ Reference to 25 C, ID = 1 mA - 0.71 - V/C VGS(th) VDS = VGS, ID = 250 A 2.5 - 4.5 V VGS = 20 V - - 100 nA VGS = 30 V - - 1 A VDS = 600 V, VGS = 0 V - - 1 VDS = 480 V, VGS = 0 V, TJ = 125 C - - 10 IGSS IDSS A - 0.320 0.368 gfs VDS = 30 V, ID = 4.5 A - 2.4 - S Input capacitance Ciss VGS = 0 V, VDS = 100 V, f = 1 MHz - 778 - - 48 - - 4 - - 29 - - 138 - - 26 52 - 6 - - 13 - Drain-source on-state resistance Forward Transconductance RDS(on) VGS = 10 V ID = 4.5 A Dynamic Output capacitance Coss Reverse transfer capacitance Crss Effective output capacitance, energy related a Co(er) Effective output capacitance, time related b Co(tr) pF VDS = 0 V to 480 V, VGS = 0 V Total gate charge Qg Gate-source charge Qgs Gate-drain charge Qgd Turn-on delay time td(on) Rise time Turn-off delay time tr td(off) Fall time tf Gate input resistance Rg VGS = 10 V ID = 4.5 A, VDS = 480 V - 14 28 VDD = 480 V, ID = 4.5 A, VGS = 10 V, Rg = 9.1 - 13 26 - 31 62 - 12 24 f = 1 MHz, open drain 0.4 1.2 2.4 - - 9 nC ns Drain-Source Body Diode Characteristics Continuous source-drain diode current IS Pulsed diode forward current ISM Diode forward voltage VSD Reverse recovery time trr Reverse recovery charge Qrr Reverse recovery current IRRM MOSFET symbol showing the integral reverse p - n junction diode D A G S - - 22 TJ = 25 C, IS = 4.5 A, VGS = 0 V - - 1.2 - 207 414 ns - 2.2 4.4 C - 20 - A TJ = 25 C, IF = IS = 4.5 A, dI/dt = 100 A/s, VR = 25 V V Notes a. Coss(er) is a fixed capacitance that gives the same energy as Coss while VDS is rising from 0 % to 80 % VDSS. b. Coss(tr) is a fixed capacitance that gives the same charging time as Coss while VDS is rising from 0 % to 80 % VDSS. S17-0286-Rev. A, 27-Feb-17 Document Number: 91967 2 For technical questions, contact: hvm@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 SiHD9N60E www.vishay.com Vishay Siliconix TYPICAL CHARACTERISTICS (25 C, unless otherwise noted) 25 15 V 14 V 13 V 12 V 11 V 10 V 9V 8V 7V 6V BOTTOM 5 V 20 15 3.0 TJ = 25 C ID = 4.5 A RDS(on), Drain-to-Source On-Resistance (Normalized) 10 5 0 2.0 1.5 1.0 VGS = 10 V 0.5 0 0 5 10 15 VDS, Drain-to-Source Voltage (V) 20 -60 -40 -20 15 10 000 TOP 15 V 14 V 13 V 12 V 11 V 10 V 9V 8V 7V 6V BOTTOM 5 V 9 TJ = 150 C Ciss 1000 C, Capacitance (pF) 12 0 20 40 60 80 100 120 140 160 TJ, Junction Temperature (C) Fig. 4 - Normalized On-Resistance vs. Temperature Fig. 1 - Typical Output Characteristics ID, Drain-to-Source Current (A) 2.5 6 VGS = 0 V, f = 1 MHz Ciss = Cgs + Cgd, Cds shorted Crss = Cgd Coss = Cds + Cgd 100 Coss 10 Crss 3 0 1 0 5 10 15 VDS, Drain-to-Source Voltage (V) 20 0 100 200 300 400 500 VDS, Drain-to-Source Voltage (V) 600 Fig. 5 - Typical Capacitance vs. Drain-to-Source Voltage Fig. 2 - Typical Output Characteristics 7 10 000 25 6 Coss, Output Capacitance (pF) ID, Drain-to-Source Current (A) TJ = 25 C 20 15 TJ = 150 C 10 5 5 1000 4 Coss Eoss 3 100 2 1 VDS = 29.8 V 10 0 0 5 10 15 VGS, Gate-to-Source Voltage (V) Fig. 3 - Typical Transfer Characteristics S17-0286-Rev. A, 27-Feb-17 20 Eoss, Output Capacitance Stored Energy (J) ID, Drain-to-Source Current (A) TOP 0 0 100 200 300 400 500 VDS, Drain-to-Source Voltage (V) 600 Fig. 6 - Coss and Eoss vs. VDS Document Number: 91967 3 For technical questions, contact: hvm@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 SiHD9N60E www.vishay.com Vishay Siliconix 10 VDS = 480 V VDS = 300 V VDS = 120 V 8 9 ID, Drain Current (A) VGS, Gate-to-Source Voltage (V) 12 6 4 3 2 0 0 0 10 20 30 Qg, Total Gate Charge (nC) 25 40 Fig. 7 - Typical Gate Charge vs. Gate-to-Source Voltage 50 75 100 125 TC, Case Temperature (C) 150 Fig. 10 - Maximum Drain Current vs. Case Temperature 100 750 VDS, Drain-to-Source Breakdown Voltage (V) ISD, Reverse Drain Current (A) 6 TJ = 150 C 10 TJ = 25 C 1 VGS = 0 V 0.1 0.2 0.4 0.6 0.8 1.0 VSD, Source-Drain Voltage (V) 1.2 1.4 Fig. 8 - Typical Source-Drain Diode Forward Voltage 725 700 675 650 625 600 575 ID = 250 A 550 -60 -40 -20 0 20 40 60 80 100 120 140 160 TJ, Junction Temperature (C) Fig. 11 - Temperature vs. Drain-to-Source Voltage 100 Operation in this area limited by RDS(on) IDM limited ID, Drain Current (A) 10 100 s Limited by RDS(on)* 1 1 ms 0.1 10 ms TC = 25 C TJ = 150 C Single pulse BVDSS limited 0.01 1 10 100 1000 VDS, Drain-to-Source Voltage (V) * VGS > minimum VGS at which RDS(on) is specified Fig. 9 - Maximum Safe Operating Area S17-0286-Rev. A, 27-Feb-17 Document Number: 91967 4 For technical questions, contact: hvm@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 SiHD9N60E www.vishay.com Vishay Siliconix 1 Normalized Effective Transient Thermal Impedance Duty cycle = 0.5 0.2 0.1 0.1 0.05 0.02 Single pulse 0.01 0.0001 0.001 0.01 Pulse Time (s) 0.1 1 Fig. 12 - Normalized Thermal Transient Impedance, Junction-to-Case RD VDS VDS tp VGS VDD D.U.T. RG + - VDD VDS 10 V Pulse width 1 s Duty factor 0.1 % IAS Fig. 13 - Switching Time Test Circuit Fig. 16 - Unclamped Inductive Waveforms VDS QG 10 V 90 % QGS QGD VG 10 % VGS td(on) td(off) tf tr Charge Fig. 17 - Basic Gate Charge Waveform Fig. 14 - Switching Time Waveforms Current regulator Same type as D.U.T. L VDS Vary tp to obtain required IAS 50 k D.U.T. RG 12 V + - 0.2 F 0.3 F VDD + IAS D.U.T. - VDS 10 V tp 0.01 VGS 3 mA Fig. 15 - Unclamped Inductive Test Circuit IG ID Current sampling resistors Fig. 18 - Gate Charge Test Circuit S17-0286-Rev. A, 27-Feb-17 Document Number: 91967 5 For technical questions, contact: hvm@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 SiHD9N60E www.vishay.com Vishay Siliconix Peak Diode Recovery dV/dt Test Circuit + D.U.T. Circuit layout considerations * Low stray inductance * Ground plane * Low leakage inductance current transformer + - - Rg * * * * + dV/dt controlled by Rg Driver same type as D.U.T. ISD controlled by duty factor "D" D.U.T. - device under test + - VDD Driver gate drive P.W. Period D= P.W. Period VGS = 10 Va D.U.T. lSD waveform Reverse recovery current Body diode forward current dI/dt D.U.T. VDS waveform Diode recovery dV/dt Re-applied voltage Inductor current VDD Body diode forward drop Ripple 5 % ISD Note a. VGS = 5 V for logic level devices Fig. 19 - For N-Channel Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and reliability data, see www.vishay.com/ppg?91967. S17-0286-Rev. A, 27-Feb-17 Document Number: 91967 6 For technical questions, contact: hvm@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 Package Information Vishay Siliconix TO-252AA (HIGH VOLTAGE) E b3 E1 L3 D1 D H L4 b2 b A c2 e A1 L1 L c L2 MILLIMETERS INCHES DIM. MIN. MAX. MIN. MAX. E 6.40 6.73 0.252 0.265 L 1.40 1.77 0.055 L1 2.743 REF L2 0.070 0.108 REF 0.508 BSC 0.020 BSC L3 0.89 1.27 0.035 0.050 L4 0.64 1.01 0.025 0.040 D 6.00 6.22 0.236 0.245 H 9.40 10.40 0.370 0.409 b 0.64 0.88 0.025 0.035 b2 0.77 1.14 0.030 0.045 b3 5.21 5.46 0.205 e 2.286 BSC 0.215 0.090 BSC A 2.20 2.38 0.087 A1 0.00 0.13 0.000 0.094 0.005 c 0.45 0.60 0.018 0.024 c2 0.45 0.58 0.018 0.023 D1 5.30 - 0.209 - E1 4.40 - 0.173 - 0' 10' 0' 10' ECN: S-81965-Rev. A, 15-Sep-08 DWG: 5973 Notes 1. Package body sizes exclude mold flash, protrusion or gate burrs. Mold flash, protrusion or gate burrs shall not exceed 0.10 mm per side. 2. Package body sizes determined at the outermost extremes of the plastic body exclusive of mold flash, gate burrs and interlead flash, but including any mismatch between the top and bottom of the plastic body. 3. The package top may be smaller than the package bottom. 4. Dimension "b" does not include dambar protrusion. Allowable dambar protrusion shall be 0.10 mm total in excess of "b" dimension at maximum material condition. The dambar cannot be located on the lower radius of the foot. Document Number: 91344 Revision: 15-Sep-08 www.vishay.com 1 Application Note 826 Vishay Siliconix RECOMMENDED MINIMUM PADS FOR DPAK (TO-252) 0.224 0.243 0.087 (2.202) 0.090 (2.286) (10.668) 0.420 (6.180) (5.690) 0.180 0.055 (4.572) (1.397) Recommended Minimum Pads Dimensions in Inches/(mm) Return to Index Return to Index APPLICATION NOTE Document Number: 72594 Revision: 21-Jan-08 www.vishay.com 3 Legal Disclaimer Notice www.vishay.com Vishay Disclaimer ALL PRODUCT, PRODUCT SPECIFICATIONS AND DATA ARE SUBJECT TO CHANGE WITHOUT NOTICE TO IMPROVE RELIABILITY, FUNCTION OR DESIGN OR OTHERWISE. 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Except as expressly indicated in writing, Vishay products are not designed for use in medical, life-saving, or life-sustaining applications or for any other application in which the failure of the Vishay product could result in personal injury or death. Customers using or selling Vishay products not expressly indicated for use in such applications do so at their own risk. Please contact authorized Vishay personnel to obtain written terms and conditions regarding products designed for such applications. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document or by any conduct of Vishay. Product names and markings noted herein may be trademarks of their respective owners. (c) 2021 VISHAY INTERTECHNOLOGY, INC. ALL RIGHTS RESERVED Revision: 01-Jan-2021 1 Document Number: 91000