SiHD9N60E
www.vishay.com Vishay Siliconix
S17-0286-Rev. A, 27-Feb-17 1Document Number: 91967
For technical questions, contact: hvm@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
E Series Power MOSFET
FEATURES
• Low figure-of-merit (FOM) Ron x Qg
• Low input capacitance (Ciss)
• Reduced switching and conduction losses
• Ultra low gate charge (Qg)
• Avalanche energy rated (UIS)
• Material categorization: for definitions of compliance
please see www.vishay.com/doc?99912
APPLICATIONS
• Server and telecom power supplies
• Switch mode power supplies (SMPS)
• Power factor correction power supplies (PFC)
• Lighting
- High-intensity discharge (HID)
- Fluorescent ballast lighting
• Industrial
- Welding
- Induction heating
- Motor drives
- Battery chargers
- Renewable energy
- Solar (PV inverters)
Notes
a. Repetitive rating; pulse width limited by maximum junction temperature.
b. VDD = 140 V, starting TJ = 25 °C, L = 28.2 mH, Rg = 25 , IAS = 2.8 A.
c. 1.6 mm from case.
d. ISD ID, dI/dt = 100 A/μs, starting TJ = 25 °C.
PRODUCT SUMMARY
VDS (V) at TJ max. 650
RDS(on) typ. () at 25 °C VGS = 10 V 0.320
Qg max. (nC) 52
Qgs (nC) 6
Qgd (nC) 13
Configuration Single
N-Channel MOSFET
G
D
S
DPAK
(TO-252)
S
D
G
ORDERING INFORMATION
Package DPAK (TO-252)
Lead (Pb)-free and halogen-free SiHD9N60E-GE3
ABSOLUTE MAXIMUM RATINGS (TC = 25 °C, unless otherwise noted)
PARAMETER SYMBOL LIMIT UNIT
Drain-source voltage VDS 600 V
Gate-source voltage VGS ± 30
Continuous drain current (TJ = 150 °C) VGS at 10 V TC = 25 °C ID
9
ATC = 100 °C 6
Pulsed drain current a IDM 22
Linear derating factor 0.63 W/°C
Single pulse avalanche energy b EAS 111 mJ
Maximum power dissipation PD78 W
Operating junction and storage temperature range TJ, Tstg -55 to +150 °C
Drain-source voltage slope TJ = 125 °C dV/dt 70 V/ns
Reverse diode dV/dt d 40
Soldering recommendations (peak temperature) cFor 10 s 300 °C
SiHD9N60E
www.vishay.com Vishay Siliconix
S17-0286-Rev. A, 27-Feb-17 2Document Number: 91967
For technical questions, contact: hvm@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
Notes
a. Coss(er) is a fixed capacitance that gives the same energy as Coss while VDS is rising from 0 % to 80 % VDSS.
b. Coss(tr) is a fixed capacitance that gives the same charging time as Coss while VDS is rising from 0 % to 80 % VDSS.
THERMAL RESISTANCE RATINGS
PARAMETER SYMBOL TYP. MAX. UNIT
Maximum Junction-to-Ambient RthJA -62
°C/W
Maximum Junction-to-Case (Drain) RthJC -1.6
SPECIFICATIONS (TJ = 25 °C, unless otherwise noted)
PARAMETER SYMBOL TEST CONDITIONS MIN. TYP. MAX. UNIT
Static
Drain-source breakdown voltage VDS VGS = 0 V, ID = 250 μA 600 - - V
VDS temperature coefficient VDS/TJ Reference to 25 °C, ID = 1 mA - 0.71 - V/°C
Gate-source threshold voltage (N) VGS(th) VDS = VGS, ID = 250 μA 2.5 - 4.5 V
Gate-source leakage IGSS VGS = ± 20 V - - ± 100 nA
VGS = ± 30 V - - ± 1 μA
Zero gate voltage drain current IDSS
VDS = 600 V, VGS = 0 V - - 1 μA
VDS = 480 V, VGS = 0 V, TJ = 125 °C - - 10
Drain-source on-state resistance RDS(on) V
GS = 10 V ID = 4.5 A - 0.320 0.368
Forward Transconductance gfs VDS = 30 V, ID = 4.5 A - 2.4 - S
Dynamic
Input capacitance Ciss VGS = 0 V,
VDS = 100 V,
f = 1 MHz
- 778 -
pF
Output capacitance Coss -48-
Reverse transfer capacitance Crss -4-
Effective output capacitance, energy
related a Co(er)
VDS = 0 V to 480 V, VGS = 0 V
-29-
Effective output capacitance, time
related b Co(tr) - 138 -
Total gate charge Qg
VGS = 10 V ID = 4.5 A, VDS = 480 V
-2652
nC Gate-source charge Qgs -6-
Gate-drain charge Qgd -13-
Turn-on delay time td(on)
VDD = 480 V, ID = 4.5 A,
VGS = 10 V, Rg = 9.1
-1428
ns
Rise time tr -1326
Turn-off delay time td(off) -3162
Fall time tf -1224
Gate input resistance Rgf = 1 MHz, open drain 0.4 1.2 2.4
Drain-Source Body Diode Characteristics
Continuous source-drain diode current ISMOSFET symbol
showing the
integral reverse
p - n junction diode
--9
A
Pulsed diode forward current ISM --22
Diode forward voltage VSD TJ = 25 °C, IS = 4.5 A, VGS = 0 V - - 1.2 V
Reverse recovery time trr TJ = 25 °C, IF = IS = 4.5 A,
dI/dt = 100 A/μs, VR = 25 V
- 207 414 ns
Reverse recovery charge Qrr -2.24.4μC
Reverse recovery current IRRM -20-A
S
D
G
SiHD9N60E
www.vishay.com Vishay Siliconix
S17-0286-Rev. A, 27-Feb-17 3Document Number: 91967
For technical questions, contact: hvm@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted)
Fig. 1 - Typical Output Characteristics
Fig. 2 - Typical Output Characteristics
Fig. 3 - Typical Transfer Characteristics
Fig. 4 - Normalized On-Resistance vs. Temperature
Fig. 5 - Typical Capacitance vs. Drain-to-Source Voltage
Fig. 6 - Coss and Eoss vs. VDS
0
5
10
15
20
25
0 5 10 15 20
ID, Drain-to-Source Current (A)
VDS, Drain-to-Source Voltage (V)
TJ= 25 °C
TOP 15 V
14 V
13 V
12 V
11 V
10 V
9 V
8 V
7 V
6 V
BOTTOM 5 V
0
3
6
9
12
15
0 5 10 15 20
ID, Drain-to-Source Current (A)
VDS, Drain-to-Source Voltage (V)
TJ= 150 °C
TOP 15 V
14 V
13 V
12 V
11 V
10 V
9 V
8 V
7 V
6 V
BOTTOM 5 V
0
5
10
15
20
25
0 5 10 15 20
I
D
, Drain-to-Source Current (A)
V
GS
, Gate-to-Source Voltage (V)
T
J
= 150 °C
T
J
= 25 °C
V
DS
= 29.8 V
0
0.5
1.0
1.5
2.0
2.5
3.0
-60 -40 -20 0 20 40 60 80 100 120 140 160
RDS(on), Drain-to-Source On-Resistance
(Normalized)
TJ, Junction Temperature (°C)
ID= 4.5 A
VGS = 10 V
1
10
100
1000
10 000
0 100 200 300 400 500 600
C, Capacitance (pF)
V
DS
, Drain-to-Source Voltage (V)
C
iss
C
oss
C
rss
V
GS
= 0 V, f = 1 MHz
C
iss
= C
gs
+ C
gd
, C
ds
shorted
C
rss
= C
gd
C
oss
= C
ds
+ C
gd
0
1
2
3
4
5
6
7
10
100
1000
10 000
0 100 200 300 400 500 600
Eoss, Output Capacitance Stored Energy (μJ)
Coss, Output Capacitance (pF)
VDS, Drain-to-Source Voltage (V)
Coss Eoss
SiHD9N60E
www.vishay.com Vishay Siliconix
S17-0286-Rev. A, 27-Feb-17 4Document Number: 91967
For technical questions, contact: hvm@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
Fig. 7 - Typical Gate Charge vs. Gate-to-Source Voltage
Fig. 8 - Typical Source-Drain Diode Forward Voltage
Fig. 9 - Maximum Safe Operating Area
Fig. 10 - Maximum Drain Current vs. Case Temperature
Fig. 11 - Temperature vs. Drain-to-Source Voltage
0
3
6
9
12
0 10203040
VGS, Gate-to-Source Voltage (V)
Qg, Total Gate Charge (nC)
VDS= 480 V
VDS= 300 V
VDS= 120 V
0.1
1
10
100
0.2 0.4 0.6 0.8 1.0 1.2 1.4
ISD, Reverse Drain Current (A)
VSD, Source-Drain Voltage (V)
TJ= 150 °C
TJ= 25 °C
VGS = 0 V
0.01
0.1
1
10
100
1101001000
ID, Drain Current (A)
VDS, Drain-to-Source Voltage (V)
* VGS > minimum VGS at which RDS(on) is specied
Limited by RDS(on)*
1 ms
IDM limited
TC= 25 °C
TJ= 150 °C
Single pulse
BVDSS limited
10 ms
100 μs
Operation in this area
limited by RDS(on)
0
2
4
6
8
10
25 50 75 100 125 150
ID, Drain Current (A)
TC, Case Temperature (°C)
550
575
600
625
650
675
700
725
750
-60 -40 -20 0 20 40 60 80 100 120 140 160
VDS, Drain-to-Source Breakdown Voltage (V)
TJ, Junction Temperature (°C)
ID= 250 μA
SiHD9N60E
www.vishay.com Vishay Siliconix
S17-0286-Rev. A, 27-Feb-17 5Document Number: 91967
For technical questions, contact: hvm@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
Fig. 12 - Normalized Thermal Transient Impedance, Junction-to-Case
Fig. 13 - Switching Time Test Circuit
Fig. 14 - Switching Time Waveforms
Fig. 15 - Unclamped Inductive Test Circuit
Fig. 16 - Unclamped Inductive Waveforms
Fig. 17 - Basic Gate Charge Waveform
Fig. 18 - Gate Charge Test Circuit
0.01
0.1
1
0.0001 0.001 0.01 0.1 1
Normalized Effective Transient
Thermal Impedance
Pulse Time (s)
Duty cycle = 0.5
0.2
0.1
0.05
0.02
Single pulse
VDS
90 %
10 %
VGS
td(on) trtd(off) tf
RG
IAS
0.01 Ω
tp
D.U.T.
L
VDS
+
-VDD
10 V
Vary tp to obtain
required IAS
IAS
V
DS
VDD
VDS
tp
QGS QGD
QG
VG
Charge
10 V
D.U.T.
3 mA
VGS
VDS
IGID
0.3 µF
0.2 µF
50 kΩ
12 V
Current regulator
Current sampling resistors
Same type as D.U.T.
+
-
SiHD9N60E
www.vishay.com Vishay Siliconix
S17-0286-Rev. A, 27-Feb-17 6Document Number: 91967
For technical questions, contact: hvm@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
Fig. 19 - For N-Channel
Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon
Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and
reliability data, see www.vishay.com/ppg?91967.
P.W. Period
dI/dt
Diode recovery
dV/dt
Ripple ≤ 5 %
Body diode forward drop
Re-applied
voltage
Reverse
recovery
current
Body diode forward
current
VGS = 10 Va
ISD
Driver gate drive
D.U.T. lSD waveform
D.U.T. VDS waveform
Inductor current
D = P.W.
Period
+
-
+
+
+
-
-
-
Peak Diode Recovery dV/dt Test Circuit
VDD
• dV/dt controlled by Rg
• Driver same type as D.U.T.
• ISD controlled by duty factor “D”
• D.U.T. - device under test
D.U.T. Circuit layout considerations
• Low stray inductance
• Ground plane
• Low leakage inductance
current transformer
Rg
Note
a. VGS = 5 V for logic level devices
VDD
Document Number: 91344 www.vishay.com
Revision: 15-Sep-08 1
Package Information
Vishay Siliconix
TO-252AA (HIGH VOLTAGE)
Notes
1. Package body sizes exclude mold flash, protrusion or gate burrs. Mold flash, protrusion or gate burrs shall not exceed 0.10 mm per side.
2. Package body sizes determined at the outermost extremes of the plastic body exclusive of mold flash, gate burrs and interlead flash, but
including any mismatch between the top and bottom of the plastic body.
3. The package top may be smaller than the package bottom.
4. Dimension "b" does not include dambar protrusion. Allowable dambar protrusion shall be 0.10 mm total in excess of "b" dimension at maximum
material condition. The dambar cannot be located on the lower radius of the foot.
E
b3
L3
L4
b2
e
b
D H
E1
D1
A
c2
L1
L2
c
A1
L
θ
MILLIMETERS INCHES
DIM. MIN. MAX. MIN. MAX.
E 6.40 6.73 0.252 0.265
L 1.40 1.77 0.055 0.070
L1 2.743 REF 0.108 REF
L2 0.508 BSC 0.020 BSC
L3 0.89 1.27 0.035 0.050
L4 0.64 1.01 0.025 0.040
D 6.00 6.22 0.236 0.245
H 9.40 10.40 0.370 0.409
b 0.64 0.88 0.025 0.035
b2 0.77 1.14 0.030 0.045
b3 5.21 5.46 0.205 0.215
e 2.286 BSC 0.090 BSC
A 2.20 2.38 0.087 0.094
A1 0.00 0.13 0.000 0.005
c 0.45 0.60 0.018 0.024
c2 0.45 0.58 0.018 0.023
D1 5.30 - 0.209 -
E1 4.40 - 0.173 -
θ0' 10' 0' 10'
ECN: S-81965-Rev. A, 15-Sep-08
DWG: 5973
Application Note 826
Vishay Siliconix
Document Number: 72594 www.vishay.com
Revision: 21-Jan-08 3
APPLICATION NOTE
RECOMMENDED MINIMUM PADS FOR DPAK (TO-252)
0.420
(10.668)
Recommended Minimum Pads
Dimensions in Inches/(mm)
0.224
(5.690)
0.180
(4.572)
0.055
(1.397)
0.243
(6.180)
0.087
(2.202)
0.090
(2.286)
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Revision: 01-Jan-2021 1Document Number: 91000
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