May 2007 Rev 7 1/26
1
STM6321/6322
STM6821/6822/6823/6824/6825
5-pin Supervisor with watchdog timer and push-button reset
Features
■Precision VCC monitoring of 5, 3.3, 3, or 2.5V
power supplies
■RST Outputs (active-low, push-pull or open
drain)
■RST Outputs (active-high, push-pull)
■Reset pulse width of 1.4ms, 200ms and 240ms
(typ) (a)
■Watchdog timeout period of 1.6s (typ) (a)
■Manual reset input (MR)
■Low supply current - 3µA (typ)
■Guaranteed RST (RST) assertion down to
VCC = 1.0V
■Operating temperature: –40 to +85°C
(industrial grade)
■RoHS Compliance
Lead-free components are compliant with the
RoHS directive.
a. Other trec and watchdog timings are offered. Minimum order quantities may apply. Contact
local sales office for availability.
SOT23-5 (WY)
Table 1. Device options
Part number Watchdog input Manual reset
input
Reset output
Active-low
(push-pull)
Active-high
(push-pull)
Active-low
(open drain)
STM6321 ✔✔✔
STM6322 ✔✔✔
STM6821 ✔✔ ✔
STM6822 ✔✔ ✔
STM6823 ✔✔✔
STM6824 ✔✔✔
STM6825 ✔✔✔
www.st.com
Contents STM6321/6322STM6821/6822/6823/6824/6825
2/26
Contents
1 Summary description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
1.1 Pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
1.1.1 Active-low, push-pull reset output (RST) - STM6822/6823/6824/6825 . . 7
1.1.2 Active-low, open drain reset output (RST) - STM6321/6322/6822 . . . . . 7
1.1.3 Push-button reset input (MR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
1.1.4 Watchdog input (WDI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
1.1.5 Active-high reset output (RST) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.1 Reset output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.2 Open drain RST output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.3 Push-button reset input (STM6322/6821/6822/6823/6825) . . . . . . . . . . . 11
2.4 Watchdog input (STM6321/6821/6822/6823/6824) . . . . . . . . . . . . . . . . . 11
2.5 Applications information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.5.1 Watchdog input current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.5.2 Ensuring a valid reset output down to VCC = 0V . . . . . . . . . . . . . . . . . . 11
2.6 Interfacing to microprocessors with bi-directional reset pins . . . . . . . . . . 12
3 Typical operating characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4 Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
5 DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
6 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
7 Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
8 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
STM6321/6322STM6821/6822/6823/6824/6825 List of tables
3/26
List of tables
Table 1. Device options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Table 2. Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Table 3. Pin functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Table 4. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Table 5. Operating and AC measurement conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Table 6. DC and AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Table 7. SOT23-5 – 5-lead small outline transistor package mechanical data. . . . . . . . . . . . . . . . . 22
Table 8. Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Table 9. Marking description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Table 10. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
List of figures STM6321/6322STM6821/6822/6823/6824/6825
4/26
List of figures
Figure 1. Logic diagram (STM6821/6822/6823) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Figure 2. Logic diagram (STM6321/6322/6824/6825) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Figure 3. STM6822/6823 SOT23-5 connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 4. STM6821 SOT23-5 connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 5. STM6322/6825 SOT23-5 connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 6. STM6321/6824 SOT23-5 connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 7. Block diagram (STM6821/6822/6823) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 8. Block diagram (STM6321/6824) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 9. Block diagram (STM6322/6825) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 10. Hardware hookup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 11. STM6321/6322/6822 open drain RST output with multiple supplies . . . . . . . . . . . . . . . . . 10
Figure 12. Ensuring RST valid to VCC = 0, (active-low push-pull outputs). . . . . . . . . . . . . . . . . . . . . . 12
Figure 13. Ensuring RST valid to VCC = 0, (active-high, push-pull outputs) . . . . . . . . . . . . . . . . . . . . 12
Figure 14. Interfacing to microprocessors with bi-directional reset I/O . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 15. VCC-to-Reset output delay vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 16. Supply current vs. temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 17. MR-to-reset output delay vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 18. Normalized power-up trec vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 19. Normalized reset threshold voltage vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 20. Normalized power-up watchdog time-out period . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 21. Voltage output low vs. ISINK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 22. Voltage output high vs. ISOURCE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 23. Maximum transient duration vs. reset threshold overdrive . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 24. AC Testing input/output waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 25. MR timing waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 26. Watchdog timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 27. SOT23-5 – 5-lead small outline transistor package mechanical drawing . . . . . . . . . . . . . . 22
STM6321/6322STM6821/6822/6823/6824/6825 Summary description
5/26
1 Summary description
The STM6xxx Supervisors are self-contained devices which provide microprocessor
supervisory functions. A precision voltage reference and comparator monitors the VCC input
for an out-of-tolerance condition. When an invalid VCC condition occurs, the reset output
(RST) is forced low (or high in the case of RST). These devices also offer a watchdog timer
(except for STM6322/6825) and/or a push-button (MR) reset input.
These devices are available in a standard 5-pin SOT23 package.
Figure 1. Logic diagram (STM6821/6822/6823)
1. For STM6821 only.
Figure 2. Logic diagram (STM6321/6322/6824/6825)
1. For STM6321/6824.
Table 2. Signal names
MR Push-button Reset Input
WDI Watchdog Input
RST Active-low Reset Output
RST Active-high Reset Output
VCC Supply voltage
VSS Ground
AI09128
VCC
STM6XXX
VSS
RST (RST)(1)
WDI
MR
AI09129
VCC
STM6XXX
VSS
RST
RST
(WDI)(1) MR
Summary description STM6321/6322STM6821/6822/6823/6824/6825
6/26
Figure 3. STM6822/6823 SOT23-5 connections
1. Open drain for STM6822.
Figure 4. STM6821 SOT23-5 connections
1. Push-pull only.
Figure 5. STM6322/6825 SOT23-5 connections
1. Open drain for STM6322.
2. Push-pull only.
Figure 6. STM6321/6824 SOT23-5 connections
1. Open drain for STM6321.
2. Push-pull only.
1
WDI
RST
(1)
V
CC
MR
V
SS
AI09130a
SOT23-5
2
34
5
1
WDI
RST
(1)
V
CC
MR
V
SS
AI12285
SOT23-5
2
34
5
1V
CC
V
SS
AI09131a
SOT23-5
2
34
5
MR
RST
(1)
RST
(2)
1V
CC
V
SS
AI12286
SOT23-5
2
34
5
WDI
RST
(1)
RST
(2)
STM6321/6322STM6821/6822/6823/6824/6825 Summary description
7/26
1.1 Pin descriptions
1.1.1 Active-low, push-pull reset output (RST) - STM6822/6823/6824/6825
Pulses low when triggered, and stays low whenever VCC is below the reset threshold or
when MR is a logic low. It remains low for trec after either VCC rises above the reset
threshold, the watchdog triggers a reset, or MR goes from low to high.
1.1.2 Active-low, open drain reset output (RST) - STM6321/6322/6822
Pulses low when triggered, and stays low whenever VCC is below the reset threshold or
when MR is a logic low. It remains low for trec after either VCC rises above the reset
threshold, the watchdog triggers a reset, or MR goes from low to high. Connect a pull-up
resistor to supply voltage.
1.1.3 Push-button reset input (MR)
A logic low on MR asserts the reset output. Reset remains asserted as long as MR is low
and for trec after MR returns high. This active-low input has an internal 52kΩ pull-up. It can
be driven from a TTL or CMOS logic line, or shorted to ground with a switch. Leave open if
unused.
1.1.4 Watchdog input (WDI)
If WDI remains high or low for at least 1.6s, the internal watchdog timer expires and reset is
asserted. The internal watchdog timer clears while reset is asserted or when WDI sees a
rising or falling edge. The watchdog function CAN be disabled if WDI is left unconnected or
is connected to a tri-state buffer output.
1.1.5 Active-high reset output (RST)
Active-high, push-pull reset output; inverse of RST.
Table 3. Pin functions
Pin
Name Function
STM6822
STM6823 STM6821 STM6321
STM6824
STM6322
STM6825
1—1 1RST
Active-Low Reset Output
33—4MR
Push-button Reset Input
4 4 4 — WDI Watchdog Input
— 1 3 3 RST Active-High Reset Output
5555V
CC Supply Voltage
2222V
SS Ground
Summary description STM6321/6322STM6821/6822/6823/6824/6825
8/26
Figure 7. Block diagram (STM6821/6822/6823)
1. Push-pull for STM6823, open drain for STM6822.
2. Active-high (push-pull) for STM6821.
Figure 8. Block diagram (STM6321/6824)
3. Acive-low (open drain) for STM6321, active-low (push-pull) for STM6824.
4. Push-pull only.
Figure 9. Block diagram (STM6322/6825)
1. Active-low (open drain) for STM6322, active-low (push-pull) for STM6825.
2. Push-pull only.
AI09132a
VRST RST (RST)(1,2)
WATCHDOG
TIMER
WDI
Transitional
Detector
COMPARE trec
Generator
VCC
WDI
MR
VCC
A12287
V
RST
RST
(1)
WATCHDOG
TIMER
WDI
Transitional
Detector
COMPARE t
rec
Generator
V
CC
WDI
RST
(2)
AI12288
V
RST
RST
(1)
COMPARE t
rec
Generator
V
CC
MR
RST
(2)
V
CC
STM6321/6322STM6821/6822/6823/6824/6825 Summary description
9/26
Figure 10. Hardware hookup
1. For STM6321/6821/6822/6823/6824
2. For STM6322/6821/6822/6823/6825
3. For STM6821/ (RST output only)
4. For STM6321/6322/6824/6825 (both RST and RST outputs)
AI09133
V
CC
V
CC
MR
(2)
0.1μFSTM6XXX
WDI
(1)
RST (RST)
(3)
RST
(4)
To Microprocessor Reset
From Microprocessor
Push-button
To Microprocessor Reset
Operation STM6321/6322STM6821/6822/6823/6824/6825
10/26
2 Operation
2.1 Reset output
The STM6xxx Supervisor asserts a reset signal to the MCU whenever VCC goes below the
reset threshold (VRST), a watchdog time-out occurs, or when the Push-button Reset Input
(MR) is taken low. Reset is guaranteed valid for VCC < VRST down to VCC =1V for TA = 0°C
to 85°C.
During power-up, once VCC exceeds the reset threshold an internal timer keeps reset low
for the reset time-out period, trec. After this interval reset is de-asserted.
Each time RST is asserted, it stays low for at least the reset time-out period (trec). Any time
VCC goes below the reset threshold the internal timer clears. The reset timer starts when
VCC returns above the reset threshold.
2.2 Open drain RST output
The STM6321/6322/6822 have an active-low, open drain reset output. This output structure
will sink current when RST is asserted. Connect a pull-up resistor from RST to any supply
voltage up to 6V (see Figure 11). Select a resistor value large enough to register a logic low,
and small enough to register a logic high while supplying all input current and leakage paths
connected to the reset output line. A 10kΩ pull-up resistor is sufficient in most applications.
Figure 11. STM6321/6322/6822 open drain RST output with multiple supplies
1. STM6322/6822
2. STM6321/6822
3. STM6321/6322
AI09137
STM6XXX
RST
MR
(1)
WDI
(2)
RST
(3)
GND
10k
V
CC
5V System
5.0V3.3V
STM6321/6322STM6821/6822/6823/6824/6825 Operation
11/26
2.3 Push-button reset input (STM6322/6821/6822/6823/6825)
A logic low on MR asserts reset. Reset remains asserted while MR is low, and for trec (see
Figure 25 on page 19) after it returns high. The MR input has an internal 52kΩ pull-up
resistor, allowing it to be left open if not used. This input can be driven with TTL/CMOS-logic
levels or with open-drain/collector outputs. Connect a normally open momentary switch from
MR to GND to create a manual reset function; external debounce circuitry is not required. If
MR is driven from long cables or the device is used in a noisy environment, connect a 0.1µF
capacitor from MR to GND to provide additional noise immunity. MR may float, or be tied to
VCC when not used.
2.4 Watchdog input (STM6321/6821/6822/6823/6824)
The watchdog timer can be used to detect an out-of-control MCU. If the MCU does not
toggle the Watchdog Input (WDI) within tWD (1.6sec), the reset is asserted. The internal
watchdog timer is cleared by either:
1. a reset pulse, or
2. by toggling WDI (high-to-low or low-to-high), which can detect pulses as short as 50ns.
The timer remains cleared and does not count for as long as reset is asserted. As soon as
reset is released, the timer starts counting.
Note: The watchdog function may be disabled by floating WDI or tri-stating the driver connected to
WDI. When tri-stated or disconnected, the maximum allowable leakage current is 10µA and
the maximum allowable load capacitance is 200pF.
2.5 Applications information
2.5.1 Watchdog input current
The WDI input is internally driven through a buffer and series resistor from the watchdog
counter. For minimum watchdog input current (minimum overall power consumption), leave
WDI low for the majority of the watchdog time-out period. When high, WDI can draw as
much as 160µA. Pulsing WDI high at a low duty cycle will reduce the effect of the large input
current. When WDI is left unconnected, the watchdog timer is serviced within the watchdog
time-out period by a low-high-low pulse from the counter chain.
2.5.2 Ensuring a valid reset output down to VCC =0V
The STM6xxx Supervisors are guaranteed to operate properly down to VCC = 1V. In
applications that require valid reset levels down to VCC = 0, a pull-down resistor to active-
low outputs (push/pull only, see Figure 12 on page 12) and a pull-up resistor to active-high
outputs (push/pull only, see Figure 13 on page 12) will ensure that the reset line is valid
while the reset output can no longer sink or source current. This scheme does not work with
the open drain outputs of the STM6321/6322/6822.
The resistor value used is not critical, but it must be large enough not to load the reset
output when VCC is above the reset threshold. For most applications, 100kΩ is adequate.
Operation STM6321/6322STM6821/6822/6823/6824/6825
12/26
Figure 12. Ensuring RST valid to VCC = 0, (active-low push-pull outputs)
Figure 13. Ensuring RST valid to VCC = 0, (active-high, push-pull outputs)
1. This configuration does not work on open drain outputs of the STM6321/6322/6822.
2.6 Interfacing to microprocessors with bi-directional reset pins
Microprocessors with bi-directional reset pins can contend with the STM6321
/
6322
/
6821
/
6822
/
6823
/
6824
/
6825 reset output. For example, if the reset output is driven high and the
microprocessor wants to pull it low, signal contention will result. To prevent this from
occurring, connect a 4.7kΩ resistor between the reset output and the microprocessor’s reset
I/O as in Figure 14.
Figure 14. Interfacing to microprocessors with bi-directional reset I/O
AI09138
STM6XXX
RSTGND
V
CC
V
CC
R1
AI09139
STM6XXX
RST
GND
V
CC
V
CC
R1
AI09135
STM6XXX
RST
GND
4.7k
V
CC
Microprocessor
RST
Buffered Reset to other
System Components
GND
V
CC
STM6321/6322STM6821/6822/6823/6824/6825 Typical operating characteristics
13/26
3 Typical operating characteristics
Figure 15. VCC-to-Reset output delay vs. temperature
Figure 16. Supply current vs. temperature
Temperature (˚C)
Reset Output Delay (µs)
AI09627a
0
5
10
15
20
25
30
35
–40 –20 0 20 40 60 80
Temperature (˚C)
Supply Current (µA)
VCC = 3V
VCC = 5V
AI09628a
0
1
2
3
4
5
6
7
–40 –20 0 20 40 60 80
Typical operating characteristics STM6321/6322STM6821/6822/6823/6824/6825
14/26
Figure 17. MR-to-reset output delay vs. temperature
Figure 18. Normalized power-up trec vs. temperature
Temperature (˚C)
Reset Output Delay (ns)
AI09669
0
100
200
300
400
500
600
–40 –20 0 20 40 60 80
Temperature (˚C)
Normalized Power-up trec
AI09670
0.99
1.00
1.01
1.02
1.03
1.04
1.05
–40 –20 0 20 40 60 80
STM6321/6322STM6821/6822/6823/6824/6825 Typical operating characteristics
15/26
Figure 19. Normalized reset threshold voltage vs. temperature
Figure 20. Normalized power-up watchdog time-out period
Temperature (˚C)
Normalized Reset Threshold Voltage
AI09631a
0.95
0.96
0.97
0.98
0.99
1.00
1.01
1.02
1.03
1.04
1.05
–40 –20 0 20 40 60 80
Temperature (˚C)
Normalized Watchdog Time-out Period
AI09671
0.99
1.00
1.01
1.02
1.03
1.04
1.05
–40 –20 0 20 40 60 80
Typical operating characteristics STM6321/6322STM6821/6822/6823/6824/6825
16/26
Figure 21. Voltage output low vs. ISINK
Figure 22. Voltage output high vs. ISOURCE
ISINK (mA)
VOUT (V)
VCC = 2.9V
AI09634a
0.00
0.05
0.10
0.15
0.20
0.25
0.30
0.35
0123456
ISOURCE (mA)
VOUT (V)
AI09635a
2.74
2.76
2.78
2.80
2.82
2.84
2.86
2.88
2.90
2.92
0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
VCC = 2.9V
STM6321/6322STM6821/6822/6823/6824/6825 Typical operating characteristics
17/26
Figure 23. Maximum transient duration vs. reset threshold overdrive
Reset Threshold Overdrive (mV)
Transient Duration (µs)
AI09637a
0
5
10
15
20
25
30
35
0 20 40 60 80 100 120 140 160 180 200
S
Z
L
Maximum rating STM6321/6322STM6821/6822/6823/6824/6825
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4 Maximum rating
Stressing the device above the rating listed in the Ta b l e 4 may cause permanent damage to
the device. These are stress ratings only and operation of the device at these or any other
conditions above those indicated in the Operating sections of this specification is not
implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect
device reliability. Refer also to the STMicroelectronics SURE Program and other relevant
quality documents.
Table 4. Absolute maximum ratings
Symbol Parameter Value Unit
TSTG Storage Temperature (VCC Off) –55 to 150 °C
TSLD(1)
1. Reflo
w at peak temperature of 260°C (total thermal budget not to exceed 245°C for greater than 30 seco
nds).
Lead Solder Temperature for 10 seconds 260 °C
VIO Input or Output Voltage –0.3 to VCC +0.3 V
VCC Supply Voltage –0.3 to 7.0 V
IOOutput Current 20 mA
PDPower Dissipation 320 mW
STM6321/6322STM6821/6822/6823/6824/6825 DC and AC parameters
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5 DC and AC parameters
This section summarizes the operating measurement conditions, and the DC and AC
characteristics of the device. The parameters in the DC and AC characteristics Tables that
follow, are derived from tests performed under the Measurement Conditions summarized in
Ta bl e 5 . Designers should check that the operating conditions in their circuit match the
operating conditions when relying on the quoted parameters.
Table 5. Operating and AC measurement conditions
Figure 24. AC Testing input/output waveforms
Figure 25. MR timing waveform
1. RST for STM6322/6821/6825.
Figure 26. Watchdog timing
Parameter STM6xxx Unit
VCC Supply Voltage 1.0 to 5.5 V
Ambient operating temperature (TA)–40 to 85°C
Input rise and fall times ≤ 5ns
Input pulse voltages 0.2 to 0.8VCC V
Input and output timing ref. voltages 0.3 to 0.7VCC V
AI02568
0.8VCC
0.2VCC
0.7VCC
0.3VCC
AI07837a
RST
(1)
MR
tMLRL
trec
tMLMH
AI09136
RST
WDI
V
CC
trec
tWD
DC and AC parameters STM6321/6322STM6821/6822/6823/6824/6825
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Table 6. DC and AC characteristics
Sym Alter-
native Description Test Condition (1) Min Typ Max Unit
VCC Operating Voltage 1.2 (2) 5.5 V
ICC
VCC Supply Current
(MR and WDI unconnected)
T/S/R/Z (VCC < 3.6V) 4 12 µA
L/M (VCC < 5.5V) 6 17 µA
VCC Supply Current
(MR unconnected;
STM6322/6825)
T/S/R/Z (VCC < 3.6V) 3 8 µA
L/M (VCC < 5.5V) 3 12 µA
ILI
Input Leakage Current 0V = VIN = VCC –1 +1 µA
Input Leakage Current
(WDI)(3)
WDI = VCC, time average 120 160 µA
WDI = GND, time average –20 –15 µA
ILO
Open Drain Reset Output
Leakage Current
VCC > VRST
,
Reset not asserted –1 +1 µA
VIH Input High Voltage (MR)VRST > 4.0V 2.0 V
VRST < 4.0V 0.7VCC V
VIH Input High Voltage (WDI) (4) VRST (max) < VCC < 5.5V 0.7VCC V
VIL Input Low Voltage (MR)VRST > 4.0V 0.8 V
VRST < 4.0V 0.3VCC V
VIL Input Low Voltage (WDI) (4) VRST (max) < VCC < 5.5V 0.3VCC V
VOL
Output Low Voltage (RST;
Push-pull or Open Drain)
VCC ≥ 1.0V, ISINK = 50µA,
Reset asserted 0.3 V
VCC ≥ 1.2V, ISINK = 100µA,
Reset asserted 0.3 V
VCC ≥ 2.7V, ISINK = 1.2mA,
Reset asserted 0.3 V
VCC ≥ 4.5V, ISINK = 3.2mA,
Reset asserted 0.4 V
Output Low Voltage (RST;
Push-pull Only)
VCC ≥ 2.7V, ISINK = 1.2mA,
Reset not asserted 0.3 V
VCC ≥ 4.5V, ISINK = 3.2mA,
Reset not asserted 0.4 V
VOH
Output High Voltage (RST)
VCC ≥ 2.7V, ISOURCE = 500µA,
Reset not asserted 0.8VCC V
VCC ≥ 4.5V, ISOURCE = 800µA
, Reset not asserted 0.8VCC V
Output High Voltage (RST)
VCC ≥ 1.0V, ISOURCE = 1µA,
Reset asserted (0°C to 85°C) 0.8VCC V
VCC ≥ 1.5V, ISOURCE = 100µA,
Reset asserted 0.8VCC V
VCC ≥ 2.55V, ISOURCE = 500µA,
Reset asserted 0.8VCC V
VCC ≥ 4.25V, ISOURCE = 800µA,
Reset asserted 0.8VCC V
STM6321/6322STM6821/6822/6823/6824/6825 DC and AC parameters
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Reset Thresholds
VRST(5) Reset Threshold
STM6xxxL 25°C 4.561 4.630 4.699 V
–40 to 85°C 4.514 4.746 V
STM6xxxM 25°C 4.314 4.390 4.446 V
–40 to 85°C 4.270 4.490 V
STM6xxxT 25°C 3.040 3.080 3.110 V
–40 to 85°C 3.000 3.150 V
STM6xxxS 25°C 2.890 2.930 2.960 V
–40 to 85°C 2.857 3.000 V
STM6xxxR 25°C 2.590 2.630 2.660 V
–40 to 85°C 2.564 2.696 V
STM6xxxZ (6) 25°C 2.280 2.320 2.350 V
–40 to 85°C 2.250 2.380 V
Reset Threshold Hysteresis L/M versions 10 mV
T/S/R/Z versions 5 mV
VCC to RST Delay
(VRST – VCC = 100mV, VCC
falling at 1mV/µs)
20 µs
trec (7) Reset Pulse Width
A11.42ms
Blank 140 200 280 ms
J 240 280 480 ms
Reset Threshold
Temperature Coefficient 40 ppm
/°C
Push-button Reset Input
tMLMH tMR MR Pulse Width 1 µs
tMLRL tMRD MR to RST Output Delay 500 ns
MR Glitch Immunity 100 ns
MR Pull-up Resistor 35 52 75 kΩ
Watchdog Timer
tWD (7) Watchdog Timeout Period 1.12 1.60 2.24 s
WDI Pulse Width 50 ns
1. Valid for Ambient Operating Temperature: TA = –40 to 85°C; VCC = 4.5 to 5.5V for “L/M” versions; VCC = 2.7 to 3.6V for
“T/S/R” versions; and VCC = 2.1 to 2.75V for “Z” version (except where noted).
2. VCC (min) = 1.0V for TA = 0 to +85°C.
3. WDI input is designed to be driven by a three-state output device. To float WDI, the “high-impedance mode” of the output
device must have a maximum leakage current of 10µA and a maximum output capacitance of 200pF. The output device
must also be able to source and sink at least 200µA when active.
4. WDI is internally serviced within the watchdog period if WDI is left unconnected.
5. The leakage current measured on the RST pin is tested with the reset asserted (output high impedance).
6. Contact local sales office for availability.
7. Other trec and watchdog timings are offered. Minimum order quantities may apply. Contact local sales office for availability.
Sym Alter-
native Description Test Condition (1) Min Typ Max Unit
Package mechanical data STM6321/6322STM6821/6822/6823/6824/6825
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6 Package mechanical data
Figure 27. SOT23-5 – 5-lead small outline transistor package mechanical drawing
1. Drawing is not to scale.
Table 7. SOT23-5 – 5-lead small outline transistor package mechanical data
Symb
mm inches
Typ Min Max Typ Min Max
A 1.200 0.900 1.450 0.0472 0.0354 0.0571
A1 0.150 0.0059
A2 1.050 0.900 1.300 0.0413 0.0354 0.0512
B 0.400 0.350 0.500 0.0157 0.0138 0.0197
C 0.150 0.090 0.200 0.0059 0.0035 0.0079
D 2.900 2.800 3.000 0.1142 0.1102 0.1181
D1 1.900 0.0748
E 2.800 2.600 3.000 0.1102 0.1024 0.1181
e 0.950 0.0374
F 1.600 1.500 1.750 0.0630 0.0591 0.0689
K010010
L 0.350 0.100 0.600 0.0138 0.0039 0.0236
SOT23-5
CP
A
C
A2
A1
D1D
e
B
E
L
K
F
STM6321/6322STM6821/6822/6823/6824/6825 Part numbering
23/26
7 Part numbering
Table 8. Ordering information scheme
For other options, or for more information on any aspect of this device, please contact the
ST sales office nearest you.
Example: STM6xxx LWY6E
Device Type
STM6xxx
Reset Threshold Voltage
L: VRST = 4.514 to 4.746V
M: VRST = 4.270 to 4.490V
T: VRST = 3.000 to 3.150V
S: VRST = 2.850 to 3.000V
R: VRST = 2.564 to 2.696V
Z: VRST = 2.250 to 2.380V (1)
1. Contact local sales office for availability.
Reset Pulse Width (2)
2. Contact local sales office for availability. Other trec and watchdog timings are offered. Minimum order
quantities may apply. Contact local sales office for availability.
A: trec = 1 to 2ms
Blank: trec = 140 to 280ms
J: trec = 240 to 480ms
Package
WY = SOT23-5
Temperature range
6 = –40 to 85°C
Shipping method
E = ECOPACK Package, Tubes
F = ECOPACK Package, Tape & Reel
Part numbering STM6321/6322STM6821/6822/6823/6824/6825
24/26
Table 9. Marking description
Note: Where “x” = Assembly Work Week (A to Z), such that “A” = WW01-02, “B” = WW03-04, and
so forth.
Part number Reset threshold (V) Reset pulse width (ms) Topside marking
STM6321LWY6F 4.630 200 5AUx
STM6321MAWY6F 4.390 1.4 5CRx
STM6321MWY6F 4.390 200 5AVx
STM6321TWY6F 3.080 200 5AWx
STM6321SWY6F 2.930 200 5AXx
STM6321RWY6F 2.630 200 5AYx
STM6322LWY6F 4.630 200 5BAx
STM6322MWY6F 4.390 200 5BBx
STM6322TWY6F 3.080 200 5BCx
STM6322SWY6F 2.930 200 5BDx
STM6322RWY6F 2.630 200 5BEx
STM6821LWY6F 4.630 200 5BGx
STM6821MWY6F 4.390 200 5BHx
STM6821TWY6F 3.080 200 5BJx
STM6821SWY6F 2.930 200 5BKx
STM6821RWY6F 2.630 200 5BLx
STM6822LWY6F 4.630 200 5BNx
STM6822MWY6F 4.390 200 5BPx
STM6822TWY6F 3.080 200 5BQx
STM6822SWY6F 2.930 200 5BRx
STM6822RWY6F 2.630 200 5BSx
STM6823LWY6F 4.630 200 5BUx
STM6823MWY6F 4.390 200 5BVx
STM6823TJWY6F 3.080 280 5CMx
STM6823TWY6F 3.080 200 5BWx
STM6823SJWY6F 2.930 280 5CNx
STM6823SWY6F 2.930 200 5BXx
STM6823RJWY6F 2.630 280 5CPx
STM6823RWY6F 2.630 200 5BYx
STM6824LWY6F 4.630 200 5CAx
STM6824MWY6F 4.390 200 5CBx
STM6824TWY6F 3.080 200 5CCx
STM6824SWY6F 2.930 200 5CDx
STM6824RWY6F 2.630 200 5CEx
STM6825LWY6F 4.630 200 5CGx
STM6825MWY6F 4.390 200 5CHx
STM6825TWY6F 3.080 200 5CJx
STM6825SWY6F 2.930 200 5CKx
STM6825RWY6F 2.630 200 5CLx
STM6321/6322STM6821/6822/6823/6824/6825 Revision history
25/26
8 Revision history
Table 10. Document revision history
Date Revision Changes
August 25, 2004 1.0 First Draft
15-Dec-04 2.0 Update characteristics (Figure 15, 16, 17; Ta bl e 6 , and 8)
10-Mar-05 3.0 Document promoted to Datasheet status
17-Jun-05 4.0 Package marking update (Ta bl e 9 )
11-Apr-06 5 Update characteristics, Lead-free text, availability (Figure 3, 4, 5, 6,
7, 8, and 9; Ta b l e 1 , 6, 8, and 9)
11-Aug-2006 6 Update Summary description, Ta b l e 8 , and 9.
25-May-2007 7 Formatting changes, updated Ta b l e 9.
STM6321/6322STM6821/6822/6823/6824/6825
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