INTEGRATED CIRCUITS DATA SHEET TDA1312A; TDA1312AT Stereo continuous calibration DAC (CC-DAC) Preliminary specification File under Integrated Circuits, IC01 July 1993 Philips Semiconductors Preliminary specification Stereo continuous calibration DAC (CC-DAC) TDA1312A; TDA1312AT FEATURES GENERAL DESCRIPTION * 8 x oversampling (simultaneous input) possible The TDA1312A; 1312AT is a voltage driven D/A converter and is a device of a new generation of digital-to-analog converters which embodies the innovative technique of Continuous Calibration (CC). The largest bit-currents are repeatedly generated by one single current reference source. This duplication is based upon an internal charge storage principle having an accuracy insensitive to ageing, temperature matching and process variations. * Voltage output * Space saving package SO8 or DIL8 * Low power consumption * Wide dynamic range (16-bit resolution) * Continuous Calibration (CC) concept * Easy application: The TDA1312A; 1312AT is fabricated in a 1.0 m CMOS process and features an extremely low power dissipation, small package size and easy application. Furthermore, the accuracy of the intrinsic high coarse-current combined with the implemented symmetrical offset decoding method preclude zero-crossing distortion and ensures high quality audio reproduction. Therefore, the CC-DAC is eminently suitable for use in (portable) digital audio equipment. - single 4 to 5.5 V rail supply - output current and bias current are proportional to the supply voltage - integrated current-to-voltage converter * Internal bias current ensures maximum dynamic range * Wide operating temperature range (-40 C to + 85 C) * Compatible with most current Japanese input formats: time multiplexed, two's complement and TTL * No zero-crossing distortion * Cost efficient. ORDERING INFORMATION PACKAGE EXTENDED TYPE NUMBER PINS PIN POSITION MATERIAL CODE TDA1312A(1) 8 DIL plastic SOT97DE TDA1312AT(2) 8 SO8 plastic SOT96AG Notes 1. SOT97-1; 1996 August 14. 2. SOT96-1; 1996 August 14. July 1993 2 Philips Semiconductors Preliminary specification Stereo continuous calibration DAC (CC-DAC) TDA1312A; TDA1312AT QUICK REFERENCE DATA SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT VDD supply voltage 4 5 5.5 V IDD supply current VDD = 5 V; at code 0000H - 3.4 6.0 mA VFS full scale output voltage VDD = 5 V 1.8 2.0 2.2 V (THD+N)/S total harmonic distortion plus at 0 dB signal level noise - -68 -63 dB - 0.04 0.07 % - -30 -24 dB - 3 6 % at -60 dB signal level; A-weighted - -33 - dB - 2 - % A-weighted; at code 0000H 86 92 - dB at -60 dB signal level S/N signal-to-noise ratio at bipolar zero tCS current settling time to 1 LSB - 0.2 - s BR input bit rate at data input - - 18.4 Mbits/s fBCK clock frequency at clock input - - 18.4 MHz TCFS full scale temperature coefficient at analog outputs (IOL; IOR) - 400 - ppm Tamb operating ambient temperature -40 - +85 C Ptot total power dissipation - 17 30 mW July 1993 VDD = 5 V; at code 0000H 3 This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... 6 RIGHT INPUT REGISTER LEFT OUTPUT REGISTER RIGHT OUTPUT REGISTER LEFT BIT SWITCHES RIGHT BIT SWITCHES 7 I/V I/V IOL IOR 11-BIT PASSIVE DIVIDER 4 BCK DATAR DATAL 32 (5-BIT) CALIBRATED CURRENT SOURCES 1 CALIBRATED SPARE SOURCE 1 CALIBRATED SPARE SOURCE 3 8 11-BIT PASSIVE DIVIDER REFERENCE SOURCE CONTROL AND TIMING TDA1312A TDA1312AT 5 VDD 4 C2 GND MGE225 Preliminary specification Fig.1 Block diagram. 100 nF TDA1312A; TDA1312AT WS 32 (5-BIT) CALIBRATED CURRENT SOURCES 1 2 VOR Philips Semiconductors VOL LEFT INPUT REGISTER Stereo continuous calibration DAC (CC-DAC) July 1993 handbook, full pagewidth Philips Semiconductors Preliminary specification Stereo continuous calibration DAC (CC-DAC) TDA1312A; TDA1312AT PINNING SYMBOL PIN DESCRIPTION BCK 1 bit clock input DATAR 2 right data input DATAL 3 GND handbook, halfpage BCK 1 8 WS left data input DATAR 2 7 VOR 4 ground DATAL VDD 5 positive supply voltage VOL 6 left channel output VOR 7 right channel output WS 8 word select input GND VOL 4 VDD 5 MGE224 Fig.2 Pin configuration. connected to an 11-bit binary current divider consisting of 2048 transistors. A symmetrical offset decoding principle is incorporated and arranges the bit switching in such a way that the zero-crossing is performed only by switching the LSB currents. FUNCTIONAL DESCRIPTION The basic operation of the continuous calibration DAC is illustrated in Fig.3. The figure shows the calibration and operation cycle. During calibration of the MOS current source (Fig.3a) transistor M1 is connected as a diode by applying a reference current. The voltage Vgs on the intrinsic gate-source capacitance Cgs of M1 is then determined by the transistor characteristics. After calibration of the drain current to the reference value Iref, the switch S1 is opened and S2 is switched to the other position (Fig.3b). The gate-to-source voltage Vgs of M1 is not changed because the charge on Cgs is preserved. Therefore, the drain current of M1 will still be equal to IREF and this exact duplicate of IREF is now available at the OUT terminal. The TDA1312A; AT (CC-DAC) accepts serial input data formats of 16-bit word length. Left and right data words are time multiplexed. The most significant bit (bit 1) must always be first. The input data format is shown in Figs.4 and 5. Data is placed in the right and left input registers (see Fig.1). The data in the input registers is simultaneously latched in the output registers which control the bit switches. An internal offset voltage VOFF is added to the full scale output voltage VFS; VOFF and VFS are proportional to VDD: Where VDD1/VDD2 = VFS1/VFS2 = VOFF1/VOFF2. The 32 current sources and the spare current source of the TDA1312A; AT are continuously calibrated (see Fig.1). The spare current source is included to allow continuous converter operation. The output of one calibrated source is July 1993 TDA1312 3 TDA1312AT 6 5 Philips Semiconductors Preliminary specification Stereo continuous calibration DAC (CC-DAC) TDA1312A; TDA1312AT OUT handbook, halfpage OUT IREF IREF IREF S2 S2 S1 S1 + Cgs M1 + Cgs Vgs (a) M1 Vgs (b) MGE226 Fig.3 Calibration principle; (a) calibration (b) operation. LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134). SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT VDD supply voltage - 6.0 Tstg storage temperature -55 +150 C TXTAL maximum crystal temperature - +150 C Tamb operating ambient temperature -40 +85 C Ves electrostatic handling note 1 -2000 +2000 V note 2 -200 +200 V V Notes 1. Human body model: C = 100 pF; R = 1500 ; 3 zaps positive and negative. 2. Machine model: C = 200 pF; L = 0.5 H; R = 10 ; 3 zaps positive and negative. THERMAL RESISTANCE SYMBOL Rth j-a July 1993 PARAMETER THERMAL RESISTANCE from junction to ambient in free air DIL8 100 K/W SO8 210 K/W 6 Philips Semiconductors Preliminary specification Stereo continuous calibration DAC (CC-DAC) TDA1312A; TDA1312AT CHARACTERISTICS VDD = 5 V; Tamb = 25 C; measured in Fig.1; unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT Supply VDD positive supply voltage IDD supply current 4.0 5.0 5.5 V at code 0000H - 3.4 6.0 mA Digital inputs; pins WS, BCK and DATA IIL input leakage current LOW VI = 0 V - - 10 A IIH input leakage current HIGH VI = 5 V - - 10 A fBCK clock frequency - - 18.4 MHz BR bit rate data input - - 18.4 Mbits/s fWS word select input frequency - - 384 kHz Timing (see Fig.4) tr rise time - - 12 ns tf fall time - - 12 ns tCY bit clock cycle time 54 - - ns tBCKH bit clock pulse width HIGH 15 - - ns tBCKL bit clock pulse width LOW 15 - - ns tSU;DAT data set-up time 12 - - ns tHD:DAT data hold time to bit clock 2 - - ns tHD:WS word select hold time 2 - - ns tSU;WS word select set-up time 12 - - ns Analog outputs; pins VOL and VOR VFS full-scale voltage 1.8 2.0 2.2 V TCFS full-scale temperature coefficient - 400 - ppm VOFF offset voltage at code 1000H 0.42 0.47 0.52 V (THD+N)/S total harmonic distortion plus noise at 0 dB signal level; note 1 - -68 -63 dB - 0.04 0.07 % at -60 dB signal level; - note 1 - -30 -24 dB 3 6 % at -60 dB signal level; - A-weighted; note1 - -33 - dB 2 - % - -65 -61 dB - 0.05 0.09 % at 0 dB signal level; f = 20 Hz to 20 kHz July 1993 7 Philips Semiconductors Preliminary specification Stereo continuous calibration DAC (CC-DAC) SYMBOL TDA1312A; TDA1312AT PARAMETER CONDITIONS MIN. TYP. MAX. UNIT Analog outputs; pins VOL and VOR current settling time to 1 LSB tcs - channel separation IO unbalance between outputs td time delay between outputs S/N signal-to-noise ratio at bipolar zero note 1 A-weighted; at code 0000H 0.2 - s 75 80 - dB - 0.2 0.3 dB - 0.2 - s 86 92 - dB Note 1. Measured with 1 kHz sinewave generated at sampling rate of 192 kHz. LEFT handbook, full pagewidth WS RIGHT tr <12 tBCKH >15 tf <12 tHD; WS >2 tBCKL >15 >12 tSU; WS BCK tCY >54 DATAR DATAL tSU; DAT >12 tHD; DAT >2 MSB LSB MGE227 SAMPLE OUT Fig.4 Input signals timing. July 1993 8 This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... Philips Semiconductors Stereo continuous calibration DAC (CC-DAC) handbook, full pagewidth July 1993 DATAR DATAL LSB MSB BCK 9 WS MGE228 SAMPLE OUT Preliminary specification TDA1312A; TDA1312AT Fig.5 Input signals format. Philips Semiconductors Preliminary specification Stereo continuous calibration DAC (CC-DAC) TDA1312A; TDA1312AT PACKAGE OUTLINES DIP8: plastic dual in-line package; 8 leads (300 mil) SOT97-1 ME seating plane D A2 A A1 L c Z w M b1 e (e 1) b MH b2 5 8 pin 1 index E 1 4 0 5 10 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 min. A2 max. b b1 b2 c D (1) E (1) e e1 L ME MH w Z (1) max. mm 4.2 0.51 3.2 1.73 1.14 0.53 0.38 1.07 0.89 0.36 0.23 9.8 9.2 6.48 6.20 2.54 7.62 3.60 3.05 8.25 7.80 10.0 8.3 0.254 1.15 inches 0.17 0.020 0.13 0.068 0.045 0.021 0.015 0.042 0.035 0.014 0.009 0.39 0.36 0.26 0.24 0.10 0.30 0.14 0.12 0.32 0.31 0.39 0.33 0.01 0.045 Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC SOT97-1 050G01 MO-001AN July 1993 EIAJ EUROPEAN PROJECTION ISSUE DATE 92-11-17 95-02-04 10 Philips Semiconductors Preliminary specification Stereo continuous calibration DAC (CC-DAC) TDA1312A; TDA1312AT SO8: plastic small outline package; 8 leads; body width 3.9 mm SOT96-1 D E A X c y HE v M A Z 5 8 Q A2 A (A 3) A1 pin 1 index Lp L 4 1 e detail X w M bp 0 2.5 5 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (2) e HE L Lp Q v w y Z (1) mm 1.75 0.25 0.10 1.45 1.25 0.25 0.49 0.36 0.25 0.19 5.0 4.8 4.0 3.8 1.27 6.2 5.8 1.05 1.0 0.4 0.7 0.6 0.25 0.25 0.1 0.7 0.3 0.01 0.019 0.0100 0.014 0.0075 0.20 0.19 0.16 0.15 0.244 0.039 0.028 0.050 0.041 0.228 0.016 0.024 inches 0.010 0.057 0.069 0.004 0.049 0.01 0.01 0.028 0.004 0.012 Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic or metal protrusions of 0.25 mm maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC SOT96-1 076E03S MS-012AA July 1993 EIAJ EUROPEAN PROJECTION ISSUE DATE 95-02-04 97-05-22 11 o 8 0o Philips Semiconductors Preliminary specification Stereo continuous calibration DAC (CC-DAC) TDA1312A; TDA1312AT Several techniques exist for reflowing; for example, thermal conduction by heated belt. Dwell times vary between 50 and 300 seconds depending on heating method. Typical reflow temperatures range from 215 to 250 C. SOLDERING Introduction There is no soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. However, wave soldering is not always suitable for surface mounted ICs, or for printed-circuits with high population densities. In these situations reflow soldering is often used. Preheating is necessary to dry the paste and evaporate the binding agent. Preheating duration: 45 minutes at 45 C. WAVE SOLDERING This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our "IC Package Databook" (order code 9398 652 90011). Wave soldering techniques can be used for all SO packages if the following conditions are observed: * A double-wave (a turbulent wave with high upward pressure followed by a smooth laminar wave) soldering technique should be used. DIP SOLDERING BY DIPPING OR BY WAVE * The longitudinal axis of the package footprint must be parallel to the solder flow. The maximum permissible temperature of the solder is 260 C; solder at this temperature must not be in contact with the joint for more than 5 seconds. The total contact time of successive solder waves must not exceed 5 seconds. * The package footprint must incorporate solder thieves at the downstream end. During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. The device may be mounted up to the seating plane, but the temperature of the plastic body must not exceed the specified maximum storage temperature (Tstg max). If the printed-circuit board has been pre-heated, forced cooling may be necessary immediately after soldering to keep the temperature within the permissible limit. Maximum permissible solder temperature is 260 C, and maximum duration of package immersion in solder is 10 seconds, if cooled to less than 150 C within 6 seconds. Typical dwell time is 4 seconds at 250 C. REPAIRING SOLDERED JOINTS A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. Apply a low voltage soldering iron (less than 24 V) to the lead(s) of the package, below the seating plane or not more than 2 mm above it. If the temperature of the soldering iron bit is less than 300 C it may remain in contact for up to 10 seconds. If the bit temperature is between 300 and 400 C, contact may be up to 5 seconds. REPAIRING SOLDERED JOINTS Fix the component by first soldering two diagonallyopposite end leads. Use only a low voltage soldering iron (less than 24 V) applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 C. SO REFLOW SOLDERING Reflow soldering techniques are suitable for all SO packages. Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. July 1993 12 Philips Semiconductors Preliminary specification Stereo continuous calibration DAC (CC-DAC) TDA1312A; TDA1312AT DEFINITIONS Data sheet status Objective specification This data sheet contains target or goal specifications for product development. Preliminary specification This data sheet contains preliminary data; supplementary data may be published later. Product specification This data sheet contains final product specifications. Limiting values Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. July 1993 13