YA19 2.5 Gb/s 16:1 Multiplexer and ClockGenerator Data Sheet Features Meets or exceeds all relevant ANSI, ITU and Bellcore specifications LVPECL 100 k inputs accept signals of 155 Mb/s data rate Differential data outputs provide CML signals at 2.5 Gb/s with 3.3 V or 5 V interface capability Internally synthesized 2.5 GHz clock removes the need for external high speed reference The Nortel Networks YA19 Multiplexer and Clock Generator multiplexes 16-bit parallel input data at 155 Mb/s into a single, serial output stream at 2.5 Gb/s. An on-chip phase locked loop generates a 2.5 GHz clock from either the incoming 155MHz data clock or from an external stable reference. The CML outputs of the YA19 are configured to interface directly with the Nortel Networks YA08 Laser Diode Driver. The YA19 is part of our family of 2.5 Gb/s components, which provides for power and chip-count savings that translate into better utilization of board real-estate and ultimately cost savings to the designer of fibre-based datacom or telecom solutions. The device is fabricated using a high yield, silicon bipolar process. Each product is available in industry-standard packaging or as flip chip, for high density modules. Single 3.3 V supply for simplified system integration YA19 Typical power dissipation of less than 1 W Manufactured using the high performance, high yield bipolar process Data 155 Mb/s 155 MHz Laser Diode Driver 2 16:1 Mux & Clk Gen Laser Diode 2.5 Gb/s Clk YA20 YA18 16 155 Mb/s 2 155 MHz 2 Data 1:16 Demux Clk AC10 Data 2.5 Gb/s 2 Clock & Data Recovery 2 AGC Post Amplifier AB89 2 Tz AMP Overhead Processor Industry standard LQFP package or high-density flip-chip for module applications YA08 16 PIN Clk 2.5 GHz Figure 1: System Block Diagram Receiver Module Functional Description The YA19 multiplexes 16-bit parallel input data at 155 Mb/s into a single serial output data stream at 2.5 Gb/s. For normal operation the device takes the input data clock at 155 MHz and generates a synchronous 2.5 GHz clock using an on-chip PLL. The device requires a single 3.3 V (5%) power supply. The CML data outputs can deliver levels suitable for input to a 3.3 V or 5 V device. In the latter case a +5 V (10%) supply is also required. System Inputs The 16-bit data bus on pins TXD_IN0-15 uses single-ended 100 k LVPECL inputs while the 155 MHz clock on pins CK155_INP/N uses similar differential inputs. These inputs do not include on-chip termination. 2 The 16 data inputs are clocked into the device on the falling edge of CK155_INP during the time window when the transmit bus is guaranteed to be stable. System Outputs The multiplexed data is output at 2.5 Gb/s on pins TXD_OUTP/N which are differential CML designed to drive 50 ohm. These output pins are provided with a local supply rail connected to pin VCC_OUT, which can be connected to VCC for 3.3 V compatible output levels, or can be connected to a separate 5 V supply if 5 V compatible output levels are required. Data bits are mapped onto the serial output stream in conventional order, with bit0 transmitted before bit1, etc. YA19 2.5 Gb/s 16:1 Multiplexer and Clock Generator Loss of Lock (LOL) Output A Loss Of Lock output, LOL, is generated from the raw frequency detector output of the VCO. It is asserted each time a cycle slip is observed by the frequency detector. LOL is a single ended opencollector output which requires external pulse stretching circuitry and is LOW if either loop is out of lock. Test Inputs and Outputs To enable testing at low speeds, various test inputs are made available. These inputs, which are not internally terminated, bypass the on-chip VCO. Under normal operation test input TEST_R must be connected to GND and inputs TEST_DIS and TEST_CK connected to VCC. A divider is included to divide the 2.5 GHz VCO output down to 155 MHz, which is delivered as a single-ended PECL output at pin CK155_OUT. Under normal operation this output should be left unconnected. TXD_IN15 VC C _ O U T INPUT REGISTER PISO REGISTER T X D _O U T P TXD_IN015 E S_ D IS A B L E T X D _O U T N B U F FE R READ CLOCK WRITE CLOCK LO A D 2 .5 G H z V C O C LO C K T E ST _ R C K 1 55_ IN P VCXO PHASE/ FREQUENCY DETECTOR T EST _D IS T E ST _ C K 2.5 GHz PHASE LOCKED LOOP LO L C K 1 55 _O U T C K 1 55_ IN N REFCK_INP/N P F D _O U T P/N 155 MHz VCXO OFF-CHIP LOOP COMPONENTS Figure 2: Functional Block Diagram Absolute Maximum Ratings These are stress ratings only: Exposure to stresses beyond these maximum ratings may cause permanent damage to, or affect the reliability of, the device. Avoid operating the device outside the recommended operating conditions defined below. Symbol Parameter Min Max Unit VCC Supply voltage - any VCC/VCC_OUT pin -1.0 6.0 V VIpecl LVPECL single ended input voltage 0 VCC+0.5 V IO Output current - LVPECL or CML -50 mA VOOC Open collector output voltage - LOL output -0.5 VCC+0.5 V Tstg Storage temperature -65 135 C Recommended Operating Conditions Symbol Parameter Min Typ Max Unit VCC Supply voltage - any VCC pin 3.14 3.3 3.46 V VCC_OUT Supply voltage for data outputs 3.14 5.50 V Vripple VCC supply noise and ripple -25 25 mV VIHPECL LVPECL INPUT HIGH VOLTAGE VCC-1.165 VCC-0.88 V VILPECL LVPECL INPUT LOW VOLTAGE VCC-2.100 VCC-1.475 V 0.1 UI rms 85 C Maximum input jitter on CK155_INP/N input (1) Tamb Ambient operating temperature -40 YA19 2.5 Gb/s 16:1 Multiplexer and Clock Generator 3 DC Electrical Characteristics Over recommended operating conditions, output load 50 ohm, VX =VCC_OUT for CML outputs. Symbol Parameter IIHpecl Min Typ Max Unit Input HIGH current - PECL input (VIH=VCC-0.88V) 100 A IILpecl Input LOW current - PECL input (VIL=VCC-1.81V) 50 A VOdiff CML differential output voltage (peak value) VOHcml 375 400 425 mV CML output HIGH voltage, referenced to VCC_OUT VX-0.01 VX VX+0.01 V VOLcml CML output LOW voltage, referenced to VCC_OUT VX-0.42 VX-0.40 VX-0.38 VOHpecl Output HIGH voltage - PECL output VCC -1.065 VCC -0.88 V VOLpecl Output LOW voltage - PECL output VCC -1.81 VCC - 1.62 V VOHLOL Output HIGH voltage - Loss of Lock output VCC -0.2 VCC V VOLLOL Output LOW voltage - Loss of Lock output VCC - 1.1 V Icc Supply Current (VCC and VCC_OUT) 250 375 mA Pd Device power dissipation 0.825 1.3 W Max Unit 2.5 GHz loop acquisition time 10 ms 155 Mhz VCXO loop acquisition time 10 s 0.0075 UI rms 0.1 dB AC Characteristics Over recommended operating conditions, output load 50 ohm. Symbol Parameter Min Jitter generated at TXD_OUTP/N outputs, bandwidth 12 kHz to 20 MHz Jitter gain from CK155_INP/N to TXD_OUTP/N at any frequency 4 TRcml Output rise time - CML output 50 125 ps TFcml Output fall time - CML output 50 125 ps TSUdi Data input SETUP time wrt CK155_INP falling edge 1.0 ns THdi Data input HOLD time wrt CK155_INP falling edge 1.0 ns YA19 2.5 Gb/s 16:1 Multiplexer and Clock Generator Design Procedure and Applications Information TXD_IN3 TXD_IN2 TXD_IN1 TXD_IN0 TXD_IN5 AMP_INN TXD_IN6 AMP_INP TXD_IN7 YA19 TXD_IN8 PD_OUTP TXD_IN9 FD_OUTN TXD_IN10 FD_OUTP TXD_IN11 TXD_IN14 TXD_IN inputs require external 50 ohm termination to VCC-2V TXD_IN TXD_IN15 CK155_INP DATA CLOCK_IN CK155_INN GND_CORE VCC_CORE TXD_IN13 ES_DISABLE CK155_OUT LOL REFCK_INP VCC_ECL2 TXD_IN12 REFCK_INN VCC_ELOL TXD_IN 3.14 to 5.5 V VCC_OUT TXD_OUT TXD_OUTP TXD_OUTN VCO_INP TEST_R (GND) LOSS OF LOCK VCC_ECL1 TXD_IN4 TEST_R 155 CLOCK OUT TX D_IN VCO_INN PD_OUTN CK155_OUT requires external 50 ohm termination to VCC-2V GND_CORE TEST_CK VCC_CORE VCC_VCO TEST_DIS TEST CLOCK (VCC) NOM) GND_VCO VCC (3.3 V TEST DISABLE (VCC) The application diagram in Figure 3 shows the configuration for usage of the YA19 in a 2.5 Gb/s OC-48/ STM-16 system. This shows required external components, including supply decoupling capacitors but not including the Loss of Lock circuitry defined in Figure 4. Figure 3: Typical Application Configuration YA19 2.5 Gb/s 16:1 Multiplexer and Clock Generator 5 Loss of Lock Output Characteristics VCC_ELOL A loss of lock signal is generated from the raw frequency detector output of the VCO loop and is asserted each time a cycle slip is observed by a frequency detector. It is a single ended CML output which requires the external circuitry shown in Figure 4 to pulse stretch the signal and generate an open collector output. LOL BFT93 BFR93 10 kohms 100 nF Figure 4: LOL External Pulse Stretching Circuit Power Supply Noise Although the device has been designed to maximize supply noise rejection, it is recommended that you use an LC filter network, shown in Figure 5, between the supply and pin 35 VCC_VCO. Using this configuration, the device will function within the jitter specification with a maximum supply noise of 50 mVpp, over a frequency range from 6 kHz to 2 MHz, on the supply. The effective series resistance of the network must not exceed 2.5 ohm. L=22H (2.5 ohm max.) Vsupply VCC_VCO C=100F YA19 Figure 5: Supply Filter Circuit PLL Performance The internally generated 2.5 GHz VCO clock signal is divided by 16 and then phase locked to the falling edge of the REFCK_INP input. The 2.5 Gb/s PLL is phase locked to the falling edge of C455 INP. 6 For the device to meet Bellcore specifications, it is necessary for the data clock to achieve phase noise of better than -90 dBc/Hz at a frequency offset of 1 kHz. YA19 2.5 Gb/s 16:1 Multiplexer and Clock Generator Setting the Loop Filter The YA19 is designed for regenerator and receiver applications. Its integrated PLL is a fully differential design with loop bandwidth set by a pair of identical external networks. The configuration of these networks is shown in Figure 6 with typical component values listed in Table 1. These components should be surface mount parts of 0603 size, with 2% tolerance for resistors up to 2 Mohm, 5% tolerance for capacitors up to 10 nF, and 10% tolerance for capacitors from 10 nF to 100 nF. The transistors are BFT93 or equivalent. 1M R2A 1M R1A C2 R 2B R3A C1A C1B 4 3 2 1 ( A 4) ( B 4) ( A 3) ( B 3) AM P _ IN P ( A 2 ) AMP _ INN ( B 2) _ IN P ( B1 ) VCO _ INN ( A 1) _ VCO 48 VCC 5 VCO 6 PD _ OUTN 7 PD _ O UTP 8 FD _ O UTN 9 FD _ O UTP 10 R1B R 3B 47 Figure 6: Loop Filter Configuration The table below defines a set of values for the loop filter components for a given bandwidth and damping factor. Alternative values can be determined by using the standard PLL performance equations. Loop bandwidth 2000 kHz Damping factor C1 C2 R1 R2 R3 5 1 nF 2 pF 8.2 Kohm 3.3 Kohm 3.3 Kohm Table 1: Typical Loop Filter Component Values Output Interfacing As with other members of the OC-48/STM-16 electro-optic interface family, the high speed (2.5 Gb/s) output of the YA19 is configured as a fully differential CML signal pair as shown in Figure 7. Although the YA19 is specifically designed to interface with the Nortel Networks YA08 Laser Diode Driver by providing a nominal peak differential output voltage of 400 mV, the outputs are such that it is CML OUTPUT (YA19) possible to drive a wide range of similar CML inputs. If you need to drive a single-ended input, you must AC couple the unused output to a 50 ohm termination. OP CML INPUT (YA18) VCC_OUT TXIVCC 380 mV(min) 420 mV(max) VCC OPB 50 50 50 50 R R OP OPB 760 mVp-p(min) 840 mVp-p(max) IP OP-OPB IPB R R Figure 8: CML Output Differential Voltage Levels GND GND Figure 7: CML Input and Output Configurations YA19 2.5 Gb/s 16:1 Multiplexer and Clock Generator 7 Pin Assignment Pin No Symbol Type 1 VCC_VCO P 2 VCO_INN I Analog Loop filter pin A1 3 VCO_INP I Analog Loop filter pin B1 4 AMP_INN I Analog Loop filter pin B2 5 AMP_INP I Analog Loop filter pin A2 6 PD_OUTN O Analog Loop filter pin B3 7 PD_OUTP O Analog Loop filter pin A3 8 FD_OUTN O Analog Loop filter pin B4 9 FD_OUTP O Analog Loop filter pin A4 10 VCC_ELOL P 11 CK155_OUT O PECL 100 k 12 LOL O CML 13 TEST_R I LVCMOS 14 REFCK_INN I PECL 100 k 155 MHz reference clock negative differential input 15 REFCK_INP I PECL 100 k 155 MHz reference clock positive differential input 17, 45 VCC_CORE P 3.3 V supply rail for digital core 18, 44 GND_CORE P Supply ground for digital core 21 CK155_INN I PECL 100 k 155 MHz data clock negative differential input 22 CK155_INP I PECL 100 k 155 MHz data clock positive differential input I PECL 100 k Parallel data input, bit 15, LSB to bit 0, MSB 23, 24, 25, 26, 28, 29, TXD_IN15 to 30, 31, 32, 33, 34, 35, TXD_IN0 37, 38, 39, 40 8 YA19 2.5 Gb/s 16:1 Multiplexer and Clock Generator Description Function 3.3 V supply rail for VCO 3.3 V supply rail for PECL output and LOL VCO divided clock output PLL loss of lock output Test reset input (connect to GND for normal operation) Pin Assignment (continued) Pin No Symbol Type Description Function 27 VCC_ECL2 P 3.3 V supply pin for PECL inputs <8:15> 36 VCC_ECL1 P 3.3 V supply pin for PECL inputs <0:7> 41 VCC_OUT P 3.3 V or 5 V supply pin for CML data output 42 TXD_OUTN O CML Serial data negative differential output 43 TXD_OUTP O CML Serial data positive differential output 46 TEST_DIS I LVCMOS 47 TEST_CK I PECL 100 k 48 GND_VCO P Test disable input (connect to VCC for normal operation) Test clock input (connect to VCC for normal operation) Supply ground for VCO Package Pin Configuration 48 47 46 45 44 43 42 41 40 39 38 37 GND_VCO TEST_CK TEST_DIS VCC_CORE GND_CORE TXD_OUTP TXD_OUTN VCC_OUT TXD_IN0 TXD_IN1 TXD_IN2 TXD_IN3 The device is packaged in a 48-lead plastic low-profile quad flat pack (LQFP). To achieve the required thermal resistance, the package contains a heat slug which must be soldered directly to the circuit board. 1 2 3 4 5 6 7 8 9 10 11 12 36 35 34 33 32 31 30 29 28 27 26 25 YA19 13 14 15 16 17 18 21 22 23 24 CK155_INN CK155_INP TXD_IN15 TXD_IN14 TOP VIEW TEST_R REFCK_INN REFCK_INP ES_DISABLE VCC_CORE GND_CORE VCC_VCO VCO_INN VCO_INP AMP_INN AMP_INP PD_OUTN PD_OUTP FD_OUTN FD_OUTP VCC_ELOL CK155_OUT LOL VCC_ECL1 TXD_IN4 TXD_IN5 TXD_IN6 TXD_IN7 TXD_IN8 TXD_IN9 TXD_IN10 TXD_IN11 VCC_ECL2 TXD_IN12 TXD_IN13 Figure 9: 48-lead LQFP YA19 2.5 Gb/s 16:1 Multiplexer and Clock Generator 9 Package Outline and Dimensions D D1 A A2 C Exposed Heatsink: 4.32 mm +/- 0.12 mm diam Intrusion: 0.0127 mm On underside of package. B E A1 Figure 10: Package Outline Min (mm) Nom (mm) Lead pitch (E) 0.50 Body size (D1) 7.00 Component tip-to-tip (D) 9.00 Component height (A) 10 Max (mm) 1.60 Component standoff (A1) 0.05 Body thickness (A2) 1.35 1.40 1.45 Lead width, plated (B) 0.17 0.22 0.27 Lead thickness, plated (C) 0.09 YA19 2.5 Gb/s 16:1 Multiplexer and Clock Generator 0.15 0.20 Notes: YA19 2.5 Gb/s 16:1 Multiplexer and Clock Generator 11 Ordering information Please quote the Product Code from Table 2 below when ordering as this is the identification that appears on the part when shipped. Table 2: Product ordering information Product Code Product Name A0742167 (QMV1051-1AF5) YA19 2.5 Gb/s 16:1 Multiplexer and Clock Generator For additional information on Nortel Networks products and services offered, please contact your local representative. Nortel Networks High Performance Optical Component Solutions attn: Marketing Department 2745 Iris Street 6th Floor Ottawa, Ontario Canada K2C 3V5 Copyright 2001 Nortel Networks Corporation. All rights reserved. Nortel, Nortel Networks, the Nortel Networks corporate logo, and the globemark design are trademarks of Nortel Networks Corporation. Any third-party trademarks are the property of their respective owners. The information contained in this document is considered to be accurate as of the date of publication. No liability is assumed by Nortel Networks for use of any information contained in this document, or for infringement of any patent rights or any other proprietary rights of third parties which may result from such use. No license is granted by implication or otherwise under any patent right or any other proprietary right of Nortel Networks. Tel: 1-800-4 NORTEL Fax: 1-613-763-8416 Email: opticalcomponents@nortelnetworks.com www.nortelnetworks.com/hpocs Publication # 84001.37/03-01 Issue 2 Issued: 5 March 2001