The 16 data inputs are clocked into the
device on the falling edge of CK155_INP
during the time window when the
transmit bus is guaranteed to be stable.
System Outputs
The multiplexed data is output at
2.5 Gb/s on pins TXD_OUTP/N which
are differential CML designed to drive
50 ohm. These output pins are provided
with a local supply rail connected to pin
VCC_OUT, which can be connected to
VCC for 3.3 V compatible output levels,
or can be connected to a separate 5 V
supply if 5 V compatible output levels are
required. Data bits are mapped onto the
serial output stream in conventional order,
with bit0 transmitted before bit1, etc.
Loss of Lock (LOL) Output
A Loss Of Lock output, LOL, is generated
from the raw frequency detector output
of the VCO. It is asserted each time a
cycle slip is observed by the frequency
detector. LOL is a single ended open-
collector output which requires external
pulse stretching circuitry and is LOW if
either loop is out of lock.
Test Inputs and Outputs
To enable testing at low speeds, various
test inputs are made available. These
inputs, which are not internally
terminated, bypass the on-chip VCO.
Under normal operation test input
TEST_R must be connected to GND and
inputs TEST_DIS and TEST_CK
connected to VCC.
A divider is included to divide the
2.5 GHz VCO output down to
155 MHz, which is delivered as a
single-ended PECL output at pin
CK155_OUT. Under normal operation
this output should be left unconnected.
YA19 2.5 Gb/s 16:1 Multiplexer and Clock Generator
2
Functional Description
The YA19 multiplexes 16-bit parallel
input data at 155 Mb/s into a single serial
output data stream at 2.5 Gb/s. For
normal operation the device takes the
input data clock at 155 MHz and
generates a synchronous 2.5 GHz clock
using an on-chip PLL.
The device requires a single 3.3 V (±5%)
power supply. The CML data outputs can
deliver levels suitable for input to a 3.3 V
or 5 V device. In the latter case a +5 V
(±10%) supply is also required.
System Inputs
The 16-bit data bus on pins TXD_IN0-15
uses single-ended 100 k LVPECL inputs
while the 155 MHz clock on pins
CK155_INP/N uses similar differential
inputs. These inputs do not include
on-chip termination.