DIVIDER
DIVIDER
SDA/SCL
VCO
PLL
Differential
LVDSInput
30MHz 319MHz-
1Bypass
CMLOutput
5Differential
CMLOutputs
15MHz 1.25GHz-
5Differential
CMLOutputs
15MHz 1.25GHz-
CDCL6010
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SLLS780B –FEBRUARY 2007–REVISED MARCH 2011
1.8V, 11 Output Clock Multiplier, Distributor, Jitter Cleaner, and Buffer
Check for Samples: CDCL6010
1FEATURES •Integrated LC Oscillator Allows External
Bandwidth Adjustment
2•Single 1.8V Supply •PLL Lock Indication
•High-Performance Clock Multiplier, Distributor, •Power Consumption: 640mW Typical
Jitter Cleaner, and Buffer With 11 Outputs
•Output Enable Control for Each Output
•Low Output Jitter: 400fs RMS
•SDA/SCL Device Management Interface
•Output Group Phase Adjustment
•48-pin QFN (RGZ) Package
•Low-Voltage Differential Signaling (LVDS)
Input, 100ΩDifferential On-Chip Termination, •Industrial Temperature Range: –40°C to +85°C
30MHz to 319MHz Frequency Range APPLICATIONS
•Differential Current Mode Logic (CML)
Outputs, 50ΩSingle-Ended On-Chip •Low Jitter Clocking for High-Speed SERDES
Termination, 15MHz to 1.25GHz Frequency •Jitter Cleaning of SERDES Reference Clocks
Range for 1G/10G Ethernet, 1X/2X/4X/10X Fibre
•One Dedicated Differential CML Output, Channel, PCI Express, Serial ATA, SONET,
Straight PLL and Frequency Divider Bypass CPRI, OBSAI, etc.
•Two Groups of Five Outputs Each with •Up to 1-to-11 Clock Buffering and Fan-out
Independent Frequency Division Ratios;
Optional PLL Bypass
•Fully Integrated Voltage Controlled Oscillator
(VCO); Supports Wide Output Frequency
Range
•Output Frequency Derived From VCO
Frequency with Divide Ratios of 1, 2, 4, 5, 8,
10, 16, 20, 32, 40, and 80
•Meets OBSAI RP1 v1.0 Standard and
CPRI v2.0 Requirements
•Meets ANSI TIA/EIA-644-A-2001 LVDS
Standard Requirements
1Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date. Copyright ©2007–2011, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
CDCL6010
SLLS780B –FEBRUARY 2007–REVISED MARCH 2011
www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
DESCRIPTION
The CDCL6010 is a high-performance, low phase noise clock multiplier, distributor, jitter cleaner, and low skew
buffer. It effectively cleans a noisy system clock with a fully-integrated low noise Voltage Controlled Oscillator
(VCO) that operates in the 1.2GHz–1.275GHz range. (Note that the LC oscillator oscillates in the
2.4GHz–2.55GHz range. The frequency is predivided by 2 before the post-dividers P0 and P1.)
The output frequency (FOUT) is synchronized to the frequency of the input clock (FIN). The programmable
pre-dividers, M and N, and the post-dividers, P0 and P1, give a high flexibility to the ratio of the output frequency
to the input frequency:
FOUT = FIN ×N/(M ×P)
Where:
P (P0, P1) = 1, 2, 4, 5, 8, 10, 16, 20, 32, 40, 80
M=1,2,4,8
N = 32, 40
provided that:
30MHz <(FIN /M) <40MHz
1200MHz <(FOUT ×P) <1275MHz
The PLL loop bandwidth is user-selectable by external filter components or by using the internal loop filter. The
PLL loop bandwidth and damping factor can be adjusted to meet different system requirements.
The CDCL6010 supports one differential LVDS clock input and a total of 11 differential CML outputs. One output
is a straight bypass with no support for jitter cleaning or clock multiplication. The remaining 10 outputs are
available in two groups of five outputs each with independent frequency division ratios. Those 10 outputs can be
optionally setup to bypass the PLL when no jitter cleaning is needed. The CML outputs are compatible with
LVDS receivers if ac-coupled.
With careful observation of the input voltage swing and common-mode voltage limits, the CDCL6010 can support
a single-ended clock input as outlined in the Pin Description Table
The CDCL6010 can operate as a multi-output clock buffer in a PLL bypass mode.
All device settings are programmable through the SDA/SCL, serial two-wire interface.
The serial interface is 1.8V tolerant only.
The phase of one output group relative to the other can be adjusted through the SDA/SCL interface. For
post-divide ratios (P0, P1) that are multiples of 5, the total number of phase adjustment steps (n) equals the
divide-ratio divided by 5. For post-divide ratios (P0, P1) that are not multiples of 5, the total number of steps (n) is
the same as the post-divide ratio. The phase adjustment step (ΔΦ) in time units is given as:
ΔΦ = 1/(n ×FOUT)
where FOUT is the respective output frequency.
The device operates in a 1.8V supply environment and is characterized for operation from –40°C to +85°C.
The CDCL6010 is available in a 48-pin QFN (RGZ) package.
Table 1. AVAILABLE OPTIONS(1)
TAPACKAGED DEVICES FEATURES
–40°C to +85°C CDCL6010RGZT 48-pin QFN (RGZ) Package, small tape and reel
–40°C to +85°C CDCL6010RGZR 48-pin QFN (RGZ) Package, tape and reel
(1) For the most current specifications and package information, see the Package Option Addendum located at the end of this data sheet or
refer to our web site at www.ti.com.
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ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted).(1)
VALUE UNIT
VDD, AVDD Supply voltage(2) –0.3 to 2.5 V
VLVDS Voltage range at LVDS input pins(2) –0.3 to VDD + 0.6 V
VIVoltage range at all non-LVDS input pins(2) –0.3 to VDD + 0.6 V
ESD Electrostatic discharge (HBM) 2 kV
TJJunction temperature +125 °C
TSTG Storage temperature range –65 to +150 °C
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
condition is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to network ground terminal.
RECOMMENDED OPERATING CONDITIONS
Over operating free-air temperature range (unless otherwise noted). MIN NOM MAX UNIT
VDD Digital supply voltage 1.7 1.8 1.9 V
AVDD Analog supply voltage 1.7 1.8 1.9 V
TAAmbient temperature (no airflow, no heatsink) –40 +85 °C
TJJunction temperature +105 °C
THERMAL INFORMATION RGZ
THERMAL METRIC(1) UNITS
(48 Pins)
airflow = 0 lfm 28.3 °C/W
θJA Junction-to-ambient thermal resistance(2):airflow = 50 lfm 22.4 °C/W
θJC(TOP) Junction-to-case (top) thermal resistance 20.5 °C/W
θJC(BOTTOM) Junction-to-case (Bottom) thermal resistance 5.3 °C/W
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
(2) No heatsink; power uniformly distributed; 36 ground vias (6 x 6 array) tied to the thermal exposed pad; 4-layer high-K board.
DC ELECTRICAL CHARACTERISTICS
Over recommended operating conditions (unless otherwise noted).
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
All outputs enabled; VDD = VDD,typ
IVDD Total current from digital 1.8V supply 270 mA
30.72MHz input; 61.44MHz output
All outputs enabled; AVDD = VDD,typ
IAVDD Total current from analog 1.8V supply 85 mA
30.72MHz input; 61.44MHz output
VIL,CMOS Low level CMOS input voltage VDD = 1.8V –0.2 0.6 V
VIH,CMOS High level CMOS input voltage VDD = 1.8V VDD –0.6 VDD V
IIL,CMOS Low level CMOS input current VDD = VDD,max, VIL = 0.0V –120 μA
IIH,CMOS High level CMOS input current VDD = VDD,max, VIH = 1.9V 65 μA
VOL,SDA Low level CMOS output voltage for the Sink current = 3mA 0 0.2VDD V
SDA pin
IOL,CMOS Low level CMOS output current 8 mA
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AC ELECTRICAL CHARACTERISTICS
Over recommended operating conditions (unless otherwise noted).
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Differential input impedance for the LVDS input
ZD,IN 90 132 Ω
terminals
VCM,IN Common-mode voltage, LVDS input 1125 1200 1375 mV
VS,IN Single-ended LVDS input voltage swing 100 600 mVPP
VD,IN Differential LVDS input voltage swing 200 1200 mVPP
tR,OUT,Output signal rise/fall time 20%–80% 100 ps
tF,OUT
VCM,OUT Common-mode voltage, CML outputs VDD –0.31 VDD –0.23 VDD –0.19 V
VS,OUT Single-ended CML output voltage swing ac-coupled 180 230 280 mVPP
Measured in a 50Ωscope; The CML
VD,OUT Differential CML output voltage swing 360 460 560 mVPP
output incorporates 50Ωresistors to VDD
FIN Clock input frequency 30 319 MHz
FOUT Clock output frequency 15 1250 MHz
FIN = 30.72MHz , FOUT = 61.44MHz
LOUT Residual clock output phase noise 400kHz PLL bandwidth
at 10Hz offset –103 dBc/Hz
at 100Hz offset –114 dBc/Hz
at 1kHz offset –123 dBc/Hz
at 10kHz offset –121 dBc/Hz
at 100kHz offset –119 dBc/Hz
at 1MHz offset –138 dBc/Hz
at 10MHz offset –152 dBc/Hz
at 20MHz offset –152 dBc/Hz
FIN = 30.72MHz, FOUT = 61.44MHz
JOUT Residual clock output jitter 400kHz PLL bandwidth
10Hz–1MHz offset 2.01 ps RMS
1MHz–20MHz offset 0.45 ps RMS
12kHz–20MHz offset 2.11 ps RMS
FIN = 30.72MHz, FOUT = 30.72MHz
TPInput-to-output delay 3 ns
YP[9:0] outputs, PLL bypass mode
FIN = 30.72MHz, FOUT = 61.44MHz 150 ps
YP[9:0] outputs, PLL mode
FIN = 30.72MHz, FOUT = 61.44MHz
TSOUT Clock output skew –64 64 ps
YP[9:0] outputs relative to YP[0]
FIN = 122.88MHz, FOUT (Y0 to Y4) =
61.44MHz, 1.46 2.52 ns
FOUT (Y5 to Y9) = 122.88MHz
(Y0 to Y4) lag (Y5 to Y9)
DCycleOUT Clock output duty cycle(1) 45% 55%
(1) Output duty cycle of the bypass output and for post-divide ratio = 1 is just as good as the input duty cycle.
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SLLS780B –FEBRUARY 2007–REVISED MARCH 2011
AC ELECTRICAL CHARACTERISTICS FOR THE SDA/SCL INTERFACE(1)
PARAMETER MIN TYP MAX UNIT
fSCL SCL frequency 400 kHz
th(START) START hold time 0.6 μs
tw(SCLL) SCL low-pulse duration 1.3 μs
tw(SCLH) SCL high-pulse duration 0.6 μs
tsu(START) START setup time 0.6 μs
th(SDATA) SDA hold time 0 μs
tsu(DATA) SDA setup time 0.6 μs
tr(SDATA) SCL / SDA input rise time 0.3 μs
tf(SDATA) SCL / SDA input fall time 0.3 μs
tsu(STOP) STOP setup time 0.6 μs
tBUS Bus free time 1.3 μs
(1) See Figure 4 for the timing behavior.
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VCP
AVDD
CLKP
CLKN
AVDD
YP0
YN0
VDD
YP1
YN1
VDD
VSS
ADD0
VDD
YN7
YP7
VDD
YN6
YP6
VDD
YN5
YP5
VDD
SDA
1
2
3
4
5
6
7
8
9
10
13
16
19
22
11
14
17
20
23
12
15
18
21
24
36
35
34
33
32
31
30
29
28
27
26
25
CDCL6010
STATUS 48
45
42
39
47
44
41
38
46
43
40
37
VCN
YN9
YP10
YP8
AVDD
VDD
AVDD
VDD
YN10
YN8
YP9
ADD1
VDD
YP2
YN2
VDD
YP3
YN3
VDD
YP4
YN4
VDD
SCL
NOTE:Exposedthermalpadmustbesolderedto VSS.
CDCL6010
SLLS780B –FEBRUARY 2007–REVISED MARCH 2011
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DEVICE INFORMATION
48-PIN QFN (RGZ)
(TOP VIEW)
The CDCL6010 is available in a 48-pin QFN (RGZ) package with a pin pitch of 0,5mm. The exposed thermal pad
serves both thermal and electrical grounding purposes.
NOTE
The device must be soldered to ground (VSS) using as many ground vias as possible. The
device performance will be severely impacted if the exposed thermal pad is not grounded
appropriately.
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SLLS780B –FEBRUARY 2007–REVISED MARCH 2011
PIN FUNCTIONS
PIN
NAME PIN NO. TYPE DESCRIPTION
8, 11, 14,17,
20, 23, 26,
VDD Power 1.8V digital power supply.
29, 32, 35,
38, 41
AVDD 2, 5, 44, 47 Power 1.8V analog power supply.
Exposed
VSS thermal pad Power Ground reference.
and pin 12
VCP, VCN 1, 48 I External loop filter terminals.
Differential LVDS input. Single-ended 1.8V input can be dc-coupled to pin 3 with pin 4 either
CLKP, CLKN 3, 4 I tied to pin 3 (recommended) or left open.
YP0, YN0 6, 7
YP1, YN1 9, 10
YP2, YN2 15, 16
YP3, YN3 18, 19
YP4, YN4 21, 22 10 differential CML outputs with support for jitter cleaning and clock multiplication. Support
O
YP5, YN5 27, 28 optional PLL bypass mode when jitter cleaning is not needed.
YP6, YN6 30, 31
YP7, YN7 33, 34
YP8, YN8 40, 39
YP9, YN9 43, 42
YP10, YN10 46, 45 O Differential CML output. Straight bypass with no jitter cleaning and no clock multiplication.
SCL serial clock pin. Open drain. Always connect to a pull-up resistor. SCL tolerated 1.8V on
SCL 24 I the input only.
SDA bidirectional serial data pin. Open drain. Always connect to a pull-up resistor. SDA
SDA 25 I/O tolerates 1.8V on the input only
STATUS 13 O LVCMOS status signaling. High status indicates PLL lock.
Configurable least significant bits (ADD[1:0]) of the SDA/SCL device address. The fixed most
ADD1, ADD0 37, 36 I significant bits (ADD[6:2]) of the 7-bit device address are 11010.
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VDD
CLKN
CLKP
YN[4:0]
YP[4:0]
YN[9:5]
YP[9:5]
SDA/SCL
PLL Bypass
See Note 1
Post Divider Setting
PLL Setting
VCNVCP
STATUS
PLL_LOCK
Control
I
LPF
External Low-Pass Filter
AVDD
LVDS
CML
CML
YN10
YP10
R
C1
C2
SDA/SCL
Divider M
VSS
Control
CML
CML
CML
Divider N
PFD
CP
VCO
2¸
Internal
LPF
MUX
MUX
Divider
P1
Divider
P0
CDCL6010
SLLS780B –FEBRUARY 2007–REVISED MARCH 2011
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FUNCTIONAL BLOCK DIAGRAM
(1) Outputs can be disabled to floating. When outputs are left floating, internal 50Ωtermination to VDD pulls both YN and
YP to VDD.
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-250
-200
-150
-100
-50
0
50
100
150
200
250
0 0.5 1 1.5 2
t-Time-ns
DifferentialOutputVoltage-mV
-300
-200
-100
0
100
200
300
0 10 20 30 40 50
t-Time-ns
DifferentialOutputVoltage-mV
-160
-150
-140
-130
-120
-110
-100
-90
-80
10 100 1k
OffsetFrequency-Hz
PhaseNoise-dBc/Hz
10k 100k 1M 10M 100M
CDCL6010
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SLLS780B –FEBRUARY 2007–REVISED MARCH 2011
TYPICAL CHARACTERISTICS
Typical operating conditions are at VDD = 1.8V and TA= +25°C, VD,IN = 200mVPP (unless otherwise noted).
TRANSIENT PERFORMANCE: TRANSIENT PERFORMANCE:
FIN = 30.72MHz, FOUT = 61.44MHz FIN = 250MHz, FOUT = 1.25GHz
Figure 1. Figure 2.
PHASE NOISE: FIN = 30.72MHz, FOUT = 61.44MHz
Figure 3.
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SDA/SCL INTERFACE
This section describes the SDA/SCL interface of the The device address is made up of the fixed internal
CDCL6010 device. The CDCL6010 operates as a address, 11010 (A6:A2), and configurable external
slave device of the industry standard 2-pin SDA/SCL pins ADD1 (A1) and ADD0 (A0). Four different
bus. It operates in the fast-mode at a bit-rate of up to devices with addresses 1101000, 1101001, 1101010
400kbit/s and supports 7-bit addressing compatible and 1101011, can be addressed via the same
with the popular two-pin serial interface standard. SDA/SCL bus interface. The least significant bit of the
address byte designates a write or read operation.
SDA/SCL Bus Slave Device Address R/W Bit:
0 = Write to CDCL6010 device
A6 A5 A4 A3 A2 A1 A0 R/W 1 = Read from CDCL6010 device
1 1 0 1 0 ADD1 ADD0 0/1
Command Code Definition
BIT DESCRIPTION
C7 1 = Byte Write / Read or Word Write / Read operation
(C6:C0) Byte Offset for Byte Write / Read and Word Write / Read operation.
Command Code for Byte Write / Read Hex
Operation Code C7 C6 C5 C4 C3 C2 C1 C0
Byte 0 80h 1 0 0 0 0 0 0 0
Byte 1 81h 1 0 0 0 0 0 0 1
Byte 2 82h 1 0 0 0 0 0 1 0
Byte 3 83h 1 0 0 0 0 0 1 1
Byte 4 84h 1 0 0 0 0 1 0 0
Byte 5 85h 1 0 0 0 0 1 0 1
Byte 6 86h 1 0 0 0 0 1 1 0
Byte 7 87h 1 0 0 0 0 1 1 1
Command Code for Word Write / Read Hex
Operation Code C7 C6 C5 C4 C3 C2 C1 C0
Word 0: Byte 0 and byte 1 80h 1 0 0 0 0 0 0 0
Word 1: Byte 1 and byte 2 81h 1 0 0 0 0 0 0 1
Word 2: Byte 2 and byte 3 82h 1 0 0 0 0 0 1 0
Word 3: Byte 3 and byte 4 83h 1 0 0 0 0 0 1 1
Word 4: Byte 4 and byte 5 84h 1 0 0 0 0 1 0 0
Word 5: Byte 5 and byte 6 85h 1 0 0 0 0 1 0 1
Word 6: Byte 6 and byte 7 86h 1 0 0 0 0 1 1 0
Word 7: Byte 7 87h 1 0 0 0 0 1 1 1
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SCL
SDA
t(BUS)
tSU(SDATA) t(SDATA)h
tr(SM)
tr(SM)
tf(SM)
tf(SM)
tw(SCLH)
VIH(SM)
VIH(SM)
VIL(SM)
VIL(SM)
PSBit7(MSB) Bit0(LSB)
Bit6 A P
tSU(STOP)
t(START)h
tSU(START)
tw(SCLL)
1 7 1 1 81 1
S SlaveAddress DataByte
Wr A A P
S
Sr
Rd
Wr
A
N
P
Startcondition
Repeatedstartcondition
Read(bitvalue=1)
Write(bitvalue=0)
Acknowledge(bitvalue=0)
Notacknowledge(bitvalue=1)
Stopcondition
MastertoSlavetransmission
SlavetoMastertransmission
CDCL6010
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SLLS780B –FEBRUARY 2007–REVISED MARCH 2011
SDA/SCL Timing Characteristics
Figure 4. Timing Diagram for the SDA/SCL Serial Control Interface
SDA/SCL Programming Sequence
LEGEND FOR PROGRAMMING SEQUENCE
Byte Write Programming Sequence:
1 7 1 1 8 1 8 1 1
S Slave Address Wr A Command Code A Data Byte A P
Byte Read Programming Sequence:
1 7 1 1 8 1 1 7 1 1 8 1 1
Wr Command
S Slave Address A A S Slave Address Rd A Data Byte N P
Code
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Word Write Programming Sequence:
17118181811
S Slave Address Wr A Command Code A Data Byte Low A Data Byte High A P
Word Read Programming Sequence:
171181171181811
Slave Command Slave
S Wr A A S Rd A Data Byte A Data Byte N P
Address Code Address
SDA/SCL Connections Recommendations
The serial interface inputs don’t have glitch suppression circuit. So, any noises or glitches at serial input lines
may cause programming error. The serial interface lines should be routed in such a way that the lines would
have minimum noise impact from the surroundings.
Figure 5 is recommended to improve the interconnections.
Figure 5. Serial Interface Connections
Lower RPresistor value (around 1 kΩ) should be chosen so that signals will have faster rise time. A capacitor
can be connected to SCL line to ground which will act as a filter.
An I2C level translator will help to overcome the noises issue.
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SDA/SCL Bus Configuration Command Bitmap
Byte 0:
Power Up
Bit Bit Name Description/Function Type Condition Reference To
7 PLL-LOCK 1 if PLL has achieved lock, otherwise 0 R 0
6 MANF[6] Manufacturer reserved R
5 MANF[5] Manufacturer reserved R
4 MANF[4] Manufacturer reserved R
3 MANF[3] Manufacturer reserved R
2 MANF[2] Manufacturer reserved R
1 MANF[1] Manufacturer reserved R
0 MANF[0] Manufacturer reserved R
Byte 1:
Power Up
Bit Bit Name Description/Function Type Condition Reference To
7 RES Reserved R/W 0
6 RES Reserved R/W 0
5 ENPH Phase select enable R/W 1
4 PH1[4] Phase select for YP[9:5] and YN[9:5] R/W 0 Table 5,Table 6
3 PH1[3] Phase select for YP[9:5] and YN[9:5] R/W 0 Table 5,Table 6
2 PH1[2] Phase select for YP[9:5] and YN[9:5] R/W 0 Table 5,Table 6
1 PH1[1] Phase select for YP[9:5] and YN[9:5] R/W 0 Table 5,Table 6
0 PH1[0] Phase select for YP[9:5] and YN[9:5] R/W 0 Table 5,Table 6
Byte 2:
Power Up
Bit Bit Name Description/Function Type Condition Reference To
7 RES Reserved R/W 0
6 RES Reserved R/W 0
5 ENP1 Post-divider P1 enable; if 0 output YP[9:5] and YN[9:5] are disabled R/W 1
4 ENBP1 Bypass PLL for post-divider P1: If 1 input is CLKP/CLKN, if 0 input is PLL R/W 0
clock
3 SELP1[3] Divide ratio select for post-divider P1 R/W 0 Table 2
2 SELP1[2] Divide ratio select for post-divider P1 R/W 1 Table 2
1 SELP1[1] Divide ratio select for post-divider P1 R/W 1 Table 2
0 SELP1[0] Divide ratio select for post-divider P1 R/W 1 Table 2
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Byte 3:
Bit Power Up
Bit Name Description/Function Type Condition Reference To
7 RES Reserved R/W 0
6 RES Reserved R/W 0
5 PLLLOC PLL Lock Overwrite: If 1 output not gated by PLL Lock status. R/W 0
K OW
4 PH0[4] Phase select for YP[4:0] and YN[4:0] R/W 0 Table 5,Table 6
3 PH0[3] Phase select for YP[4:0] and YN[4:0] R/W 0 Table 5,Table 6
2 PH0[2] Phase select for YP[4:0] and YN[4:0] R/W 0 Table 5,Table 6
1 PH0[1] Phase select for YP[4:0] and YN[4:0] R/W 0 Table 5,Table 6
0 PH0[0] Phase select for YP[4:0] and YN[4:0] R/W 0 Table 5,Table 6
Byte 4:
Power Up
Bit Bit Name Description/Function Type Condition Reference To
7 RES Reserved R/W 0
6 RES Reserved R/W 0
5 ENP0 Post-divider P0 enable. If 0, output YP[4:0] and YN[4:0] are disabled R/W 1
4 ENBP0 Bypass PLL for post-divider P0. If 1, input is CLKP/CLKN; if 0 input is PLL R/W 0
clock
3 SELP0[3] Divide ratio select for post-divider P0 R/W 0 Table 2
2 SELP0[2] Divide ratio select for post-divider P0 R/W 1 Table 2
1 SELP0[1] Divide ratio select for post-divider P0 R/W 1 Table 2
0 SELP0[0] Divide ratio select for post-divider P0 R/W 1 Table 2
Byte 5:
Power Up
Bit Bit Name Description/Function Type Condition Reference To
7 EN Chip enable; if 0 chip is in Iddq mode R/W 1
6 ENDRV10 YP10, YN10 enable; if 0 output is disabled R/W 1
5 ENDRV9 YP[9], YN[9] enable; if 0 output is disabled R/W 1
4 ENDRV8 YP[8], YN[8] enable; if 0 output is disabled R/W 1
3 ENDRV7 YP[7], YN[7] enable; if 0 output is disabled R/W 1
2 ENDRV6 YP[6], YN[6] enable; if 0 output is disabled R/W 1
1 ENDRV5 YP[5], YN[5] enable; if 0 output is disabled R/W 1
0 ENDRV4 YP[4], YN[4] enable; if 0 output is disabled R/W 1
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Byte 6:
Power Up
Bit Bit Name Description/Function Type Condition Reference To
7 ENDRV3 YP[3], YN[3] enable; if 0 output is disabled R/W 1
6 ENDRV2 YP[2], YN[2] enable; if 0 output is disabled R/W 1
5 ENDRV1 YP[1], YN[1] enable; if 0 output is disabled R/W 1
4 ENDRV0 YP[0], YN[0] enable; if 0 output is disabled R/W 1
3 SELBW[3] PLL BW select; if 1 external loop filter is expected R/W 0 Table 7
2 SELBW[2] PLL BW select; if 1 external loop filter is expected R/W 0 Table 7
1 SELBW[1] PLL BW select; if 1 external loop filter is expected R/W 0 Table 7
0 SELBW[0] PLL BW select; if 1 external loop filter is expected R/W 0 Table 7
Byte 7:
Bit Power Up
Bit Name Description/Function Type Condition Reference To
7 ENPLL PLL enable; if 0 PLL is switched off R/W 1
6 RES Reserved R/W 0
5 SELM[1] Divide ratio select for input clock CLKP and CLKN R/W 0 Table 4
4 SELM[0] Divide ratio select for input clock CLKP and CLKN R/W 0 Table 4
3 SELN[3] Divide ratio select for pre-divider N (PLL clock) R/W 1 Table 3
2 SELN[2] Divide ratio select for pre-divider N (PLL clock) R/W 0 Table 3
1 SELN[1] Divide ratio select for pre-divider N (PLL clock) R/W 0 Table 3
0 SELN[0] Divide ratio select for pre-divider N (PLL clock) R/W 1 Table 3
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Table 2. Divide Ratio Settings for Post-Divider P0 or P1
Divide SELP1[3] or SELP1[2] or SELP1[1] or SELP1[0] or
Ratio SELP0[3] SELP0[2] SELP0[1] SELP0[0] Notes
1 0 0 0 0
2 0 0 0 1
4 0 0 1 0
5 0 0 1 1
8 0 1 0 0
10 0 1 0 1
16 0 1 1 0
20 0 1 1 1 Default
32 1 0 0 0
40 1 0 0 1
80 1 0 1 0
Table 3. Divide Ratio Settings for Divider N
Divide
Ratio SELN[3] SELN[2] SELN[1] SELN[0] Notes
32 1 0 0 0
40 1 0 0 1 Default
Table 4. Divide Ratio Settings for Divider M
Divide
Ratio SELM[1] SELM[0] Notes
1 0 0 Default
2 0 1
4 1 0
8 1 1
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Table 5. Phase Settings for Divide Ratio = 5, 10, 20, 40, 80
With PH0[4:0] = 00000
PH1
Divide Phase Lead
Ratio [4] [3] [2] [1] [0] (radian) Notes
5 X X X X X 0 Phase setting not available
10 X X X 0 X 0
X X X 1 X (2π/2)
20 X X 0 0 X 0 00000:Default
X X 0 1 X (2π/4)
X X 1 0 X 2(2π/4)
X X 1 1 X 3(2π/4)
40 X 0 0 0 X 0
X 0 0 1 X (2π/8)
X 0 1 0 X 2(2π/8)
X 0 1 1 X 3(2π/8)
X 1 0 0 X 4(2π/8)
X 1 0 1 X 5(2π/8)
X 1 1 0 X 6(2π/8)
X 1 1 1 X 7(2π/8)
80 0 0 0 0 X 0
0 0 0 1 X (2π/16)
0 0 1 0 X 2(2π/16)
0 0 1 1 X 3(2π/16)
0 1 0 0 X 4(2π/16)
0 1 0 1 X 5(2π/16)
0 1 1 0 X 6(2π/16)
0 1 1 1 X 7(2π/16)
1 0 0 0 X 8(2π/16)
1 0 0 1 X 9(2π/16)
1 0 1 0 X 10(2π/16)
1 0 1 1 X 11(2π/16)
1 1 0 0 X 12(2π/16)
1 1 0 1 X 13(2π/16)
1 1 1 0 X 14(2π/16)
1 1 1 1 X 15(2π/16)
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Table 6. Phase Settings for Divide Ratio = 1, 2, 4, 8, 16, 32
With PH0[4:0] = 00000
PH1
Divide Phase Lead
Ratio [4] [3] [2] [1] [0] (radian) Notes
1 X X X X X 0 Phase setting not available
2 X X X X 0 0
X X X X 1 (2π/2)
4 X X X 0 0 0
X X X 0 1 (2π/4)
X X X 1 0 2(2π/4)
X X X 1 1 3(2π/4)
8 X X 0 0 0 0
X X 0 0 1 (2π/8)
X X 0 1 0 2(2π/8)
X X 0 1 1 3(2π/8)
X X 1 0 0 4(2π/8)
X X 1 0 1 5(2π/8)
X X 1 1 0 6(2π/8)
X X 1 1 1 7(2π/8)
16 X 0 0 0 0 0
X 0 0 0 1 (2π/16)
X 0 0 1 0 2(2π/16)
X 0 0 1 1 3(2π/16)
X 0 1 0 0 4(2π/16)
X 0 1 0 1 5(2π/16)
X 0 1 1 0 6(2π/16)
X 0 1 1 1 7(2π/16)
X 1 0 0 0 8(2π/16)
X 1 0 0 1 9(2π/16)
X 1 0 1 0 10(2π/16)
X 1 0 1 1 11(2π/16)
X 1 1 0 0 12(2π/16)
X 1 1 0 1 13(2π/16)
X 1 1 1 0 14(2π/16)
X 1 1 1 1 15(2π/16)
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Table 6. Phase Settings for Divide Ratio = 1, 2, 4, 8, 16, 32 (continued)
With PH0[4:0] = 00000
PH1
Divide Phase Lead
Ratio [4] [3] [2] [1] [0] (radian) Notes
32 0 0 0 0 0 0
0 0 0 0 1 (2π/32)
0 0 0 1 0 2(2π/32)
0 0 0 1 1 3(2π/32)
0 0 1 0 0 4(2π/32)
0 0 1 0 1 5(2π/32)
0 0 1 1 0 6(2π/32)
0 0 1 1 1 7(2π/32)
0 1 0 0 0 8(2π/32)
0 1 0 0 1 9(2π/32)
0 1 0 1 0 10(2π/32)
0 1 0 1 1 11(2π/32)
0 1 1 0 0 12(2π/32)
0 1 1 0 1 13(2π/32)
0 1 1 1 0 14(2π/32)
0 1 1 1 1 15(2π/32)
1 0 0 0 0 16(2π/32)
1 0 0 0 1 17(2π/32)
1 0 0 1 0 18(2π/32)
1 0 0 1 1 19(2π/32)
1 0 1 0 0 20(2π/32)
1 0 1 0 1 21(2π/32)
1 0 1 1 0 22(2π/32)
1 0 1 1 1 23(2π/32)
1 1 0 0 0 24(2π/32)
1 1 0 0 1 25(2π/32)
1 1 0 1 0 26(2π/32)
1 1 0 1 1 27(2π/32)
1 1 1 0 0 28(2π/32)
1 1 1 0 1 29(2π/32)
1 1 1 1 0 30(2π/32)
1 1 1 1 1 31(2π/32)
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Table 7. PLL Bandwidth Setting
PLL SELBW
Bandwidth(1) C1R C2On-Chip Loop
(kHz) [3] [2] [1] [0] (nF) (Ω) (nF) Filter ON/OFF Notes
400 0 0 0 0 N/A N/A N/A ON Default
350 0 0 1 0 2.2 8660 0 OFF
300 0 0 1 1 3.3 7500 0 OFF
250 0 1 0 0 4.7 6200 0 OFF
200 0 1 1 0 8.2 4990 0 OFF
175 1 0 0 0 10 4300 0 OFF
150 1 0 1 0 15 3740 0 OFF
125 1 1 1 1 22 3090 0 OFF
100 1 1 1 1 33 2490 0.24 OFF
75 1 1 1 1 56 1870 0.82 OFF
50 1 1 1 1 150 1210 2.70 OFF
20 1 1 1 1 680 470 18 OFF
10 1 1 1 1 3300 220 68 OFF
(1) Refer to Functional Block Diagram for the external low pass filter architecture.
FREQUENCY SETTINGS FOR SOME APPLICATIONS
APPLICATION
PROTOCOL Output Output VCO PLL Ref Clock Ref Clock PLL Ref Clock Ref Clock
Clock Divider Freq Divider Divider Max Freq Divider Divider Min Freq
MHz P0, P1 GHz N (max f) M (max f) MHz N (min f) M (min f) MHz
10G Ethernet 312.5 4 1.250 32 8 312.5 40 1 31.25
(XAUI) 156.25 8 1.250 32 8 312.5 40 1 31.25
78.125 16 1.250 32 8 312.5 40 1 31.25
62.5 20 1.250 32 8 312.5 40 1 31.25
1G Ethernet 250 5 1.250 40 8 250 40 1 31.25
Serial ATA 125 10 1.250 40 8 250 40 1 31.25
62.5 20 1.250 40 8 250 40 1 31.25
10X FIBRE CHANNEL 159.375 8 1.275 32 8 318.75 40 1 31.875
63.75 20 1.275 32 8 318.75 40 1 31.875
CPRI 245.76 5 1.229 40 8 245.78 40 1 30.72
122.88 10 1.229 40 8 245.78 40 1 30.72
61.44 20 1.229 40 8 245.78 40 1 30.72
30.72 40 1.229 40 8 245.78 40 1 30.72
OBSAI 153.6 8 1.229 32 8 307.2 32 1 38.4
76.8 16 1.229 32 8 307.2 32 1 38.4
PCI Express 250 5 1.250 40 8 250 40 1 31.25
Serial ATA 150 8 1.200 32 8 300 32 1 37.5
75 16 1.200 32 8 300 32 1 37.5
SONET 622.08 2 1.244 32 8 311.04 40 1 31.104
311.04 4 1.244 32 8 311.04 40 1 31.104
155.52 8 1.244 32 8 311.04 40 1 31.104
62.208 20 1.244 32 8 311.04 40 1 31.104
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REVISION HISTORY
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Original (February 2007) to Revision A Page
•Added second specification condition for clock output skew parameter. ............................................................................. 4
Changes from Revision A (March 2008) to Revision B Page
•Added Sentence to the Description: The serial interface is 1.8V tolerant only. ................................................................... 2
•Changed VILVDS From: -0.3 to 4.0 To: -0.3 to VDD + 0.6 in the Abs Max table ..................................................................... 3
•Changed VIFrom: -0.3 to 3.0 To: -0.3 to VDD + 0.6 in the Abs Max table ............................................................................ 3
•Added the THERMAL INFORMATION table ........................................................................................................................ 3
•Changed the Test Conditions of VD,OUT in the AC Electrical Characteristics table ............................................................... 4
•Changed the description of SCL and SDA in the PIn Functions table ................................................................................. 7
•Added Note 1 to the FUNCTIONAL BLOCK DIAGRAM ....................................................................................................... 8
•Added the SDA/SCL Connections Recommendations section .......................................................................................... 12
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PACKAGE OPTION ADDENDUM
www.ti.com 22-Jun-2012
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
CDCL6010RGZR ACTIVE VQFN RGZ 48 2500 Green (RoHS
& no Sb/Br) CU NIPDAUAGLevel-3-260C-168 HR
CDCL6010RGZRG4 ACTIVE VQFN RGZ 48 2500 Green (RoHS
& no Sb/Br) CU NIPDAUAGLevel-3-260C-168 HR
CDCL6010RGZT ACTIVE VQFN RGZ 48 250 Green (RoHS
& no Sb/Br) CU NIPDAUAGLevel-3-260C-168 HR
CDCL6010RGZTG4 ACTIVE VQFN RGZ 48 250 Green (RoHS
& no Sb/Br) CU NIPDAUAGLevel-3-260C-168 HR
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
CDCL6010RGZR VQFN RGZ 48 2500 330.0 16.4 7.3 7.3 1.5 12.0 16.0 Q2
CDCL6010RGZT VQFN RGZ 48 250 330.0 16.4 7.3 7.3 1.5 12.0 16.0 Q2
PACKAGE MATERIALS INFORMATION
www.ti.com 16-Feb-2012
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
CDCL6010RGZR VQFN RGZ 48 2500 336.6 336.6 28.6
CDCL6010RGZT VQFN RGZ 48 250 336.6 336.6 28.6
PACKAGE MATERIALS INFORMATION
www.ti.com 16-Feb-2012
Pack Materials-Page 2
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