W223-02
PRELIMINARY
Document #: 38-07243 Rev. ** Page 3 of 11
Overview
The Cypress W223-02 is a low-voltage, ten-output clock buff-
er. Output buffer impedance is approximately 15Ω which is
ideal for driving SDRAM DIMMs.
Functional Description
Output Control Pins
Outputs three-stated when OE = 0, and toggle when OE = 1.
Outputs are in phase with BUF_IN but are phase delayed by
3 to 7ns. Outputs can also be controlled via the I2C interface.
Output Drivers
The W223-02 output buffers are CMOS type which deliver a
rail-to-rail (GND to VDD) output voltage swing into a nominal
capaci tive load. Thus , outp ut signaling is both TTL and CMOS
level compatible. Nominal output buffer impedance is 15Ω.
Operation
Data is written to the W223-02 in eleven bytes of eight bits
each. Bytes are written in the order shown in Table 1.
Table 1. Byte Writing Sequence
Byte
Sequence Byte Name Bit Sequence Byte Description
1 Sl ave Addres s 11010010 Command s the W223-02 to accept th e bits in Data By tes 0–7 fo r int er-
nal regis ter c onfi gu ration. Since other devic es may exist on the sam e
common serial data bus, it is necessary to have a specific slave address
for each potential receiver . The slave receiver address for the W223-02
is 11010010. Re gis ter sett ing w ill not b e ma de if the Slav e Ad dres s i s
not correct (or is for an alternate slave receiver).
2 Command Code “Don’t Care”Unused by the W223-02, therefore bit values are ignored (“Don’t Care).
This byte must be included in the data write sequence to maintain prop-
er byte allocation. The Command Code Byte is part of the standard
serial c ommunicat ion protocol and may be u sed when writ ing to anot h-
er addressed slave receiver on the serial data bus.
3 By te Count “Don’t Care”Unused by the W223-02, therefore bit values are ignored (“Don’t
Care”). This b yte must be inc luded in the data write sequ ence to main-
tain proper byte allocati on. The Byte Count Byte is part of the standard
serial c ommunicat ion protocol and may be u sed when writ ing to anot h-
er addressed slave receiver on the serial data bus.
4 Data Byte 0 “Don’t Care”Refer to Cypress clock drivers.
5 Data Byte 1
6 Data Byte 2
7 Data Byte 3
8 Data Byte 4
9 Data Byte 5 Refer to Table 2 The data bits in thes e bytes set inte rnal W223-02 re gisters t hat control
device operation. The data bits are only accepted when the Address
Byte bit se quence is 11010010, a s note d a bo ve. Fo r description of bi t
control fu nctions, ref er to Table 2, Data B yte Serial Co nfigura tion Map.
10 Data Byte 6
11 Data Byte 7