Ultralow Distortion,
High Speed Amplifiers
AD8007/AD8008
Rev. E
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FEATURES
Extremely low distortion
Second harmonic
−88 dBc @ 5 MHz
−83 dBc @ 20 MHz (AD8007)
−77 dBc @ 20 MHz (AD8008)
Third harmonic
−101 dBc @ 5 MHz
−92 dBc @ 20 MHz (AD8007)
−98 dBc @ 20 MHz (AD8008)
High speed
650 MHz, −3 dB bandwidth (G = +1)
1000 V/μs slew rate
Low noise
2.7 nV/√Hz input voltage noise
22.5 pA/√Hz input inverting current noise
Low power: 9 mA/amplifier typical supply current
Wide supply voltage range: 5 V to 12 V
0.5 mV typical input offset voltage
Small packaging: 8-lead SOIC, 8-lead MSOP, and 5-lead SC70
APPLICATIONS
Instrumentation
IF and baseband amplifiers
Filters
A/D drivers
DAC buffers
CONNECTION DIAGRAMS
8
7
6
5
1
2
3
4
NC = NO CONNECT
NC
–IN
+IN
NC
+V
S
V
OUT
NC
–V
S
AD8007
(Top View)
02866-001
Figure 1. 8-Lead SOIC (R)
5
1
2
3
–IN
+IN
+V
S
V
OUT
–V
S
4
AD8007
(Top View)
02866-002
Figure 2. 5-Lead SC70 (KS)
1
V
OUT1
–IN1
+IN1
–V
S
+V
S
V
OUT2
–IN2
+IN2
8
27
36
45
AD8008
(Top View)
02866-003
Figure 3. 8-Lead SOIC (R) and 8-Lead MSOP (RM)
GENERAL DESCRIPTION
The AD8007 (single) and AD8008 (dual) are high performance
current feedback amplifiers with ultralow distortion and noise.
Unlike other high performance amplifiers, the low price and
low quiescent current allow these amplifiers to be used in a
wide range of applications. Analog Devices, Inc., proprietary
second-generation eXtra-Fast Complementary Bipolar (XFCB)
process enables such high performance amplifiers with low power
consumption.
The AD8007/AD8008 have 650 MHz bandwidth, 2.7 nV/√Hz
voltage noise, −83 dB SFDR at 20 MHz (AD8007), and −77 dBc
SFDR at 20 MHz (AD8008).
With the wide supply voltage range (5 V to 12 V) and wide
bandwidth, the AD8007/AD8008 are designed to work in a
variety of applications. The AD8007/AD8008 amplifiers have
a low power supply current of 9 mA/amplifier.
The AD8007 is available in a tiny SC70 package as well as a
standard 8-lead SOIC. The dual AD8008 is available in both an
8-lead SOIC and an 8-lead MSOP. These amplifiers are rated to
work over the industrial temperature range of −40°C to +85°C.
FREQUENCY (MHz)
–
30
–40
–110 1110
DISTO
00
R
TION (dBc)
–70
–80
–90
–100
–50
–60
SECOND
G = +2
R
L
= 150Ω
V
S
= ±5V
V
OUT
= 2V p-p
02866-004
THIRD
Figure 4. AD8007 Second and Third Harmonic Distortion vs. Frequency
AD8007/AD8008
Rev. E | Page 2 of 20
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
Connection Diagrams ...................................................................... 1
General Description ......................................................................... 1
Revision History ............................................................................... 2
Specifications ..................................................................................... 3
VS = ±5 V ....................................................................................... 3
VS = 5 V .......................................................................................... 4
Absolute Maximum Ratings ............................................................ 6
Maximum Power Dissipation ......................................................... 6
Output Short Circuit ........................................................................ 6
ESD Caution .................................................................................. 6
Typical Performance Characteristics ..............................................7
Theory of Operation ...................................................................... 15
Using the AD8007/AD8008 ...................................................... 15
Layout Considerations ............................................................... 16
Layout And Grounding Considerations ...................................... 17
Grounding ................................................................................... 17
Input Capacitance ...................................................................... 17
Output Capacitance ................................................................... 17
Input-to-Output Coupling ........................................................ 17
External Components and Stability ......................................... 17
Outline Dimensions ....................................................................... 18
Ordering Guide .......................................................................... 19
REVISION HISTORY
11/09—Rev. D to Rev. E
Change to Output Capacitance Section ....................................... 17
Updated Outline Dimensions ....................................................... 18
Changes to Ordering Guide .......................................................... 19
6/03—Rev. C to Rev. D
Change to Layout Considerations Section .................................. 15
Deleted Figure 7 .............................................................................. 16
Deleted Evaluation Board Section ................................................ 16
Updated Outline Dimensions ....................................................... 16
10/02—Rev. B to Rev. C
Connection Diagrams Captions Updated .................................... 1
Ordering Guide Updated ................................................................ 5
Figure 5 Edited ............................................................................... 14
Updated Outline Dimensions ....................................................... 19
9/02—Rev. A to Rev. B
Updated Outline Dimensions ....................................................... 19
8/02—Rev. 0 to Rev. A
Added AD8008 .................................................................. Universal
Added SOIC-8 (RN) and MSOP-8 (RM) ...................................... 1
Changes to Features .......................................................................... 1
Changes to General Description .................................................... 1
Changes to Specifications ................................................................ 2
Edits to Maximum Power Dissipation Section ............................. 4
New Figure 2 ..................................................................................... 4
Changes to Ordering Guide ............................................................ 5
New TPCs 19 to 24 and TPCs 27, 29, 30, and 35 .......................... 9
Changes to Evaluation Board Section ......................................... 16
MSOP-8 (RM) Added ................................................................... 19
AD8007/AD8008
Rev. E | Page 3 of 20
SPECIFICATIONS
VS = ±5 V
TA = 25°C, RS = 200 Ω, RL = 150 Ω, RF = 499 Ω, Gain = +2, unless otherwise noted.
Table 1.
AD8007/AD8008
Parameter Conditions Min Typ Max Unit
DYNAMIC PERFORMANCE
−3 dB Bandwidth G = +1, VO = 0.2 V p-p, RL = 1 kΩ 540 650 MHz
G = +1, VO = 0.2 V p-p, RL = 150 Ω 250 500 MHz
G = +2, VO = 0.2 V p-p, RL = 150 Ω 180 230 MHz
G = +1, VO = 2 V p-p, RL = 1 kΩ 200 235 MHz
Bandwidth for 0.1 dB Flatness VO = 0.2 V p-p, G = +2, RL = 150 Ω 50 90 MHz
Overdrive Recovery Time ±2.5 V input step, G = +2, RL = 1 kΩ 30 ns
Slew Rate G = +1, VO = 2 V step 900 1000 V/μs
Settling Time to 0.1% G = +2, VO = 2 V step 18 ns
Settling Time to 0.01% G = +2, VO = 2 V step 35 ns
NOISE/HARMONIC PERFORMANCE
Second Harmonic fC = 5 MHz, VO = 2 V p-p −88 dBc
f
C = 20 MHz, VO = 2 V p-p −83/−77 dBc
Third Harmonic fC = 5 MHz, VO = 2 V p-p −101 dBc
IMD fC = 20 MHz, VO = 2 V p-p −92/−98 dBc
f
C = 19.5 MHz to 20.5 MHz, RL = 1 kΩ, VO = 2 V p-p −77 dBc
Third-Order Intercept fC = 5 MHz, RL = 1 kΩ 43.0/42.5 dBm
f
C = 20 MHz, RL = 1 kΩ 42.5 dBm
Crosstalk (AD8008) f = 5 MHz, G = +2 −68 dB
Input Voltage Noise f = 100 kHz 2.7 nV/√Hz
Input Current Noise −Input, f = 100 kHz 22.5 pA/√Hz
+Input, f = 100 kHz 2 pA/√Hz
Differential Gain Error NTSC, G = +2, RL = 150 Ω 0.015 %
Differential Phase Error NTSC, G = +2, RL = 150 Ω 0.010 Degree
DC PERFORMANCE
Input Offset Voltage 0.5 4 mV
Input Offset Voltage Drift 3 μV/°C
Input Bias Current +Input 4 8 μA
−Input 0.4 6 μA
Input Bias Current Drift +Input 16 nA/°C
−Input 9 nA/°C
Transimpedance VO = ±2.5 V, RL = 1 kΩ 1.0 1.5 MΩ
R
L = 150 Ω 0.4 0.8 MΩ
INPUT CHARACTERISTICS
Input Resistance +Input 4 MΩ
Input Capacitance +Input 1 pF
Input Common-Mode Voltage Range −3.9 to +3.9 V
Common-Mode Rejection Ratio VCM = ±2.5 V 56 59 dB
OUTPUT CHARACTERISTICS
Output Saturation Voltage VCC − VOH, VOL − VEE, RL = 1 kΩ 1.1 1.2 V
Short-Circuit Current, Source 130 mA
Short-Circuit Current, Sink 90 mA
Capacitive Load Drive 30% overshoot 8 pF
AD8007/AD8008
Rev. E | Page 4 of 20
AD8007/AD8008
Parameter Conditions Min Typ Max Unit
POWER SUPPLY
Operating Range 5 12 V
Quiescent Current per Amplifier 9 10.2 mA
Power Supply Rejection Ratio
+PSRR 59 64 dB
−PSRR 59 65 dB
VS = 5 V
TA = 25°C, RS = 200 Ω, RL = 150 Ω, RF = 499 Ω, Gain = +2, unless otherwise noted.
Table 2.
AD8007/AD8008 Unit
Parameter Conditions Min Typ Max
DYNAMIC PERFORMANCE
−3 dB Bandwidth G = +1, VO = 0.2 V p-p, RL = 1 kΩ 520 580 MHz
G = +1, VO = 0.2 V p-p, RL = 150 Ω 350 490 MHz
G = +2, VO = 0.2 V p-p, RL = 150 Ω 190 260 MHz
G = +1, VO = 1 V p-p, RL = 1 kΩ 270 320 MHz
Bandwidth for 0.1 dB Flatness VO = 0.2 V p-p, G = +2, RL = 150 Ω 72 120 MHz
Overdrive Recovery Time 2.5 V input step, G = +2, RL = 1 kΩ 30 ns
Slew Rate G = +1, VO = 2 V step 665 740 V/μs
Settling Time to 0.1% G = +2, VO = 2 V step 18 ns
Settling Time to 0.01% G = +2, VO = 2 V step 35 ns
NOISE/HARMONIC PERFORMANCE
Second Harmonic fC = 5 MHz, VO = 1 V p-p −96/−95 dBc
f
C = 20 MHz, VO = 1 V p-p −83/−80 dBc
Third Harmonic fC = 5 MHz, VO = 1 V p-p −100 dBc
f
C = 20 MHz, VO = 1 V p-p −85/−88 dBc
IMD fC = 19.5 MHz to 20.5 MHz, RL = 1 kΩ,
VO = 1 V p-p
−89/−87 dBc
Third-Order Intercept fC = 5 MHz, RL = 1 kΩ 43.0 dBm
f
C = 20 MHz, RL = 1 kΩ 42.5/41.5 dBm
Crosstalk (AD8008) Output-to-output, f = 5 MHz, G = +2 −68 dB
Input Voltage Noise f = 100 kHz 2.7 nV/√Hz
Input Current Noise −Input, f = 100 kHz 22.5 pA/√Hz
+Input, f = 100 kHz 2 pA/√Hz
DC PERFORMANCE
Input Offset Voltage 0.5 4 mV
Input Offset Voltage Drift 3 μV/°C
Input Bias Current +Input 4 8 μA
−Input 0.7 6 μA
Input Bias Current Drift +Input 15 nA/°C
−Input 8 nA/°C
Transimpedance VO = 1.5 V to 3.5 V, RL = 1 kΩ 0.5 1.3 MΩ
R
L = 150 Ω 0.4 0.6 MΩ
INPUT CHARACTERISTICS
Input Resistance +Input 4 MΩ
Input Capacitance +Input 1 pF
Input Common-Mode Voltage Range 1.1 to 3.9 V
Common-Mode Rejection Ratio VCM = 1.75 V to 3.25 V 54 56 dB
AD8007/AD8008
Rev. E | Page 5 of 20
AD8007/AD8008 Unit
Parameter Conditions Min Typ Max
OUTPUT CHARACTERISTICS
Output Saturation Voltage VCC − VOH, VOL − VEE, RL = 1 kΩ 1.05 1.15 V
Short-Circuit Current, Source 70 mA
Short-Circuit Current, Sink 50 mA
Capacitive Load Drive 30% overshoot 8 pF
POWER SUPPLY
Operating Range 5 12 V
Quiescent Current per Amplifier 8.1 9 mA
Power Supply Rejection Ratio
+PSRR 59 62 dB
−PSRR 59 63 dB
AD8007/AD8008
Rev. E | Page 6 of 20
ABSOLUTE MAXIMUM RATINGS
Table 3.
Parameter Rating
Supply Voltage 12.6 V
Power Dissipation See Figure 5
Common-Mode Input Voltage ±VS
Differential Input Voltage ±1.0 V
Output Short-Circuit Duration See Figure 5
Storage Temperature Range −65°C to +125°C
Operating Temperature Range −40°C to +85°C
Lead Temperature (Soldering, 10 sec) 300°C
RMS output voltages should be considered. If RL is referenced to
VS, as in single-supply operation, then the total drive power is
VS × IOUT.
If the rms signal levels are indeterminate, then consider the
worst case, when VOUT = VS/4 for RL to midsupply
L
S
SS
DR
V
IVP
2
4
)(
⎟
⎠
⎞
⎜
⎝
⎛
+×=
In single-supply operation, with RL referenced to VS, worst case is
VOUT = VS/2.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Airflow increases heat dissipation, effectively reducing θJA. In
addition, more metal directly in contact with the package leads
from metal traces, through-holes, ground, and power planes
reduces the θJA. Care must be taken to minimize parasitic
capacitances at the input leads of high speed op amps, see the
Layout Considerations section.
Figure 5 shows the maximum safe power dissipation in the
package vs. the ambient temperature for the SOIC-8 (125°C/W),
MSOP-8 (150°C/W), and SC70-5 (210°C/W) packages on a
JEDEC standard 4-layer board. θJA values are approximations.
MAXIMUM POWER DISSIPATION
The maximum safe power dissipation in the AD8007/AD8008
packages is limited by the associated rise in junction temperature
(TJ) on the die. The plastic encapsulating the die locally reaches
the junction temperature. At approximately 150°C, which is the
glass transition temperature, the plastic changes its properties.
Even temporarily exceeding this temperature limit can change
the stresses that the package exerts on the die, permanently
shifting the parametric performance of the AD8007/AD8008.
Exceeding a junction temperature of 175°C for an extended
time can result in changes in the silicon devices, potentially
causing failure.
AMBIENT TEMPERATURE (°C)
2.0
1.5
000106– –40
MAXIMUM POWER DISSIPATION (W)
–20 0 20 40 60 80
1.0
0.5
SOIC-8
SC70-5
MSOP-8
02866-005
The still-air thermal properties of the package and PCB (θJA),
ambient temperature (TA), and the total power dissipated in the
package (PD) determine the junction temperature of the die.
The junction temperature can be calculated as
TJ = TA + (PD × θJA)
Figure 5. Maximum Power Dissipation vs. Temperature for a 4-Layer Board
The power dissipated in the package (PD) is the sum of the
quiescent power dissipation and the power dissipated in the
package due to the load drive for all outputs. The quiescent
power is the voltage between the supply pins (VS) times the
quiescent current (IS). Assuming the load (RL ) is referenced to
midsupply, the total drive power is VS/2 × IOUT, some of which is
dissipated in the package and some in the load (VOUT × IOUT).
The difference between the total drive power and the load
power is the drive power dissipated in the package.
OUTPUT SHORT CIRCUIT
Shorting the output to ground or drawing excessive current for
the AD8007/AD8008 will likely cause catastrophic failure.
ESD CAUTION
PD = Quiescent Power + (Total Drive Power − Load Power)
L
OUT
L
OUTS
SS
DR
V
R
V
V
IVP
2
2
)( −
⎟
⎟
⎠
⎞
⎜
⎜
⎝
⎛×+×=
AD8007/AD8008
Rev. E | Page 7 of 20
TYPICAL PERFORMANCE CHARACTERISTICS
VS = ±5 V, RL = 150 Ω, RS = 200 Ω, RF = 499 Ω, unless otherwise noted.
FREQUENCY (MHz)
3
2
–5
1 10010
NORMALIZED GAIN (dB)
–1
–2
–3
–4
1
0
–6
–7 1000
G = +1
G = +2
G = +10
G = –1
02866-006
Figure 6. Small Signal Frequency Response for Various Gains
FREQUENCY (MHz)
3
2
–5
10010
GAIN (dB)
–1
–2
–3
–4
1
0
–6
–7 1000
G = +1
R
L
= 1kΩ, V
S
= ±5V
R
L
= 150kΩ, V
S
= ±5V
R
L
= 150kΩ, V
S
= 5V
02866-007
Figure 7. Small Signal Frequency Response for VS and RL
FREQUENCY (MHz)
3
2
–5
10010
GAIN (dB)
–1
–2
–3
–4
1
0
–6
–7 1000
G = +1
R
L
= 1kΩ
R
S
= 200Ω
R
S
= 301Ω
R
S
= 249Ω
02866-008
Figure 8. Small Signal Frequency Response for Various RS Values
FREQUENCY (MHz)
6.4
6.3
5.6
10010
GAIN (dB)
6.0
5.9
5.8
5.7
6.2
6.1
5.5
5.4 1000
G = +2
V
S
= +5V
V
S
= ±5V
02866-009
Figure 9. 0.1 dB Gain Flatness; VS = +5, VS = ±5 V
FREQUENCY (MHz)
9
8
1
10010
GAIN (dB)
5
4
3
2
7
6
0
–1 1000
G = +2
R
L
= 1kΩ, V
S
= +5V
R
L
= 150kΩ,
V
S
= +5V
R
L
= 1kΩ, V
S
= ±5V
R
L
= 150kΩ, V
S
= ±5V
02866-010
Figure 10. Small Signal Frequency Response for VS and RL
FREQUENCY (MHz)
9
8
1
10010
GAIN (dB)
5
4
3
2
7
6
0
–1 1000
G = +2
R
F
= R
G
= 324Ω
R
F
= R
G
= 249Ω
R
F
= R
G
= 499Ω
R
F
= R
G
= 649Ω
02866-011
Figure 11. Small Signal Frequency Response for Various Feedback Resistors,
RF = RG
AD8007/AD8008
Rev. E | Page 8 of 20
FREQUENCY (MHz)
10
9
2
1 10010
GAIN (dB)
6
5
4
3
8
7
1
01000
G = +2 20pF
0pF
499Ω
499Ω
200Ω
49.9Ω
R
SNUB
C
LOAD
20pF AND
20Ω SNUB
20pF AND
10Ω SNUB
02866-012
Figure 12. Small Signal Frequency Response for
Capacitive Load and Snub Resistor
FREQUENCY (MHz)
3
2
–5
10010
GAIN (dB)
–1
–2
–3
–4
1
0
–6
–7 1000
G = +1 V
S
= +5V, +85°C
V
S
= ±5V, +85°C
V
S
= +5V, –40°C
V
S
= ±5V, –40°C
02866-013
Figure 13. Small Signal Frequency Response over Temperature,
VS = +5 V, VS = ±5 V
FREQUENCY (MHz)
3
2
–5
1 10010
NORMALIZED GAIN (dB)
–1
–2
–3
–4
1
0
–6
–7 1000
VOUT = 2V p-p
G = +1 G = +2
G = +10
G = –1
02866-014
Figure 14. Large Signal Frequency Response for Various Gains
FREQUENCY (Hz)
10M
1M
100k10k
TRANSIMPEDANCE (Ω)
1k
100
10
1
100k
10k
10M 100M 1G
0
–30
–90
–150
–210
–270
–330
PHASE (Degrees)
2G
TRANSIMPEDANCE
PHASE
30
90
–180
1M
02866-015
Figure 15. Transimpedance and Phase vs. Frequency
FREQUENCY (MHz)
9
8
1
10010
GAIN (dB)
5
4
3
2
7
6
0
–1 1000
G = +2
V
S
= +5V, +85°C
V
S
= ±5V, +85°C
V
S
= +5V, –40°C
V
S
= ±5V, –40°C
02866-016
Figure 16. Small Signal Frequency Response over Temperature,
VS = +5 V, VS = ±5 V
FREQUENCY (MHz)
9
8
1
10010
GAIN (dB)
5
4
3
2
7
6
0
–1 1000
G = +2
R
L
= 150Ω,V
S
= ±5V, V
O
= 2V p-p
R
L
= 150Ω,V
S
= +5V, V
O
= 1V p-p
R
L
= 1kΩ,V
S
= +5V, V
O
= 1V p-p
R
L
= 1kΩ,V
S
= ±5V, V
O
= 2V p-p
02866-017
Figure 17. Large Signal Frequency Response for VS and RL
AD8007/AD8008
Rev. E | Page 9 of 20
FREQUENCY (MHz)
–90
101
DISTORTION (dBc)
–50
–60
–70
–80
–40
–100
–110 100
G = +1
V
S
= 5V
V
O
= 1V p-p HD2, R
L
= 150Ω
HD3, R
L
= 150Ω
HD2, R
L
= 1kΩ
HD3, R
L
= 1kΩ
02866-018
Figure 18. AD8007 Second and Third Harmonic Distortion vs. Frequency and RL
FREQUENCY (MHz)
–90
101
DISTORTION (dBc)
–50
–60
–70
–80
–40
–100
–110100
G = +1
V
S
= ±5V
V
O
= 2V p-p
HD2, R
L
= 150Ω
HD2, R
L
= 1kΩ
HD3, R
L
= 1kΩ
HD3, R
L
= 150Ω
02866-019
Figure 19. AD8007 Second and Third Harmonic Distortion vs. Frequency and RL
FREQUENCY (MHz)
–90
101
DISTORTION (dBc)
–50
–60
–70
–80
–40
–100
–110
100
–30 V
S
= ±5V
V
O
= 2V p-p
R
L
= 150Ω
HD2, G = +10
HD3, G = +10
HD3, G = +1
HD2, G = +1
02866-020
Figure 20. AD8007 Second and Third Harmonic Distortion vs. Frequency and Gain
FREQUENCY (MHz)
–90
101
DISTORTION (dBc)
–50
–60
–70
–80
–40
–100
–110
100
G = +2
V
S
= 5V
V
O
= 1V p-p
HD2, R
L
= 1kΩ
HD2, R
L
= 150Ω
HD3, R
L
= 150Ω
HD3, R
L
= 1kΩ
02866-021
Figure 21. AD8007 Second and Third Harmonic Distortion vs. Frequency and RL
FREQUENCY (MHz)
–90
101
DISTORTION (dBc)
–50
–60
–70
–80
–40
–100
–110 100
G = +2
VS = ±5V
VO = 2V p-p
HD2, RL = 1kΩ
HD2, RL = 150Ω
HD3, RL = 150Ω
HD3, RL = 1kΩ
02866-022
Figure 22. AD8007 Second and Third Harmonic Distortion vs. Frequency and RL
FREQUENCY (MHz)
–90
101
DISTORTION (dBc)
–50
–60
–70
–80
–40
–100
–110
100
–30 G = +2
VS = ±5V
RL = 150Ω
HD3, VO = 4V p-p
HD2, VO = 4V p-p
HD2, VO = 2V p-p
HD3, VO = 2V p-p
02866-023
Figure 23. AD8007 Second and Third Harmonic Distortion vs. Frequency and VO
AD8007/AD8008
Rev. E | Page 10 of 20
VS = ±5 V, RS = 200 Ω, RF = 499 Ω, RL = 150 Ω, @ 25°C, unless otherwise noted.
FREQUENCY (MHz)
10010
–40
1
DISTORTION (dBc)
–110
–100
–90
–80
–70
–60
–50
G = 1
V
S
= 5V
V
O
= 1V p-p
HD2, R
L
= 150Ω
HD2, R
L
= 1kΩ
HD3, R
L
= 150Ω
HD3, R
L
= 1kΩ
02866-024
Figure 24. AD8008 Second and Third Harmonic Distortion vs. Frequency and RL
FREQUENCY (MHz)
–40
1 10010
DISTORTION (dBc)
–110
–100
–90
–80
–70
–60
–50
G = 1
VS = 5V
VO = 1V p-p
HD2, RL = 150Ω
HD2, RL = 1kΩ
HD3, RL = 1kΩHD3, RL = 150Ω
02866-025
Figure 25. AD8008 Second and Third Harmonic Distortion vs. Frequency and RL
FREQUENCY (MHz)
10010
HD2, G = 10
HD2, G = 1
HD3, G = 1
HD3, G = 10
–40
1
DISTORTION (dBc)
–110
–100
–90
–80
–70
–60
–50
–30
V
S
= ±5V
V
O
= 2V p-p
R
L
= 150Ω
02866-026
Figure 26. AD8008 Second and Third Harmonic Distortion vs. Frequency and Gain
FREQUENCY (MHz)
10010
–40
1
DISTORTION (dBc)
–110
–100
–90
–80
–70
–60
–50
G = 2
V
S
= 5V
V
O
= 1V p-p
HD2, R
L
= 150Ω
HD2, R
L
= 1kΩ
HD3, R
L
= 150Ω
HD3, R
L
= 1kΩ
02866-027
Figure 27. AD8008 Second and Third Harmonic Distortion vs. Frequency and RL
FREQUENCY (MHz)
10010
–40
1
DISTORTION (dBc)
–110
–100
–90
–80
–70
–60
–50
G = 2
V
S
= ±5V
V
O
= 2V p-p
HD2, R
L
= 1kΩ
HD2, R
L
= 150Ω
HD3, R
L
= 1kΩ
HD3, R
L
= 150Ω
02866-028
Figure 28. AD8008 Second and Third Harmonic Distortion vs. Frequency and RL
FREQUENCY (MHz)
10010
–40
–110
–100
–90
–80
–70
–60
–50
–30
1
DISTORTION (dBc)
G = 2
R
L
= 150Ω
V
S
= ±5V
HD2, V
O
= 4V p-p
HD2, V
O
= 2V p-p
HD3, V
O
= 4V p-p
HD3, V
O
= 2V p-p
02866-029
Figure 29. AD8008 Second and Third Harmonic Distortion vs. Frequency and VO
AD8007/AD8008
Rev. E | Page 11 of 20
–90 1.51.0
DISTORTION (dBc)
–70
–75
–80
–85
–65
2.0 2.5
–60
V
OUT
(V p-p)
G = +2
V
S
= 5V
F
O
= 20MHz
HD3, R
L
= 1kΩ
HD2, R
L
= 1kΩ
HD3, R
L
= 150Ω
HD2, R
L
= 150Ω
02866-030
Figure 30. AD8007 Second and Third Harmonic Distortion vs. VOUT and RL
FREQUENCY (MHz)
38
5
THIRD ORDER INTERCEPT (dBm)
42
41
40
39
43
37
36
35
10 15 20 25 30 35 40 45 50 55 60 65 70
44 G = +2
V
S
= ±5V
V
O
= 2V p-p
R
L
= 1kΩ
02866-031
Figure 31. AD8007 Third-Order Intercept vs. Frequency
–90 1.51.0
–70
–75
–80
–85
–65
2.0 2.5
DISTORTION (dBc)
G = +2
V
S
= 5V
F
O
= 20MHz HD2, R
L
= 150Ω
HD2, R
L
= 1kΩ
V
OUT
(V p-p)
HD3, R
L
= 150Ω
HD3, R
L
= 1kΩ
02866-032
Figure 32. AD8008 Second and Third Harmonic Distortion vs. VOUT and RL
–90
21
DISTORTION (dBc)
–70
–75
–80
–85
–65
34
–95
–100
–105
–110
56
G = +2
V
S
= ±5V
F
O
= 20MHz
HD2, R
L
= 150Ω
HD3, R
L
= 1kΩ
HD2, R
L
= 1kΩ
HD3, R
L
= 150Ω
V
OUT
(V p-p)
02866-033
Figure 33. AD8007 Second and Third Harmonic Distortion vs. VOUT and RL
FREQUENCY (MHz)
38
42
41
40
39
43
70
44
37
36
35 6560555045403530252015105
THIRD-ORDER INTERCEPT (dBm)
G = +2
V
S
= ±5V
V
O
= 2V p-p
R
L
= 1kΩ
02866-034
Figure 34. AD8008 Third-Order Intercept vs. Frequency
–90
1
–70
–75
–80
–85
–65
62
–95
–100
–105
–110 345
HD2, R
L
= 1kΩ
HD2, R
L
= 150Ω
HD3, R
L
= 150Ω
HD3, R
L
= 1kΩ
G = +2
V
S
= 5V
F
O
= 20MHz
V
OUT
(V p-p)
DISTORTION (dBc)
02866-035
Figure 35. AD8008 Second and Third Harmonic Distortion vs. VOUT and RL
AD8007/AD8008
Rev. E | Page 12 of 20
VS = ±5 V, RL = 150 Ω, RS = 200 Ω, RF = 499 Ω, unless otherwise noted.
FREQUENCY (Hz)
k101 100
VOLTAGE NOISE (nV/ Hz)
100
10
110k 100k 1M
2.7nV/ Hz
02866-036
Figure 36. Input Voltage Noise vs. Frequency
FREQUENCY (Hz)
M01k0011M
OUTPUT IMPEDANCE (Ω)
100
10
1
100M 1G
1k
0.1
0.01
G = +2
02866-037
Figure 37. Output Impedance vs. Frequency
FREQUENCY (Hz)
100M 1G
CMRR (dB)
–10
–20
–30
100k 1M
0
10M
–40
–50
–60
–70
V
S
= ±5V, +5V
02866-038
Figure 38. CMRR vs. Frequency
FREQUENCY (Hz)
k0101 100
CURRENT NOISE (pA/ Hz)
100
10
1
100k 1M
1000
10M1k
NONINVERTING CURRENT NOISE 2.0pA/ Hz
INVERTING CURRENT NOISE 22.5pA / Hz
02866-039
Figure 39. Input Current Noise vs. Frequency
FREQUENCY (Hz)
1G100k
CROSSTALK (dB)
–100
1M 10M 100M
–90
–80
–70
–60
–50
–40
–20
–30
SIDE B DRIVEN
SIDE A DRIVEN
G = +2
R = 150Ω
V
S
= ±5V
V
M
= 1V p-p
02866-040
Figure 40. AD8008 Crosstalk vs. Frequency (Output to Output)
FREQUENCY (Hz)
20
10
M1k01 100k
PSRR (dB)
–20
–30
–40
–50
0
–10
10M 100M 1G
–60
–70
–80
+PSRR
–PSRR
02866-041
Figure 41. PSRR vs. Frequency
AD8007/AD8008
Rev. E | Page 13 of 20
50mV/DIV
010
20 30 40 50
TIME (ns)
G = +1 R
L
= 150Ω,V
S
= +5V AND ±5V
R
L
= 150Ω,V
S
= +5V AND ±5V
02866-042
Figure 42. Small Signal Transient Response for
RL = 150 Ω, RL = 1 kΩ and VS = +5 V, VS = ±5 V
1V/DIV
G = +1
0 102030405
TIME (ns)
R
L
= 150Ω
R
L
= 1kΩ
02866-043
0
Figure 43. Large Signal Transient Response for RL = 150 Ω, RL = 1 kΩ
G = +2
1V/DIV
05040302010
TIME (ns)
C
LOAD
= 0pF
C
LOAD
= 10pF
C
LOAD
= 20pF
02866-044
Figure 44. Large Signal Transient Response for
CLOAD = 0 pF, CLOAD = 10 pF, and CLOAD = 20 pF
G = +2
50mV/DIV
0102030405
TIME (ns)
0
RL = 150Ω,V
S = +5V AND ±5V
RL = 1kΩ,V
S = +5V AND ±5V
02866-045
Figure 45. Small Signal Transient Response for
RL = 150 Ω, RL = 1 kΩ and VS = +5 V, VS = ±5 V
G = –1
1V/DIV
0102030405
TIME (ns)
0
INPUT
OUTPUT
02866-046
Figure 46. Large Signal Transient Response, G = −1, RL = 150 Ω
50mV/DIV
499Ω
499Ω
200Ω
49.9Ω
R
SNUB
C
LOAD
+
–
G = +2
010 2030405
TIME (ns)
C
L
= 0pF
C
L
= 20pF C
L
= 20pF
R
SNUB
= 10Ω
02866-047
0
Figure 47. Small Signal Transient Response, Effect of Series Snub Resistor
when Driving Capacitive Load
AD8007/AD8008
Rev. E | Page 14 of 20
0 100 200
TIME (ns)
INPUT (1V/DIV)
OUTPUT (2V/DIV)
300 400 500
G = +2
+V
S
–V
S
R
L
= 150Ω
R
L
= 1kΩ
02866-048
Figure 48. Output Overdrive Recovery, RL = 1 kΩ, 150 Ω, VIN = ±2.5 V
0
TIME (ns)
5 1015 202530 354045
G = +2
0.1
0
SETTLINGTIME (%)
0.2
0.3
0.4
0.5
–0.1
–0.2
–0.3
–0.4
–0.5
18ns
02866-049
Figure 49. 0.1% Settling Time, 2 V Step
R
L
(Ω)
–1
2000
3
2
1
0
4
400 600
–2
–3
–4
800 1000
V
OUT
( V)
G = +10
V
S
= ±5V
V
IN
= ±0.75V
02866-050
Figure 50. VOUT Swing vs. RL, VS = ±5 V, G = +10, VIN = ±0.75 V
AD8007/AD8008
Rev. E | Page 15 of 20
THEORY OF OPERATION
The AD8007 (single) and AD8008 (dual) are current feedback
amplifiers optimized for low distortion performance. A simplified
conceptual diagram of the AD8007 is shown in Figure 51. It
closely resembles a classic current feedback amplifier comprised
of a complementary emitter-follower input stage, a pair of signal
mirrors, and a diamond output stage. However, in the case of
the AD8007/AD8008, several modifications were made to improve
the distortion performance over that of a classic current feedback
topology.
I
DI
–
+V
S
–V
S
C
J
1
C
J
2
Q1
Q2
IN–
–
–
–
D1
D2
I
1
I
2
IN+
I
3
I
4
I
DO
Q3
Q4
Q5
Q6
+V
S
–V
S
R
F
OUT
R
G
M2
M1
HIGH-Z
02866-051
Figure 51. Simplified Schematic of AD8007
The signal mirrors were replaced with low distortion, high
precision mirrors. In Figure 51, they are shown as M1 and M2.
Their primary function from a distortion standpoint is to reduce
the effect of highly nonlinear distortion caused by capacitances,
CJ1 and CJ2. These capacitors represent the collector-to-base
capacitances of the output devices of the mirrors.
A voltage imbalance arises across the output stage, as measured
from the high impedance node, high-Z, to the output node, OUT.
This imbalance is a result of delivering high output currents and
is the primary cause of output distortion. Circuitry is included
to sense this output voltage imbalance and generate a compensating
current, IDO. When injected into the circuit, IDO reduces the
distortion that could be generated at the output stage. Similarly, the
nonlinear voltage imbalance across the input stage (measured from
the noninverting to the inverting input) is sensed, and a current,
IDI, is injected to compensate for input-generated distortion.
The design and layout are strictly top-to-bottom symmetric to
minimize the presence of even-order harmonics.
USING THE AD8007/AD8008
Supply Decoupling for Low Distortion
Decoupling for low distortion performance requires careful
consideration. The commonly adopted practice of returning the
high frequency supply decoupling capacitors to physically separate
(and possibly distant) grounds can lead to degraded even-order
harmonic performance. This situation is shown in Figure 52 using
the AD8007 as an example; however, it is not recommended. For a
sinusoidal input, each decoupling capacitor returns to its ground a
quasi-rectified current carrying high even-order harmonics.
+V
S
–V
S
R
G
499Ω
R
S
200Ω
IN
R
F
499Ω
GND 1
GND 2
OUT
AD8007
+
+10µF
10µF
0.1µF
0.1µF
02866-052
Figure 52. High Frequency Capacitors Returned to Physically Separate
Grounds (Not Recommended)
The decoupling scheme shown in Figure 53 is recommended.
In Figure 53, the two high frequency decoupling capacitors are
first tied together at a common node and are then returned to
the ground plane through a single connection. By first adding
the two currents flowing through each high frequency decoupling
capacitor, this ensures that the current returned into the ground
plane is only at the fundamental frequency.
+V
S
–V
S
R
G
499Ω
R
S
200Ω
IN
R
F
499Ω
OUT
AD8007
+
+10µF
0.1µF
10µF
0.1µF
02866-053
Figure 53. High Frequency Capacitors Returned to Ground at a Single Point
(Recommended)
AD8007/AD8008
Rev. E | Page 16 of 20
Whenever physical layout considerations prevent the decoupling
scheme shown in Figure 53, the user can connect one of the
high frequency decoupling capacitors directly across the supplies
and connect the other high frequency decoupling capacitor to
ground (see Figure 54).
+VS
–VS
RG
499Ω
RS
200Ω
IN
RF
499Ω
OUT
AD8007
+
+
10µF
10µF
C1
0.1µF
C2
0.1µF
02866-054
Figure 54. High Frequency Capacitors Connected Across the Supplies
(Recommended)
LAYOUT CONSIDERATIONS
The standard noninverting configuration with recommended
power supply bypassing is shown in Figure 54. The 0.1 μF high
frequency decoupling capacitors should be X7R or NPO chip
components. Connect C2 from the +VS pin to the −VS pin.
Connect C1 from the +VS pin to signal ground.
The length of the high frequency bypass capacitor leads is critical.
Parasitic inductance due to long leads works against the low
impedance created by the bypass capacitor. The ground for the
load impedance should be at the same physical location as the
bypass capacitor grounds. For larger value capacitors, which are
intended to be effective at lower frequencies, the current return
path distance is less critical.
AD8007/AD8008
Rev. E | Page 17 of 20
LAYOUT AND GROUNDING CONSIDERATIONS
GROUNDING
A ground plane layer is important in densely packed printed
circuit boards (PCB) to minimize parasitic inductances. However,
an understanding of where the current flows in a circuit is critical
to implementing effective high speed circuit design. The length
of the current path is directly proportional to the magnitude of
parasitic inductances and thus the high frequency impedance of
the path. High speed currents in an inductive ground return
create unwanted voltage noise. Broad ground plane areas reduce
parasitic inductance.
INPUT CAPACITANCE
Along with bypassing and ground, high speed amplifiers can be
sensitive to parasitic capacitance between the inputs and ground.
Even 1 pF or 2 pF of capacitance reduces the input impedance at
high frequencies, in turn increasing the gain of the amplifier, which
causes peaking of the frequency response or even oscillations if
severe enough. Place the external passive components that are
connected to the input pins as close as possible to the inputs to
avoid parasitic capacitance. The ground and power planes must
be kept at a distance of at least 0.05 mm from the input pins on
all layers of the board.
OUTPUT CAPACITANCE
To a lesser extent, parasitic capacitances on the output can cause
peaking of the frequency response. The following two methods
minimize its effect:
• Put a small value resistor in series with the output to isolate
the load capacitance from the output stage of the amplifier
(see Figure 12).
• Increase the phase margin by increasing the gain of the
amplifier or by increasing the value of the feedback resistor.
INPUT-TO-OUTPUT COUPLING
To minimize capacitive coupling, the input and output signal
traces should not be parallel. When they are not parallel, they
help reduce unwanted positive feedback.
EXTERNAL COMPONENTS AND STABILITY
The AD8007/AD8008 are current feedback amplifiers and, to a
first order, the feedback resistor determines the bandwidth and
stability. The gain, load impedance, supply voltage, and input
impedances also have an effect.
Figure 11 shows the effect of changing RF on the bandwidth and
peaking for a gain of 2. Increasing RF reduces peaking but also
reduces bandwidth. Figure 6 shows that for a given RF increasing
the gain also reduces peaking and bandwidth. Table 4 shows the
recommended RF and RG values that optimize bandwidth with
minimal peaking.
Table 4. Recommended Component Values
Gain RF (Ω) RG (Ω) RS (Ω)
−1 499 499 200
+1 499 Not applicable 200
+2 499 499 200
+5 499 124 200
+10 499 54.9 200
The load resistor also affects bandwidth, as shown in Figure 7 and
Figure 10. A comparison between Figure 7 and Figure 10 also
demonstrates the effect of gain and supply voltage.
When driving loads with a capacitive component, stability
improves by using a series snub resistor, RSNUB, at the output.
The frequency and pulse responses for various capacitive
loads are illustrated in Figure 12 and Figure 47, respectively.
For noninverting configurations, a resistor in series with the
input, RS, is needed to optimize stability for a gain of 1, as
illustrated in Figure 8. For larger noninverting gains, the effect
of a series resistor is reduced.
AD8007/AD8008
Rev. E | Page 18 of 20
OUTLINE DIMENSIONS
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
COMPLIANT TO JEDEC STANDARDS MS-012-A A
012407-A
0.25 (0.0098)
0.17 (0.0067)
1.27 (0.0500)
0.40 (0.0157)
0.50 (0.0196)
0.25 (0.0099) 45°
8°
0°
1.75 (0.0688)
1.35 (0.0532)
SEATING
PLANE
0.25 (0.0098)
0.10 (0.0040)
4
1
85
5.00 (0.1968)
4.80 (0.1890)
4.00 (0.1574)
3.80 (0.1497)
1.27 (0.0500)
BSC
6.20 (0.2441)
5.80 (0.2284)
0.51 (0.0201)
0.31 (0.0122)
COPLANARITY
0.10
Figure 55. 8-Lead Standard Small Outline Package [SOIC_N]
Narrow Body
(R-8)
Dimensions shown in millimeters and (inches)
COMPLIANT TO JEDEC STANDARDS MO-187-AA
091709-A
6°
0°
0.70
0.55
0.40
4
8
1
5
0.65 BSC
0.40
0.25
1.10 MAX
3.20
3.00
2.80
COPLANARITY
0.10
0.23
0.13
3.20
3.00
2.80
5.15
4.90
4.65
PIN 1
IDENTIFIER
15° MAX
0.95
0.85
0.75
0.15
0.05
Figure 56. 8-Lead Mini Small Outline Package [MSOP]
(RM-8)
Dimensions shown in millimeters
AD8007/AD8008
Rev. E | Page 19 of 20
COMPLIANT TO JEDEC STANDARDS MO-203-AA
1.00
0.90
0.70
0.46
0.36
0.26
2.20
2.00
1.80
2.40
2.10
1.80
1.35
1.25
1.15
072809-A
0.10 MAX
1.10
0.80
0.40
0.10
0.22
0.08
312
45
0.65 BSC
COPLANARITY
0.10
SEATING
PLANE
0.30
0.15
Figure 57. 5-Lead Thin Shrink Small Outline Transistor Package [SC70]
(KS-5)
Dimensions shown in millimeters
ORDERING GUIDE
Model Temperature Range Package Description Package Outline Branding
AD8007AKS-R2 −40°C to +85°C 5-Lead SC70 KS-5 HTA
AD8007AKSZ-R21 −40°C to +85°C 5-Lead SC70 KS-5 HTC
AD8007AKSZ-REEL1 −40°C to +85°C 5-Lead SC70 KS-5 HTC
AD8007AKSZ-REEL71 −40°C to +85°C 5-Lead SC70 KS-5 HTC
AD8007AR −40°C to +85°C 8-Lead SOIC R-8
AD8007AR-REEL −40°C to +85°C 8-Lead SOIC R-8
AD8007AR-REEL7 −40°C to +85°C 8-Lead SOIC R-8
AD8007ARZ1 −40°C to +85°C 8-Lead SOIC R-8
AD8007ARZ-REEL1 −40°C to +85°C 8-Lead SOIC R-8
AD8007ARZ-REEL71 −40°C to +85°C 8-Lead SOIC R-8
AD8008AR −40°C to +85°C 8-Lead SOIC R-8
AD8008AR-REEL7 −40°C to +85°C 8-Lead SOIC R-8
AD8008AR-REEL −40°C to +85°C 8-Lead SOIC R-8
AD8008ARZ1 −40°C to +85°C 8-Lead SOIC R-8
AD8008ARZ-REEL71 −40°C to +85°C 8-Lead SOIC R-8
AD8008ARZ-REEL1 −40°C to +85°C 8-Lead SOIC R-8
AD8008ARM −40°C to +85°C 8-Lead MSOP RM-8 H2B
AD8008ARM-REEL −40°C to +85°C 8-Lead MSOP RM-8 H2B
AD8008ARM-REEL7 −40°C to +85°C 8-Lead MSOP RM-8 H2B
AD8008ARMZ1 −40°C to +85°C 8-Lead MSOP RM-8 H2B#
AD8008ARMZ-REEL1 −40°C to +85°C 8-Lead MSOP RM-8 H2B#
AD8008ARMZ-REEL71 −40°C to +85°C 8-Lead MSOP RM-8 H2B#
1 Z = RoHS Compliant Part, # denotes RoHS compliant part may be top or bottom marked.
AD8007/AD8008
Rev. E | Page 20 of 20
NOTES
©2002–2009 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D02866-0-11/09(E)
