Vishay Siliconix
SiP12202
Document Number: 73542
S-52332–Rev. B, 07-Nov-05
www.vishay.com
1
Synchronous Step Down Controller
FEATURES
• 2.7 V to 5.5 V Input Voltage Range
• Adjustable Output Voltage - 0.6 to 5.5 V
• For Converter loads up to 10 A
• High efficiency - 93 %
• Uses High Side P-Channel MOSFET
• Uses Low Side N-Channel MOSFET
• 500 kHz operation
• Internal Soft Start
• Power Good Indication
• Shutdown Pin
• Output Current Limit
• Minimum External Components
• MLP33-10 Package
APPLICATIONS
• Distributed Power
• Desktop & Notebook Computers
• Battery Operated Equipment
• Point of Load Regulation
• DSP Cores
DESCRIPTION
SiP12202 is a synchronous step down controller
designed for use in dc-dc converter circuits requiring
output currents as high as 10 amperes. SiP12202 is
designed to require a minimum number of external
components, simplifying design and layout. It accepts
input voltages from 2.7 V to 5.5 V, providing an adjust-
able output with voltage ranging from 0.6 V to 5.5 V.
SiP12202 includes a combination Compensation/
Shutdown pin. Protection features include undervolt-
age lockout, Power Good output, output current limit,
and thermal shutdown.
SiP12202 is available in a lead (Pb)-free MLP-33-10
package and is specified to operate over the range of
- 40 °C to 85 °C.
TYPICAL APPLICATION CIRCUIT
PGNDAGND
V
PG
COMP/SD
FB
DH
LX
DL
IN
V
IN
Power Good
Compensation/
Shutdown
GND
VIN
VOUT
AGND PGND
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Document Number: 73542
S-52332–Rev. B, 07-Nov-05
Vishay Siliconix
SiP12202
Notes
a. Device mounted with all leads soldered or welded to PC board
b. Derate 14 mW/°C above + 85 °C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only,
and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is
not implied. Exposure to absolute maximum rating/conditions for extended periods may affect device reliability.
ABSOLUTE MAXIMUM RATINGS
Parameter Limit Unit
VIN, LX to GND 6V
FB, PG, Comp/SD to GND - 0.3 to 6
Power Dissipationa, b 560 mW
Maximum Junction Temperature 125 °C
Storage Temperature - 55 to + 150
RECOMMENDED OPERATING RANGE
Parameter Limit Unit
Input Voltage Range 2.7 to 5.5 V
Output Voltage Adjustment Range 0.6 to 5.5
Operating Temperature Range - 40 to + 85 °C
SPECIFICATIONS
Parameter Symbol
Test Condition Unless Specified
VIN = 5.0
Limits
- 40 to 85 °C Unit
Mina TypbMaxa
Controller
Input Voltage VIN 2.7 5.5 V
Quiescent Current Non Switching 0.6 1 mA
Switching Oscillator Frequency fOSC 400 500 600 kHz
Oscillator Ramp Amplitude ΔVOSC 1V
Feedback Voltage VFB
TA = 25 °C 0.591 0.600 0.609 V
0.585 0.615
FB input Bias Current IFB 100 nA
Transconductance GM 2mA/V
Soft Start 4ms
Inputs and Outputs
SD Input Voltage VIL 0.15 V
Shutdown Current IIL 30 60 µA
MOSFET Drivers
Break-before-make-time tBBM 30 ns
Highside Driver
Output Voltage VDH 4.5 V
On resistance RDSHH VIN = 4.5 V 1.3 1.9 Ω
RDSHL VIN = 4.5 V 2.8 4.4 Ω
Rise time - PFET Turn On trH VIN = 5 V, CL = 2.7 nF 64 ns
Fall time - PFET Turn Off tfH VIN = 5 V, CL = 2.7 nF 8
Lowside Driver
Output Voltage VDL 4.5 V
On resistance RDSLH VIN = 4.5 V 5.5 8.2 Ω
RDSLL VIN = 4.5 V 0.85 1.4 Ω
Rise time - NFET Turn On trL VIN = 5 V, CL = 2.7 nF 83 ns
Fall time - NFET Turn Off tfL VIN = 5 V, CL = 2.7 nF 6.6
Document Number: 73542
S-52332–Rev. B, 07-Nov-05
www.vishay.com
3
Vishay Siliconix
SiP12202
NOTES:
a) The algebriac convention whereby the most negative value is a minimum and the most positive a maximum.
b) Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing.
PIN CONFIGURATION
Parameter Symbol
Test Condition Unless Specified
VIN = 5.0
Limits
- 40 to 85 °C Unit
Mina TypbMaxa
Protection
Under voltage lockout VUVLO Rising 2.3 2.4 2.5
UVLO-Hysteresis 0.10 V
Power Good
PG Output Voltage VPGOL ISINK = 0.5 mA 0.4 V
PG Leakage Current IPGOL VPG = 5 V 1µA
PG Voltage Threshold VETH 70 %VOUT
PG Threshold Hysteresis VEH 5%VOUT
Over Current Limit
Thermal Shutdown Temperature Rising 165 °C
Thermal Hysteresis 20 °C
MOSFET On Voltage Sense Threshold VDL With respect to VIN - 335 - 300 - 265 mV
SPECIFICATIONS
PIN DESCRIPTION
Part Number Name Function
1 COMP/SD Combination Compensation and Shut down pin
2 FB Feedback input
3 AGND Analog Ground
4PGIndicates that the output voltage is in regulation
5, 10 VIN Input voltage
6 DL Lowside gate drive
7 PGND Power Ground
8 LX Connection for the inductor node
9 DH Highside gate drive
ORDERING INFORMATION
Part Number Temperature Range Package
SiP12202DM-T1-E3 - 40 to 85 °C MLP33-10
Eva Kit Temperature Range Board
SiP12202DB - 40 to 85 °C Surface Mount
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Document Number: 73542
S-52332–Rev. B, 07-Nov-05
Vishay Siliconix
SiP12202
FUNCTIONAL BLOCK DIAGRAM
DETAILED OPERATIONAL DESCRIPTION
Enable/ON State:
The COMP/SD pin has 10 µA pull up current to ensure
auto startup as soon as the pin is released by the
external pull down MOS. When the internal reference
is ready, there will be a clamp current applied at
COMPSD; this is to ensure the COMPSD pin will not
go below 600 mV inadvertently due to the amplifier
excursion or noise. The COMPSD has to go above 600
mV to enable the chip fully.
Disable/Shutdown/Off State
To disable the chip, the COMP/SD pin has to pulled
below 150 mV typically and the external pull down
MOSFET has to be able to sink at least 250 µA. Once
the pin reaches a voltage below the 150 mV level, the
chip will go into shutdown mode with only essential
curcuitry alive and the current bias of the chip will be
cut down to 30 µA level typically. Both High Side and
Low Side Gates are off.
UVLO:
The chip enters into Under Voltage Lockout when VIN
is below 2.3 V (typical). Both High Side Gate and Low
Side Gate will be turned off. The chip will go out of
UVLO mode when VIN is above 2.4 V (typical).
Soft Start:
Once the chip is out of shutdown and UVLO mode the
soft start is initiated. The soft start is done accom-
plished by ramping up the internal reference. During
soft start mode the chip can not enter into fault mode.
If there is an over current condition (current limit condi-
tion), the High Side Gate will be turned off and the Low
Side will be turned on. Once the soft start timing
elapses, the chip enters into a normal state of opera-
tion.
Output Over Voltage State:
When the Output voltage goes above 1.083 times
nominal Output Voltage, the over voltage circuit will act
as a high speed clamp and the High Side Gate will be
turned off and the Low Side Gate will be on. The con-
dition will persist until the Output voltage drops below
the trigger voltage minus a hysteresis.
Output Over Current State:
The SiP12202 will enter a cycle by cycle over current
condition when the voltage on the LX pin falls below
VIN by 300 mV. During the over current condition the
High Side MOSFET is turned off for the duration of the
existing cycle. At the beginning of the next cycle the
High Side MOSFET turns on and the LX voltage is
measured again. If the over current condition still
exists, the High Side MOSFET is turned off again. This
is repeated seven consecutive times after which the IC
will go into a fault state. If the over current condition is
removed before seven consecutive cycles the IC
reverts to normal operating mode.
UVLO
Soft Start
OSC
500KHz
Vin
SD/Comp
Vin
DH
DL
FB
Agnd
LX
SiP12202
PG
0.45 V
Over Current
Sense
Shut Down
Gate Control
Logic
BBM
GM
Pgnd
PWM Comp
Comp
FB
0.6 V
Vin
ΔVosc
Over Temp Over Voltage
Document Number: 73542
S-52332–Rev. B, 07-Nov-05
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Vishay Siliconix
SiP12202
Fault State:
The IC can only enter into Fault mode after the soft
start mode has ended and seven consecutive over cur-
rent condition cycles has occurred. Once it enters the
Fault state, with the High Side MOSFET turned off and
the Low Side MOSFET turned on, any occurring over
current condition will be ignored. The Fault State will
last for seven soft start cycles. After which the IC will
enter Soft Start mode. If the over current condition is
removed the IC will operate normally, otherwise the
over current sequence is repeated. This fault scheme
minimizes thermal stress on the external power MOS-
FET switches
Over Temperature:
When the temperature of the chip goes above 165 °C,
the chip enters into over temperature shutdown. The
High Side gate will be off and the Low Side gate will be
on. Only system monitor circuitry will be active. Once
the temperature of the chip drops below 145 °C, the
chip enters into the normal operation mode.
Power Good:
Power Good State: When the output is above 0.75
times nominal output voltage, the PC signal will be
high to indicate that the output voltage is available for
external use. The PG pin requires a pull up resistor.
Setting the Output Voltage:
An output voltage between 0.6 V and VIN and can be
configured by connecting FB pin to a resistive divider
between the output and GND. Select resistor R2 in the
1 kΩ to 10 kΩ range. R1 is then given by:
where VFB = 0.6 V
TYPICAL CHARACTERISTICS
()
1
V
V
R
R
FB
OUT
21
−=
R
1
R
2
0.6 V
FB
V
OUT
EFFICIENCY vs LOAD CURRENT
LOAD CURRENT (A)
EFFICIENCY (%)
50
55
60
65
70
75
80
85
90
95
100
0246810
Vout = 2.5 V
Vout = 3.3 V
Vin = 5.0 V
OSCILLATOR FREQUENCY Vs TEMPERATURE
400
450
500
550
600
-45 -10 25 60 95 130
TEMPERATURE (°C)
FREQUENCY (kHz)
Vin = 5.0 V
Vin = 2.7 V
FEEDBACK THRESHOLD Vs TEMPERATURE
TEMPERATURE (°C)
VOLTAGE ( V)
0.585
0.595
0.605
0.615
-45 -10 25 60 95 130
Vin = 2.7 V to 5.0 V
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Document Number: 73542
S-52332–Rev. B, 07-Nov-05
Vishay Siliconix
SiP12202
TYPICAL CHARACTERISTICS
CURRENT SENSE VOLTAGE Vs TEMPERATURE
TEMPERATURE (°C)
VOLTAGE (mV)
- 340
- 320
- 300
- 280
- 260
- 45 - 10 25 60 95 130
Vin = 5.0 V
Vin = 2.7 V
UVLO Vs TEMPERATURE
TEMPERATURE (°C)
VOLTAGE ( V)
- 45 - 10 25 60 95 130
2.3
2.35
2.4
2.45
2.5
QUIESCENT CURRENT Vs TEMPERATURE
TEMPERATURE (°C)
CURRENT (mA)
- 45 - 10 25 60 95 130
0.4
0.6
0.8
Vin = 2.7 V
Vin = 5.0 V
FB INPUT BIAS CURRENT Vs TEMPERATURE
TEMPERATURE (°C)
CURRENT (nA)
- 45 - 10 25 60 95 130
- 10
- 5
0
5
10
Vin = 5.0 V
Vin = 2.7 V
SHUTDOWN CURRENT Vs TEMPERATURE
TEMPERATURE (°C)
CURRENT (mA)
- 45 - 10 25 60 95 130
10
20
30
40
50
Vin = 5.0 V
Vin = 2.7 V
POWER GOOD THRESHOLD Vs TEMPERATURE
TEMPERATURE (°C)
VOLTAGE (% VOUT)
- 45 - 10 25 60 95 130
70
75
80
Vin = 5.0 V
Vin = 2.7 V
Vishay Siliconix
SiP12202
Document Number: 73542
S-52332–Rev. B, 07-Nov-05
www.vishay.com
7
TYPICAL WAVEFORMS
1 µs/div
VIN = 5 V, VOUT = 2.5 V, Load Current = 5 A, L = 1.5 µH,
COUT = 220 µF x 2
Typical Switching Waveform
1 ms/div
VIN = 5 V, VOUT = 2.5 V, Load Current = 1 A,
Output Filter Cap = 220 µF x 2
Soft Start
1 ms/div
VIN = 5 V, VOUT = 2.5 V, Load Current = 1 A,
Output Filter Cap = 220 µF x 2
Shut Down
DH = 5 V/div
V
LX
= 5 V/div
DL = 5 V/div
Inductor Current
5 A/div
Comp/SD = 1 V/div
VOUT = 1 V/div
Inductor Current
5 A/div
PG = 5 V/div
Comp/SD = 1 V/div
V
OUT
= 1 V/div
Inductor Current
5 A/div
10 µs/div
VIN = 5 V, VOUT = 2.5 V, Load Current = 1 A to 8 A Step,
L = 1.5 µH, COUT = 220 µF x 2
Load Transient Response
1 µs/div
VIN = 5 V, VOUT = 2.5 V, Load Current = 1 A,
L = 1.5 µH, COUT = 220 µF x 2
Output Voltage Ripple
V
OUT
= 500 mV/div
Inductor Current
5 A/div
V
OUT
= 20 mV/div
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Document Number: 73542
S-52332–Rev. B, 07-Nov-05
Vishay Siliconix
SiP12202
APPLICATION NOTES
Inductor Selection:
An inductor is one of the energy storage component in a
converter. Choosing an inductor means specifying its
size, structure, material, inductance, saturation level,
dc-resistance (DR.), and core loss. Fortunately, there
are many inductor vendors that offer wide selections
with ample specifications and test data, such as Vishay
Dale.
The following are some key parameters that users
should focus on. In PWM mode, inductance has a direct
impact on the ripple current. The peak-to-peak inductor
ripple current can be calculated as
where f = switching frequency.
Higher inductance means lower ripple current, lower
current, lower voltage ripple on both input and output,
and higher efficiency, unless the resistive loss of the
inductor dominates the overall conduction loss. How-
ever, higher inductance also means a bigger inductor
size and a slower response to transients. In PSM mode,
inductance affects inductor peak current, and conse-
quently impacts the load capability and switching fre-
quency. For fixed line and load conditions, higher
inductance results in a lower peak current for each
pulse, a lower load capability, and a higher switching fre-
quency.
The saturation level is another important parameter in
choosing inductors. Note that the saturation levels spec-
ified in data sheets are maximum currents. For a dc-to-
dc converter operating in PWM mode, it is the maximum
peak inductor current that is relevant, and which can be
calculated using these equations:
This peak current varies with inductance tolerance and
other errors, and the rated saturation level varies over
temperature. So a sufficient design margin is required
when choosing current ratings.
A high-frequency core material, such as ferrite, should
be chosen, the core loss could lead to serious efficiency
penalties. The DCR should be kept as low as possible to
reduce conduction losses.
Input Capacitor Selection:
To minimize current pulse induced ripple caused by the
step-down controller and interference of large voltage
spikes from other circuits, a low-ESR input capacitor is
required to filter the input voltage. The input capacitor
should be rated for the maximum RMS input current:
It is common practice to rate for the worst-case RMS rip-
ple that occurs when the duty cycle is at 50%:
Output Capacitor Selection:
The selection of the output capacitor is primarily deter-
mined by the ESR required to minimize voltage ripple
and current ripple. The desired output ripple ΔVOUT can
be calculated by:
Current ripple can be calculated by:
Where: ΔVOUT = Desired Output Ripple Voltage
f = switching frequency
Imax = Maximum Inductor Current
Imin = Minimum Inductor Current
T = Switching Period
Multiple capacitors placed in parallel may be needed to
meet the ESR requirements. However if the ESR is too
low it can cause instability.
MOSFET Selection:
The key selection criteria for the MOSFETs include max-
imum specifications for on-resistance, drain-source volt-
age, gate source, current, and total gate charge Qg.
While the voltage ratings are fairly straightforward, it is
important to carefully balance on-resistance and gate
charge. In typical MOSFETs, the lower the on-resis-
tance, the higher the gate charge. The power loss of a
MOSFET consists of conduction, gate charge, and
crossover losses. For lower-current application, gate
charge losses become a significant factor, so low gate
charge MOSFETs, such as Vishay Siliconix's LITTLE
FOOT family of PWM-optimized devices, are desirable.
()
Lf
V
V
VV
I
IN
OUT
INOUT
PP
−
=
−
2
I
II
PP
OUTPK
−
+=
⎟
⎠
⎞
⎜
⎝
⎛
=
IN
OUT
IN
OUT
LOAD(max)RMS
V
V
1-
V
V
I
I
2
I
I
LOAD(max)
RMS
=
()
⎟
⎠
⎞
⎜
⎝
⎛
+
=
Δ
OUT
minmax
8fC
1
ESR
I
-I
VOUT
() )
VV
(
V
V
L
T
I
-I OUT
-
IN
IN
OUT
minmax =
Vishay Siliconix
SiP12202
Document Number: 73542
S-52332–Rev. B, 07-Nov-05
www.vishay.com
9
Compensation:
The SiP12202 uses voltage mode control in conjunction
with a high frequency Transconductance error amplifier.
The voltage feedback loop is compensated at the Comp/
SD pin, which is the output node of the error amplifier.
The feedback loop is generally compensated with an RC
+ C (one pole, one zero) network from comp to GND.
Loop stability is affected by the values of the inductor,
the output capacitor, the output capacitor ESR, and the
error amplifier compensation network.
The ideal Bode plot for a compensated system would be
gain that rolls off at a slope of - 20 dB/decade, crossing
0 dB at the desired bandwidth and a phase margin
greater than 90° for all frequencies below the 0 dB cros-
sing.
The compensation network used with the error amplifier
must provide enough phase margin at the 0 dB cross-
over frequency for the overall open-loop transfer func-
tion to be stable. The following guidelines will calculate
the compensation pole and zero to stabilize the
SiP12201.
The inductor and output capacitor values are usually
determined by efficiency, voltage and current ripple
requirements. The inductor and the output capacitor cre-
ate a double pole at the frequency and a -180° phase
change:
The ESR of the output capacitor and the output capaci-
tor value form a zero at the frequency:
The fZ(ESR) typically should be higher than the fp(LC) and
give a 90° phase boost. R3 and C1 will establish the sec-
ond zero of the system. The frequency of the zero
should be 2 x lower than the double pole frequency of
the inductor and the output capacitor.
Choose a value for R3 usually between 1 kΩ and 10 kΩ.
This second zero will provide the second 90° phase
boost and will stabilize the closed loop system.
The second pole should be placed at ½ the switching
frequency.
Although a mathematical approach to frequency com-
pensation can be used, the added complication of input
and/or output filters, unknown capacitor ESR, and gross
operating point changes with input voltage, load current
variations, all suggest a more practical empirical me-
thod. This can be done by injecting at the load a variable
frequency small signal voltage between the output and
the feedback network and using an RC network box to
iterate toward the final values; or by obtaining the opti-
mum loop response using a network analyzer to mea-
sure the loop Gain and Phase.
Layout:
As in the design of any switching dc-to-dc converter,
driver careful layout will ensure that there is a successful
transition from design to production. One of the few
drawbacks of switching dc-to-dc converters is the noise
induced by their high-frequency switching. Parasitic
inductance and capacitance may become significant
when a converter is switching at 500 kHz. However,
GM
ΔVosc
0.6 V
PWM Comp
ESR
R1
R2 R3
L
C2 C
OUT
C1
V
IN
V
OUT
V
OUT
OSC
500 kHz
FB Compensation
OUT
p(LC)
CL2
1
f
π
=
)ESR)(C
(
2
1
f
OUT
Z(ESR)
π
=
R3C1
2
1
fZ(comp)
π
=
C
2
R
3
2
1
=
π
f
p(comp)
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Document Number: 73542
S-52332–Rev. B, 07-Nov-05
Vishay Siliconix
SiP12202
noise levels can be minimized by properly laying out the
components. Here are some general guidelines for lay-
ing out a step-down converter with the SiP12202. Since
power traces in step down converters carry pulsating
current, energy stored in trace inductance during the
pulse can cause high-frequency ringing with input and
output capacitors. Minimizing the length of the power
traces will minimize the parasitic inductance in the trace.
The same pulsating currents can cause voltage drops
due to the trace resistance and cause effects such as
ground bounce. Increasing the width of the power trace,
which in-creases the cross sectional area, will minimize
the trace resistance. In all dc-to-dc converters the de-
coupling capacitors should be placed as close as possi-
ble to the pins being decoupled to reduce the noise. The
connections to both terminals should be as short as pos-
sible with low-inductance (wide) traces. In the SiP12202
converters, the VIN is decoupled to PGND. It may be
necessary to decouple VDD to AGND, with the decoup-
ling capacitor being placed adjacent to the pins. AGND
and PGND traces should be isolated from each other
and only connected at a single node such as a "star
ground".
Document Number: 91000 www.vishay.com
Revision: 18-Jul-08 1
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All product specifications and data are subject to change without notice.
Vishay Intertechnology, Inc., its affiliates, agents, and employees, and all persons acting on its or their behalf
(collectively, “Vishay”), disclaim any and all liability for any errors, inaccuracies or incompleteness contained herein
or in any other disclosure relating to any product.
Vishay disclaims any and all liability arising out of the use or application of any product described herein or of any
information provided herein to the maximum extent permitted by law. The product specifications do not expand or
otherwise modify Vishay’s terms and conditions of purchase, including but not limited to the warranty expressed
therein, which apply to these products.
No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this
document or by any conduct of Vishay.
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