SEMICONDUCTOR
7-1
September 1996
CA3083
General Purpose High Current
NPN Transistor Array
Features
• High IC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100mA (Max)
•Low V
CE sat (at 50mA). . . . . . . . . . . . . . . . . . 0.7V (Max)
• Matched Pair (Q1 and Q2)
-V
IO (VBE Match). . . . . . . . . . . . . . . . . . . . . . .±5mV (Max)
-I
IO (at 1mA) . . . . . . . . . . . . . . . . . . . . . . . . 2.5µA (Max)
• 5 Independent Transistors Plus Separate Substrate
Connection
Applications
• Signal Processing and Switching Systems Operating
from DC to VHF
• Lamp and Relay Driver
• Differential Amplifier
• Temperature Compensated Amplifier
• Thyristor Firing
• See Application Note AN5296 “Applications of the
CA3018 Circuit Transistor Array” for Suggested
Applications
Description
The CA3083 is a versatile array of five high current (to
100mA) NPN transistors on a common monolithic substrate.
In addition, two of these transistors (Q1 and Q2) are
matched at low current (i.e., 1mA) for applications in which
offset parameters are of special importance.
Independent connections for each transistor plus a separate
terminal for the substrate permit maximum flexibility in circuit
design.
Pinout
CA3083
(PDIP, CERDIP, SOIC)
TOP VIEW
Ordering Information
PART NUMBER
(BRAND) TEMP.
RANGE (oC) PACKAGE PKG.
NO.
CA3083 -55 to 125 16 Ld PDIP E16.3
CA3083F -55 to 125 16 Ld CERDIP F16.3
CA3083M
(3083) -55 to 125 16 Ld SOIC M16.15
CA3083M96
(3083) -55 to 125 16 Ld SOIC Tape
and Reel M16.15
14
15
16
9
13
12
11
10
1
2
3
4
5
7
6
8
SUBSTRATE
Q1
Q2
Q3
Q4
Q5
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright © Harris Corporation 1996 File Number 481.3
7-2
Absolute Maximum Ratings Thermal Information
The following ratings apply for each transistor in the device:
Collector-to-Emitter Voltage, VCEO . . . . . . . . . . . . . . . . . . . . . . 15V
Collector-to-Base Voltage, VCBO . . . . . . . . . . . . . . . . . . . . . . . . 20V
Collector-to-Substrate Voltage, VCIO (Note 1) . . . . . . . . . . . . . . 20V
Emitter-to-Base Voltage, VEBO . . . . . . . . . . . . . . . . . . . . . . . . . . 5V
Collector Current (IC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .100mA
Base Current (IB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20mA
Operating Conditions
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC
Thermal Resistance (Typical, Note 2) θJA (oC/W) θJC (oC/W)
CERDIP Package . . . . . . . . . . . . . . . . 135 65
PDIP Package . . . . . . . . . . . . . . . . . . . 135 N/A
SOIC Package. . . . . . . . . . . . . . . . . . . 200 N/A
Maximum Power Dissipation (Any One Transistor) . . . . . . . . 500mW
Maximum Junction Temperature (Hermetic Package) . . . . . . . . 175oC
Maximum Junction Temperature (Plastic Package) . . . . . . . . 150oC
Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC
Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . . 300oC
(SOIC - Lead Tips Only)
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
1. The collector of each transistor of the CA3083 is isolated from the substrate b y an integ r al diode . The substr ate m ust be connected to a
voltage which is more negativ e than any collector v oltage in order to maintain isolation between tr ansistors and provide normal transistor
action. To avoid undesired coupling between transistors, the substrate Terminal (5) should be maintained at either DC or signal (AC)
ground. A suitable bypass capacitor can be used to establish a signal ground.
2. θJA is measured with the component mounted on an evaluation PC board in free air.
Electrical Specifications For Equipment Design, TA = 25oC
PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS
FOR EACH TRANSISTOR
Collector-to-Base Breakdown Voltage V(BR)CBO IC = 100µA, IE = 0 20 60 - V
Collector-to-Emitter Breakdown Voltage V(BR)CEO IC = 1mA, IB = 0 15 24 - V
Collector-to-Substrate Breakdown Voltage V(BR)CIO ICI = 100µA, IB = 0, IE = 0 20 60 - V
Emitter-to-Base Breakdown Voltage V(BR)EBO IE = 500µA, IC = 0 5 6.9 - V
Collector-Cutoff-Current ICEO VCE = 10V, IB = 0 - - 10 µA
Collector-Cutoff-Current ICBO VCB = 10V, IE = 0 - - 1 µA
DC Forw ard-Current Transfer Ratio (Note 3) (Figure 1) h FE VCE = 3V IC = 10mA 40 76 -
IC = 50mA 40 75 -
Base-to-Emitter Voltage (Figure 2) VBE VCE = 3V, IC = 10mA 0.65 0.74 0.85 V
Collector-to-Emitter Saturation Voltage (Figures 3, 4) VCE SAT IC = 50mA, IB = 5mA - 0.40 0.70 V
Gain Bandwidth Product fTVCE = 3V, IC = 10mA - 450 - MHz
FOR TRANSISTORS Q1 AND Q2(As a Differential Amplifier)
Absolute Input Offset Voltage (Figure 6) |VIO|V
CE = 3V, IC = 1mA - 1.2 5 mV
Absolute Input Offset Current (Figure 7) |IIO|V
CE = 3V, IC = 1mA - 0.7 2.5 µA
NOTE:
3. Actual forcing current is via the emitter for this test.
CA3083
7-3
Typical Performance Curves
FIGURE 1. hFE vs ICFIGURE 2. VBE vs IC
FIGURE 3. VCE SAT vs ICFIGURE 4. VCE SAT vs IC
FIGURE 5. VBE SAT vs ICFIGURE 6. VIO vs IC (TRANSISTORS Q1 AND Q2 AS A
DIFFERENTIAL AMPLIFIER)
VCE = 3V
COLLECTOR CURRENT (mA)
DC FOR WARD CURRENT TRANSFER RATIO
TA = 0oC
TA = 25oC
0.1 1 10 100
60
50
70
80
90
100
TA = 70oC
VCE = 3V
COLLECTOR CURRENT (mA)
BASE-TO-EMITTER VOLTAGE (V)
TA = 70oC
TA = 25oC
0.1 1 10 100
0.6
0.5
0.7
0.8
0.9
TA = 0oC
hFE = 10, TA = 25oC
COLLECTOR CURRENT (mA)
COLLECTOR-TO-EMITTER
1 10 100
0.2
0
0.4
0.6
0.8
1
MAXIMUM
TYPICAL
SATURATION VOLTAGE (V)
COLLECTOR CURRENT (mA)
COLLECTOR-TO-EMITTER
1 10 100
0.2
0
0.4
0.6
0.8
1
1.2
MAXIMUM
hFE = 10, TA = 70oC
TYPICAL
SATURATION VOLTAGE (V)
hFE = 10, TA = 25oC
COLLECTOR CURRENT (mA)
BASE-TO-EMITTER
1 10 100
0.6
0.5
0.7
0.8
0.9
1
SATURATION VOLTAGE (V)
VCE = 3V, TA = 25oC
COLLECTOR CURRENT (mA)
ABSOLUTE INPUT OFFSET V OLTAGE (mV)
0.1 1 10
1
0
2
3
4
5
6
CA3083
7-4
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Harris Semiconductor products are sold by description only. Harr is Semiconductor reserves the right to make changes in circuit design and/or specifications at
any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Harris is
believed to be accurate and reliable. However, no responsibility is assumed by Harris or its subsidiaries for its use; nor for any infringements of patents or other
rights of third parties which ma y result from its use . No license is g r anted b y implication or otherwise under any patent or patent rights of Harris or its subsidiaries.
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SEMICONDUCTOR
FIGURE 7. IIO vs IC (TRANSISTORS Q1 AND Q2 AS A DIFFERENTIAL AMPLIFIER)
Typical Performance Curves
(Continued)
VCE = 3V, TA = 25oC
COLLECTOR CURRENT (mA)
ABSOLUTE INPUT OFFSET CURRENT (µA)
0.1 1 10
1
10
0.1
CA3083
