AMD SempronTM Processor Product Data Sheet * * Compatible with Existing 32-Bit Code Base - Including support for SSE, SSE2, SSE3*, MMXTM, 754-Pin Package Specific Features 3DNow!TM technology and legacy x86 instructions *SSE3 supported by Rev. E and later processors * Refer to the AMD Functional Data Sheet, - Runs existing operating systems and drivers 754-Pin Package, order# 31410, for functional, - Local APIC on-chip electrical, and mechanical details of 754-pin package processors. AMD64 Technology (Supported by Rev. E3 and later processors) - AMD64 technology instruction set extensions - 64-bit integer registers, 48-bit virtual addresses, 40-bit physical addresses - Eight additional 64-bit integer registers (16 total) - Eight additional 128-bit SSE registers (16 total) * Packaging - 754-pin lidded micro PGA - 1.27-mm pin pitch - 29x29-row pin array - 40mm x 40mm organic substrate - Organic C4 die attach * 64-Kbyte 2-Way Associative ECC-Protected L1 Data Cache - Two 64-bit operations per cycle, 3-cycle latency * * 64-Kbyte 2-Way Associative Parity-Protected L1 Instruction Cache * 256-Kbyte 16-Way Associative ECC-Protected L2 Cache - Exclusive cache architecture--storage in addition to L1 caches Integrated Memory Controller - Low-latency, high-bandwidth - 72-bit DDR SDRAM at 100, 133, 166, and 200 MHz - Supports up to three unbuffered DIMMs - ECC checking with double-bit detect and single-bit correct * Electrical Interfaces - HyperTransportTM technology: LVDS-like differential, unidirectional - DDR SDRAM: SSTL_2 per JEDEC specification - Clock, reset, and test signals also use DDR SDRAM-like electrical specifications * Machine Check Architecture - Includes hardware scrubbing of major ECC-protected arrays * Power Management - Multiple low-power states - System Management Mode (SMM) - ACPI-compliant, including support for processor performance states * HyperTransportTM Technology to I/O Devices - One 16-bit link supporting speeds up to 800 MHz (1600 MT/s) or 3.2 Gigabytes/s in each direction Publication # Issue Date: 31805 Revision: September 2006 3.05 Advanced Micro Devices AMD SempronTM Processor Product Data Sheet 939-Pin Package Specific Features * * * * 2 Refer to the AMD Functional Data Sheet, 939-Pin Package, order# 31411, for functional, electrical, and mechanical details of 939-pin package processors Packaging - 939-pin lidded micro PGA - 1.27-mm pin pitch - 31x31-row pin array - 40mm x 40mm organic substrate - Organic C4 die attach 31805 Socket AM2 Processor Specific Features * Refer to the Socket AM2 Processor Functional Data Sheet, order# 31117, for functional and mechanical details of socket AM2 processors. Refer to the AMD NPT Family 0Fh Processor Electrical Data Sheet, order# 31119, for electrical details of socket AM2 processors. * Packaging - Lidded micro PGA - 1.27-mm pin pitch - 31x31 grid array - Compliant with RoHS (EU Directive 2002/95/EC) with lead used only in small amounts in specifically exempted applications Integrated Memory Controller - Low-latency, high-bandwidth - 144-bit DDR SDRAM at 100, 133, 166, and 200 MHz - Supports up to four unbuffered DIMMs * - ECC checking with double-bit detect and single-bit correct Electrical Interfaces - HyperTransportTM technology: LVDS-like differential, unidirectional - DDR SDRAM: SSTL_2 per JEDEC specification - Clock, reset, and test signals also use DDR SDRAM-like electrical specifications Rev. 3.05 September 2006 * Integrated Memory Controller - Low-latency, high-bandwidth - 128-bit DDR2 SDRAM controller operating at up to 333 MHz - Supports up to four unbuffered DIMMs Electrical Interfaces - HyperTransportTM technology: LVDS-like differential, unidirectional - DDR2 SDRAM: SSTL_1.8 per JEDEC specification - Clock, reset, and test signals also use DDR2 SDRAM-like electrical specifications 31805 Rev. 3.05 AMD SempronTM Processor Product Data Sheet September 2006 Revision History Date Revision Description September 2006 3.05 Third public release. Added RoHS compliance statement to Socket AM2 Processor Specific Features. June 2006 3.03 Second public release. Added AMD64 technology and SSE3 support. Added 939-pin package and socket AM2 processor information. Added revision history. August 2004 3.00 Initial public release. (c) 2004 - 2006 Advanced Micro Devices, Inc. All rights reserved. The contents of this document are provided in connection with Advanced Micro Devices, Inc. ("AMD") products. AMD makes no representations or warranties with respect to the accuracy or completeness of the contents of this publication and reserves the right to make changes to specifications and product descriptions at any time without notice. The information contained herein may be of a preliminary or advance nature and is subject to change without notice. No license, whether express, implied, arising by estoppel or otherwise, to any intellectual property rights is granted by this publication. Except as set forth in AMD's Standard Terms and Conditions of Sale, AMD assumes no liability whatsoever, and disclaims any express or implied warranty, relating to its products including, but not limited to, the implied warranty of merchantability, fitness for a particular purpose, or infringement of any intellectual property right. AMD's products are not designed, intended, authorized or warranted for use as components in systems intended for surgical implant into the body, or in other applications intended to support or sustain life, or in any other application in which the failure of AMD's product could create a situation where personal injury, death, or severe property or environmental damage may occur. AMD reserves the right to discontinue or make changes to its products at any time without notice. Trademarks AMD, the AMD Arrow logo, AMD Sempron, and combinations thereof, and 3DNow! are trademarks of Advanced Micro Devices, Inc. HyperTransport is a licensed trademark of the HyperTransport Technology Consortium. MMX is a trademark of Intel Corporation. Other product names used in this publication are for identification purposes only and may be trademarks of their respective companies. 3