HIGH-SPEED IDT7024S/L 4K x 16 DUAL-PORT STATIC RAM Features * 1DT7024 easily expands data bus width to 32 bits or more * True Dual-Ported memory cells which allow simultaneous using the Master/Slave select when cascading more than reads of the same memory location one device * High-speed access * MIS =H for BUSY output flag on Master ~ Military: 20/25/35/55/70ns (max.) WS = L for BUSY input on Slave ~ Industrial: 55ns (max.) * Interrupt Flag On-chip port arbitration logic Full on-chip hardware support of semaphore signaling ~ Commercial: 15/1 7/20/25/35/55ns (max.} * Low-power operation od - 10770248 between ports Active: 750mW (typ.) * Fully asynchronous operation from either port Standby: 5mW (typ.) * Battery backup operation2V data retention - IDT70241. * TTL-compatible, single 5V (t10%) power supply Active: 750mW (typ.) * Available in 84-pin PGA, Flatpack, PLCC, and 100-pin Thin Standby: 1mW {typ.) Quad Flatpack * Separate upper-byte and lower-byte contro! for multiplexed | * Industrial temperature range (40 C to +85 ) is available bus compatibility for selected speeds Functional Block Diagram AIL RWa UBL UBR CB. CBr CEL CER OEL OER V/Osr-1/O15t /Osr-1/O15R vO re VvOoL-VO7L Control Control VvOor-VO7R BUSY. Busya AML 3 MEMORY Address AtIR AOL ARRAY Decoder Aor ARBITRATION __ INTERRUPT CER SEMAPHORE OER LOGIC RWA SEML _ SEMR INT? MS NTR? 2740 drw 01 NOTES: 1. (MASTER): BUSY is output; (SLAVE): BUSY is input. 2. BUSY outputs and INT outputs are non-tri-stated push-pull. JANUARY 1999 1999 integrated Device Technology. inc. DSC 2738/8OR wate rie High-Speed 4K x 16 Duai-Por Description The IDT7024 is a high-speed 4Kx 16 Dual-Port Static RAM. The 1DT7024 is designed tobe used asa stand-alone 64K-bit Dual-Port RAM of as a combination MASTER/SLAVE Dual-Port RAM for 32-bit or more word systems. UsingtheIDT MASTER/SLAVE Dual-Port RAM approach in 32-bit or wider memory system applications results in full-speed, error- free operation without the need for additional discrete logic. This device provides two independent ports with separate control, address, and /O pins that permitindependent, asynchronous access for reads or writes to any location in memory. An automatic power down feature controlled by chip enable (CE) permits the on-chip circuitry ofeach Py Aa. PyAn. 1DT7024J or F Ao Q) swe, eee Fist. [) BUSY. ["] GND PIMs 1 BUSA Hitt 7) Aor Pain [7 Aan CJ A3a LC) Aas [J ASA f) AeA 84-Pin PLCC / Flatpack Top View) NOTES: 1. Ali Vec pins must be connected to the power supply. 2. All GND pins must be connected to the ground supply. 3. J84-1 package body is approximately 1.15 in x 1.15 in x .17 in. F84-2 package body is approximately 1.17 in x 1.17 in x .11 in. PN100-1 package body is approximately 14mm x 14mm x 1.4mm. 4. This package code is used to reference the package diagram. 5. This text does not indicate orientation of the actual part-marking. 2740 drw 02 \ eee ee i nercial jemperature Ranges port to enter a very low standby power mode. Fabricated using IDT's CMOS high-performance technology, these devices typically operate on only 750mW of power. Low-power (L) versions offer battery backup data retention capability with typical power consumption of 500yW froma 2V battery. TheIDT7024 is packaged in aceramic 84-pin PGA, an84-pin Flatpack and PLCC, and a 100-pin TOFP. Military grade product is manufactured incompliance with the latestrevision of MIL-PRF-38535 QML, makingit ideally suited to military temperature applications demanding the highest level of performance and reliability. index wees noc NCS NIC vO. vOMmES V2.0 Vow GNDcS VOuLco vO {DT?7024PF Voor PNioo-1(4) GNOco vOorr vORcS VOernc Veco (OsRe /O4neS VOsRm /Oernc wCrcS 100-Pin TQFP Top View5)OR MACs Sots! High-Speed 4 16 Dual-Pori St; wg he Pin Configurations" *) (con't.) Miulfaiy. ndustial ana Comercial lemperature Ranges 63 1 80 5& 55 34 St 4g 46 4s 43 11) von | vos. | vOu | vOa | vOo | OE | SEM LB. Ant | Ato Ar 66 64 a2 59 58 49 50 a7 44 a3 490 10} yoru | vos | vO | vos | von | UB | TR | NC | An | aw | as a7 88 57 33 52 4 a9 8 | youn | vost GND | Veco | RAL As. Mat 63 a3 38 37 98 | vous, | vor ASL Aa 72 71 73 33 35 34 97 | vors. | vou | vec BUSY. | Ao iNT. 1OT7024G 75 70 74 G34-3(4) 32 4 36 96 | voor | GND | GND 84-Pin PGA eno | MS | an 76 7? 78 Top View(5) 28 29 30 % |} voir | voer | Voc Aon | NTR | BUSYa 73 80 26 a7 041 Vosr | vOsR AaR AiR 81 a3 7 "1 12 j 23 25 03) YOsR | VOrA GND | GND | SEMa | Asa | Agr | 22 1 2 5 a 10 14 ia 20 22 2a 02) vOsr | vOsr | vOroR | vO1sR | VOrsR | RAR | OBe ' Aun | Asn | Asa Aar 4 3 4 8 9 15 13 116 18 19 at O1 | WOsR | VOR | VOR | YOR | C&R | TBR | CER ; NIC | Aor | Ask | Ara A B c D E F G H J K L Index 27 AD dew O4 NOTES: 1. All Vcc pins must be connected to the power supply. 2. Ail GND pins must be connected to the ground supply. 3. Package body is approximately 1.12 in x 1.12 in x .16 in. 4. This package code is used to reference the package diagram. 5. This text does not indicate orientation of the actual part-marking. Pin Names Maximum Operating Temperature 1,2) Left Port Right Port Names and Supply Voltagd , CE CER Chip Enable Grade Ambient GND Vec Temperature RW RYWR Read/Write Enable Military 55C to +125C ov 5.0V + 10% OEL OER Output Enable - Commercial 0C to +70C OV 5.0V + 10% Aan - Atte Aor - AiR Address Industrial 40C to +85C ov 5.0V + 10% VOot - YOu: VOor - /O15R Data Input/Output NOTES: 2740 thi 02 SEML SEMR Semaphore Enable 1. This is the parameter Ta. UB. UBr Upper Byte Select 2. industrial temperature: for specific speeds, packages and powers contact your sales office CB. {Br Lower Byte Select INTL INTR interrupt Flag USYL BUSYR Busy Flag MWS Master or Slave Select Vec Power GNO Ground 7740 bt 01IDT7O24S/. batts ibt~t Slot -1e kL. Sa ome OLPICL) i ioe ee Lite LEE ESRT: sae ee) SURE cEee Leer e Mats tine Lot) Truth Table I: Non-Contention Read/Write Control inputs Outputs CE RW OE UB iB SEM Oss 100-7 Mode H X x x X H High-Z High-Z Deseicted: Power-Down xX X Xx H H H High-Z High-Z Both Bytes Deselected L L X L H H DATAN High-Z Write to Upper Byte Only L L Xx H L H High-Z DATAIN Write to Lower Byte Only L L X L L H DATAIN DATAIN Write to Both Bytes L H L L H H DATAouT High-Z Read Upper Byte Only L H L H L H High-Z DATAcur =| Read Lower Byte Only L H L L L H DATAout DATAcut | Read Both Bytes x Xx H X x Xx High-Z HighZ | Outputs Disabled 2740 bt 03 NOTE: 1. Ao. Ant # Aor - AiR Truth Table Il: Semaphore Read/Write Contrdl) Inputs" Outputs Cee RW OE UB iB SEM 1108-15 00-7 Mode H H L x xX L DATAout DATAour =| Read Semaphore Fiag Data Out X H L H H L DATAout DATAouT =| Read Semaphore Flag Data Out H tT xX x x L DATAN DATAN | Write /Oo into Semaphore Flag X tT xX H H L DATAIN DATAIN Write /Oo into Semaphore Fiag L x X L x L Not Allowed L X Xx x L L - - Not Allowed 2740 ti 04 NOTE: 1. There are eight semaphore flags written to via Oo and read from all of the '/0's (Vo - 1/015) These eight semaphores are addressed by Ao - Az. Absolute Maximum Ratings") Recommended DC Operating Symbol Rating Commercial Militay | uit| Conditions & Industrial Symboi Parameter Min. | Typ. | Max } Unit VreRM) _ | Terminal Voltage 05t0+7.0 | 05p+70 | V VV 45 55 | vy with Respect Vcc | Supply Voltage . 5.0 . to GND GND | Ground 0 0 0 Vv TBS Temperature $510 +125 | 651 +135 | C Vix | input High Voltage 22 | | 60] v Under Bias Vi. | input Low Voltage o5. ) | o8 | Vv TstG Storage -65 to +125 65 to +150 C Temperature NOTES: 2740 tht 06 1. Vu > -1.5V for pulse width less than 10ns. ut 50 50 mA 2 pu on Gueet 2. VTerM must not exceed Vcc + 10%. NOTES: mons 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any olher conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. VTERM must not exceed Vcc +10% for more than 25% of the cycle time or 10ns maximum, and is limited to < 20mA for the period over Vrerm > Vcc + 10%.IDT7024S/1 High-Speed 4K x 16 Gual-Porl Static RATA Capacitance(Ta = +25C, f = 1.0MHzj") il ere le Tere meet lal leinperaiuie Ranges Symbol! Parameter Conditions | Max. | Unit Cn Input Capacitance Vin = 3dV 9 pF Cout | Output Capacitance Vout = 3dV 10 oF NOTES: var 1, This parameter are determined by device characterization, but is not production tested. 2. 3dV references the interpolated capacitance when the input and output signals switch from OV to 3V or from 3V to OV. DC Electrical Characteristics Over the Operating Temperature and Supply Voltage Rang@vcc = 5.0v + 10%) 7024S 7024. Symbol Parameter Test Conditions Min. Max. Min. Max. Unit Hhuf Input Leakage Current) Vcc = 5.5V, Vin = OV to Voc o 10 - 5 HA tho Output Leakage Current CE = Vi, Vout = OV to Voc 10 -- 5 pA VoL Output Low Voltage lo. = +4mA ~ 0.4 - 0.4 v VoH Output High Voltage lou = ~4mA 24 ~ 24 Vv NOTE: 740 tbl 08 1. At Vcc < 2.0V input leakages are undefined. DC Electrical Characteristics Over the Operating Temperature and Supply Voltage Rang@) (vcc = 5.0V + 10%) 7024X15 7024X17 7024X20 7024X25 Com'l Only Com Only Coml & Com'l & Military Military Symbol Parameter Test Condition Version Typ. | Max | Typ. | Max ] Typ. | Max | Typ. [ Max | unit lec Dynamic Operating CE = Vu, COM'L S 170 310 170 310 160 200 155 265 mA Current Outputs Open L | 170 | 260 | 170 | 260 | 160 | 240 | 155 | 220 (Both Ports Active) SEM = Vin f= fue MIL & $ 160 370 455 340 IND L 160 320 155 280 sB1 Standby Current C&r = CEL = VH COM'L s 20 60 20 60 20 60 16 60 mA (Both Ports - TTL SEMr = SEML = Vin L 20 50 20 50 2 50 16 50 Level Inputs) f= faa?) MIL & $ 20 90 16 80 IND L 20 70 16 65 isn2 Standby Current CEa" = Vi and CE = Vin) COM'L $ 105 190 4 490 98 180 9 170 mA (One Port - TL Active Port Outputs Open, L 105 160 105 160 95 150 90 146 Level inputs) fefMax) SEMR = SEM = Vie MIL & s 95 240 90 215 IND L 95 210 90 180 \spa Full Standby Curent Both Ports CEL and COML Ss 1.0 15 1.0 15 1.0 15 1.0 1 mA (Both Ports - CER 2 Vee - 0.2V, L 02 5 0.2 5 02 5 0.2 5 CMOS Level Inputs) Vin 2 Vec - 0.2V or Vins 0.2V, f= off MIL & Ss 1.0 x 1.0 30 SEMr = SEM: > Vcc - 0.2V IND L 0.2 10 0.2 10 IsBa Full Standby Current CEw s0.2V and COM. $ 100 170 400 170 90 155 85 145 mA (One Port - CEw > Veo - 0.28 L 100 140 100 140 90 130 85 120 CMOS Level Inputs) SEMR = SEM > Vcc - 0.2V Vin 2 Vec - 0.2V or Vin < 0.2V MIL & S 90 225 85 200 Active Port Outputs Open, IND L 90 200 85 470 f= faax?? NOTES: 2740 tbi 08a 1. % in part number indicates power rating (S or L) 2. Vcc = 5V, Ta = +25, and are not production tested. Icc oc = 120mA (TYP.) 3. At f= fax, address and l/O's are cycling at the maximum frequency fead cycle of 1/trc, and using "AC Test Conditions of input levels of GND to 3V. 4. f= 0 means no address or control lines change. 5, Port "A" may be either left or right port. Port "B" is the opposite from port "A. 6. Industrial temperature: for specific speeds, packages and powers contact your sales office.IDT7024S/. High-Speed 4 x 16 Dual-Port Stalic HAL: ore TR PMTs (CE TntcT DC Electrical Characteristics Over the Operating Temperature and Supply Voltage Rang@) (cont.) (Vcc = 5.0V + 10%) i bernperature Ranges 7024X35 7024X55 7024X70 Com'l & Com'l, Ind Military Only Military & Military Symbol Parameter Test Condition Version Typ.) | Max | Typ.2 | Max | Typ. | Max. | Unit lec Dynamic Operating CE = Vr, COM'L $ 150 250 150 250 | mA Current uts Open L 150 210 150 210 ~ (Both Ports Active) SEM = Vin f= hwo) MIL & S 150 300 150 300 140 300 IND L 150 250 150 250 140 250 Isat Standby Current CEr = CEL = Vin COM'L Ss 13 60 13 60 - _ mA (Both Ports - TH SEMe = SEM. = Vin L 13 x 13 50 - - Level Inputs) = far?) MIL & s 13 80 13 80 10 80 IND L 13 65 13 65 10 65 isB2 Standby Current CE-ar = Vii and CE*e* = Viv? COM'L S 85 155 95 155 mA (One Port - TIL Active Port Outputs Open, L 85 1 95 130 - Level Inputs) fefuax) SEM = SEM. = Vin MIL & S 85 190 95 190 80 190 IND L 85 160 95 160 80 160 IsB3 Full Standby Current Both Ports CEL and COM'L s 1.0 15 1.0 15 mA (Both Ports - CEr > Voc - 0.2V, L 0.2 5 0.2 5 - CMOS Level Inputs) Vin > Veco - 0.2V or Vin < 0.2V, f= 04 MIL & Ss 1.0 30 1.0 30 1.0 30 SEM = SEM 2 Voc - 0.2V IND L{ o2 | 10 | 02 | 0 | 02 | 1 isa Full Standby Current CE s 0.2V and cOM'L s 80 135 80 135 -- mA (One Port - CEs" > Voc - 0.2V) L 80 110 80 110 - CMOS Level inputs) SEMr = SEM. > Vec - 0.2V Vin > Voc - 0.2 or Vin < 0.2V MIL & s 80 175 80 175 75 175 Active Port Outputs Open, IND L 80 150 80 150 75 150 f= Mad 2740 thi 09b NOTES * 1. X' in part number indicates power rating (S or L) 2. Vcc = SV, Ta = +25 T, and are not production tested. 3. At f = fmax, address and I/O's are cycling at the maximum frequency read cycle of Ttrc, and using AC Test Conditionsof input levels of GND to 3V. 4. f = 0 means no address or control lines change. 5. Port "A" may be either left or right port. Port "B" is the opposite from port "A". 6. Industrial temperature: for specific speeds, packages and powers contact your sales office. Data retention Characteristics Over All Temperature Ranges (L Version Only) (Vic = 0.2V, Vic = Vcc - 0.2) Symbol Parameter Test Condition Min. Typ. Max. | Unit VbR Vec for Data Retention Voc = 2V 2.0 _ _ V IccoR Data Retention Current CE > Vic MIL. & IND. a 100 4000 yA VIN > Vie or < Vic COM'L. _ 100 1500 tcor) Chip Deselect to Data Retention Time SEM 2 Vic a - = Vv iro) Operation Recovery Time inc _ _ Vv 2740 thl 10 NOTES: 1. Ta = +25T, Vcc = 2V, and are by device characterization but are not production tested. 2. Irc = Read Cycle Time 3. This parameter is guaranteed but not tested. 4, At Vcc < 2.0V, input leakages are not defined.eh mathe hrs High-Speed 4K x 16 Qual-Poil Static HAM AU esie me raveles:1 Sari mele [serie hint -2 near: lm aden) (ciel is tam ical? [23-3 p a y ) Data Retention Waveform DATA RETENTION MODE "| Voc 4.5V VDR > 2V # 4.5V ~ tcoR - 2 > Vor CE ITLLLLL LF \ / vi AAA 2740 drw 05. AC Test Conditions Input Pulse Levels GND to 3.0V Input Rise/Fall Times 5ns input Timing Reference Levels 41.5V Output Reference Levels 1.5V Output Load Figures 1 and 2 2740 bi 11 5V 5V 12502 12502 DATAOuT BUSY DATAOUT INT 7759 30pF 775Q 5pF* = = 2740 drw 06 Figure 1. AC Output Test Load Figure 2. Output Test Load (for t1z, tz, twz, tow) Including scope and Jigaera sous a ar as Soars] High-Speec AC Electrical Characteristics Over the teria eee eres T Operating Temperature and Supply Voltage Rang@) minercial iemperatue Ranges 7024X15 7024X17 7024X20 7024X25 Com'l Only Com'! Only Com'l & Com'l & Military Military Symbol Parameter Min. | Max. Min. | Max. Min. | Max. Min. Max. Unit READ CYCLE fRC Read Cycle Time 15 _ 17 20 oe 25 ns AA Address Access Time oo 15 17 ~ 20 2 ns tACE Chip Enable Access Time ~ 15 - 7 ~ 20 25 ns taBE Byte Enable Access Time - 15 - 17 20 25 ns {AGE Output Enable Access Time _ 10 ~ 10 -- 42 - 13 ns {oH Output Hold from Address Change 3 ~ 3 - 3 3 ns tz Output LowZ Time! 3 _ 3 ~- 3 - 3 - ns ez Output High-Z Time!" ~ 10 = 10 ~~ 12 15 ng Pu Chip Enable to Power Up Time? Q 0 - 0 0 ns PD Chip Disable to Power Down Time"? _ 15 | 7 - 20 | 25 ns tsop Semaphore Flag Update Pulse (OE or SEM) 10 10 - 10 ~ 10 ns isaa Semaphore Address Access) - 45 - 7 - 20 -- 25 ng 2740 toi 12a 7024X35 7024X55 7024X70 Com'! & Com't, tnd Military Only Military & Military Symbol Parameter Min. | Max. Min. Max. Min. Max. Unit READ CYCLE iRC Read Cycle Time 35 oo 55 o 70 ns taa Address Access Time 35 - 55 - 70 ns tAce Chip Enable Access Time 35 - 55 70 ns tage Byte Enable Access Time - 35 55 _ 70 ns {ade Output Enable Access Time 20 ~ 30 3 ns tou Output Hold from Address Change 3 _ 3 3 ns a2 Output Low-Z Time!" 3 ~ 3 ~ 3 _ ns Hz Output High-Z Time!" ~ 15 ~ 25 ~~ 30 ns Pu Chip Enable to Power Up Time!?) 0 ~~ 0 : 0 ns to Chip Disable to Power Down Time!*) 35 - 50 50 ng tsor Semaphore Flag Update Pulse (OE or SEM) 15 15 - 15 ~ ns tsaa Semaphore Address Access"! ~ 35 55 _ 70 ns NOTES: ee PR wn om Transition is measured +500mV from Low or High-impedance voltage with the Output Test Load (Figure 2). This parameter is guaranteed by device characterization, but is not production tested. To access RAM, CE = Vu, UB or LB = Vi, and SEM =Vui. To access semaphore, CE = Vin or UB & LB = Vin, and SEM =ViL X' in part number indicates power rating (S or L). industrial temperature: for other speeds, packages and powers contact your sales office.eh ritet hrs) High-Speed 4K x 16 Dual-Port Static RAM Waveform of Read Cycle) diary. indusuial and Commieicial Temperature Ranges + tRe > ADDR x ai Bl NN NN SN RW he- trz") ] toH DATAout 4 VALID DATA | tHz BUSYouT WAAAY) M tspp (3.4) 2740 drw 07 NOTES: 1. Timing depends on which signal is asserted last, CE, OF, CB, or UB. 2. Timing depends on which signal is de-asserted first, CE, OE, LB, or UB. 3. top delay is required only in cases where opposite port is completing a write operation to the same address location. For simultaneous read operations BUSY has no relation to valid output data. 4. Start of valid data depends on which timing becomes effective last tage, tag, tAce, [aa or tBDD. 5. SEM = Vin. Timing of Power-Up Power-Down cE tpu tep ISB 2740 drw 08en i dere or inte liniste ed dK x 16 Oual-Port Si cnet SL Oreh SORT: ie i SEIVIE Meat ale [ot] AC Electrical Characteristics Over the Operating Temperature and Supply Voltag@) 7024X15 7024X17 7024X20 7024X25 Com'l Only Com't Only Com'l & Com't & Military Military Symbol Parameter Min. Max. Min | Max. Min. | Max. Min. | Max. Unit WRITE CYCLE twe Write Cycle Time 15 - 7 2 | 25 ns tew Chip Enable to End-of Write 12 _ 12 - 15 - 20 | ns taw Address Valid to End-of-Write 12 12 - 15 - 20 ~ ns tas Address Setup Time 0 o { 0 - 0 ns twe Write Pulse Width 12 12 15 20 _ ns twR Write Recovery Time 1) 0 -- 0 0 ~ ns Dw Data Valid to End-of-Write 10 ~ 10 _ 15 _ 15 ns Hz Output High-2Z Time" ~ 10 - 10 ~ 12 15 ns. DH Data Hold Time? 0 _ 0 _ 0 ~ 0 - ng wz Write Enable to Output in High-2') 10 = 10 12 15 ns tow Output Active from End-of Write4) 0 0 - 0 0 ns tswrD SEM Flag Write to Read Time 5 5 -- 5 5 ns tsps SEM Flag Contention Window 5 ~ 5 - 5 5 - ns 2740 tht *3a 7024X35 7024X55 7024X70 Com't & Com't, Ind Military Only Military & Military Symbol Parameter Min. Max. Min. Max. Min Max Unit WRITE CYCLE twec White Cycle Time 3 ~ 55 70 ~ ns tew Chip Enable to End-of-Wrte 30 45 50 ns taw Address Valid to End-of-Write 30 - 45 - 50 ns tas Address Setup Time o | 0 - 0 ns we Write Pulse Width 25 _ 40 ~~ 50 ns wR Write Recovery Time 0 _ 0 _ 0 _ ns tow Data Valid to End-of-Write 1 - 30 - 40 ~ ns hz Output High-Z Time!) - 15 25 - 30 ns oH Data Hold Time 0 0 -- 0 ns twz Write Enable to Output in High-2' 15 a 25 30 ns tow Output Active from End-of- Write"? 0 0 - 0 - ns tswRD SEM Flag Write to Read Time 5 J 5 ~ 5 ns tsps SEM Flag Contention Window 5 - 5 ~ 5 ~ ng 2740 th: 130 NOTES: 1, Transition is measured +500mV from Low or High-impedance voltage with the Output Test Load (Figure 2). 2. This parameter is guaranteed by device characterization, but is not production tested. _ 3. To access RAM, ce = Vn, UB or [B = Vu, SEM = Vin. To access semaphore, CE = Vin or UB & CB = Vin, and SEM = Vi. Either condition must be valid for the entire tew time. 4. The specification for to must be met by the device supplying write data to the RAM under all operating conditions. Although ton and tow values will vary over voltage and temperature, the actual toy will always be smaller than the actual tow. 5. 'X in part number indicates power rating (S or L). 6. Industrial temperature: for other speeds, packages and powers contact your sales office.eRe bot High-Speed 4K x 16 Dual-Parl Stale HAL diildiv. jdustial and Commercial lemperaiure Ranges Timing Waveform of Write Cycle No. 1, RW Controlled Timing*:>*) twc ADDRESS x x [- taw - CE or SEM \ # UB or LB \ zt Htas (6) <t twp le twr' _ | N | tw2"?-> << tow > DATAoutT + 4 (4) thz 7) + tow __ re ~ tb DATAIN ) 2740 drw O98 Timing Waveform of Write Cycle No. 2(CE, LB Controlled Timing") two ADDRESS V tAW ~ CE or SEM - Ke tagi tew twa ke UB or TB i x RW \ \ \ / [*_ tow Pe __ to DATAIN ) 2740 drw 10 NOTES: RW or CE or UB & LB = Vii during all address transitions. A write occurs during the overlap (tew or twe) of a U UB or UB = Va and a CE = Vn and a RIW = Vi for memory array writing cycle. twe is measured from the earlier of CE or RAW (or SEM or RW) going HIGH = Vi to the end-of-write cycle. During this period, the 1/O pins are in the output state and input signals must not be applied. If the CE or SEM LOW = Vit transition occurs simultaneously with or after the RAV = Vit transition, the outputs remain in the High-impedance state. Timing depends on which enable signal is asserted last, CE, RIW, UB, or LB. This parameter is quaranted by device characterization, but is not production tested. Transition is measured +500mV steady state with the Output Test Load (Figure 2). 8. if OE = Vi dusing R/W controlled write cycle, the write pulse width musi be the larger of twp for (twz + tow) to allow the VO drivers to turn off and data to be placed on the bus for the required tow. if OE = Vin during an RW controled write cycle, this requirement does not apply and the write pulse can be as short as the specified twe . 9. To access RAM, CE = Vi, UB or LB = Vit, and SEM = Vin. To access Semaphore, CE = Vin or UB & CB = Vin, and SEM = Vit. tew must be met for either condition.ie estes ST High-Speed dK x 16 Oual-Por Sian s Sete e Industial ana Commercial lemperiture Ranges Timing Waveform of Semaphore Read after Write Timing, Either Sid@ toH Ao-A2 VALID ADDRESS VALID ADDRESS taw peg EM tow Oo DATAIN OA ONS RW OE Write Cycle }g_____ Read Cycle 2740 drw 11 NOTES: 1. CE = Vis or UB & LB = Viv for the duration of the above timing (both write and read cycle). 2. DATAout VALID represents all O's (l/Oo-//015) equal to the semaphore value. Timing Waveform of Semaphore Write Contentiofi** ( Ao"A"-A2"A" MATCH x. SIDE "A"< Ra [| SEMa: - tSPS Ao'e-Az"e" MATCH x 2) au ok oars SIDE "B" <~ Re / GEAA oy /; XM SEM's CY 2740 drw 12 NOTES: 1. Dor = Do. = Vit, CER = CE: = Vin, or both UB & CB = Vix, semaphore flag is released from both sides (reads as ones from both sides) at cycle start. 2. All timing is the same for left and right ports. Port A may be either left or right port. Port "B" is the opposite from port A, 3. This parameter is measured from R/Wa or SEMa going HIGH to R/We or SEMs going HIGH. 4. If tsPs is not satisfied, there is no guarantee which side will obtain the semaphore flag.Teh ecire Soy High-Speed 4K x 16 Dual-PartS AC Electrical Characteristics Over the Operating Temperature and Supply Voltage Rang@) tere ameLetsic iis Lt Lee imercial Tempe: ature Ranges 7024X15 7024X17 7024X20 7024X25 Com'l Only Com'l Only Com'l & Com! & Military Military Symbol Parameter Min. | Max. Min. | Max. Min. | Max. Min. Max. Unit BUSY TIMING (M/S = Vin) {BAA BUSY Access Time from Address Match _ 15 _ 17 _ 20 - 20 ns {BDA BUSY Disable Time from Address Not Match 15 V7 20 ~- 20 ns {BAC BUSY Access Time from Chip Enable Low 15 _ 17 _ 20 - 20 ns BOC BUSY Disable Time from Chip Enable High _ 15 -- 7 Ww 7 ns taps Arbitration Priority Setup Time 5 ~ 5 _- 5 5 ns tBoo BUSY Disable to Valid Data 18 _ 18 ~ 30 30 ns twH Write Hold After BUSY) 12 13 | ~~ 15 ~~ 7 _ ns BUSY INPUT TIMING (M/S = Vin) tyB BUSY Input to Write) 0 0 -- 0 - 0 ~ ns twH Write Hold Afler BUSY 12 oop 15 _ 7 = ns PORT-TO-PORT DELAY TIMING twoo Write Pulse to Data Delay") ~ 30 - 45 50 ns tpp0 Write Data Valid to Read Data Delay" - 25 - 25 - 35 35 ns 2740 tb! t4a 7024X35 7024X55 7024X70 Com'l & Com'l, Ind Military Only Military & Military Symbol Parameter Min. Max. Min. Max. Min. Max. Unit BUSY TIMING (M/S = Vix) {BAA BUSY Access Time from Address Match 20 ~ 45 45 ns {BDA BUSY Disable Time fom Address NotMatch 20 ~ 40 40 ns tBac BUSY Access Time from Chip Enable Low 2 40 - 40 ns tBoc BUSY Disable Time from Chip Enable High - 20 - 35 3 ns TAPS Arbitration Priority Set-up Time 5 - 5 5 - ns tap0 BUSY Disable to Valid Data ~ 35 40 45 ns twH Write Hold After BUSY) 25 _ 25 25 - ns BUSY INPUT TIMING (M/S = Vin) twa BUSY Input to Write) 0 0 ~ 0 ~ ns twH Write Hold After BUSY 25 25 ~- 25 ns PORT-TO-PORT DELAY TIMING twoo Write Pulse to Data Delay" - 60 - 80 95 ns 'DoD Write Data Valid to Read Data Delay ~ 45 - 65 ~ 80 ns 2740 tbl 14b NOTES: _ 1. Port-to-port detay through RAM cells from writing port to reading port, refer to Timing Waveform of Write Port-to-Port Read and BUSY (M/S = Vi)". 2. To ensure that the earlier of the two ports wins. 3. tepo is a calculated parameter and is the greater of Ons, twop ~ twe (actual) or poo - tow factual). 4. To ensure that the write cycle is inhibited on port 'B during contention with port A. 5. To ensure that a write cycle is completed on port B' after contention with port A. 6. X in part number indicates power rating (S or L). 7. Industrial temperature: for other speeds, packages and powers contact your sales office.eh Odie 5 a8 High-Speed 4K x 16 Quadl-Port Giane RAM industrial a cial lemperaiure Ranges Timing Waveform of Write with Port-to-Port Read an@UsY 4.5)(M/S = Vin) + two al ADDR'a" DK MATCH *K >| tDH DATAIN "a" *K VALID *K taps! ADDR's" MATCH \ tBAA He tBDA tBDD BUSY's" ow two DATAouT 8" SK vaso + toon). ---+ NOTES: _ 2740 drw 13 1. To ensure that the earlier of the two ports wins. tps is ignored for M/S = Vit (SLAVE). 2. CEL = CEr = Vi. 3. OE = Vi for the reading port. 4. if WS = Viu (slave) then BUSY is an input BUSY*a = Vi. and BUSY*s" = don't care, for this example. 5. All timing is the same for both left and right ports. Port "A" may be either the left or right port. Port "B" is the port opposite from port "A. Timing Waveform of Write withBUSY ~ twep-> YO iWin Sk 7 we? BUSY*s" VY Ad twa? Rive" YA 2) | 2740 drw 14 NOTES: 1. twH must be met for both BUSY input (slave) and output (master). 2. BUSY is asserted on port "B Blocking R/W-s", until BUSY*s" goes HIGH. 3. twe is only for the Slave Version.Toker tie High-Speed 4K 16 Dual- eit: Lom eee ae PUIELEsEM Pe STeLeeS CELT LEte me OrSLhstttL-Teonr [me RARE OlSTEe Lee G om SEI nT For) Waveform of BUSY Arbitration Controlled byCE Timing (M/S = Vin) ADDR" and B* a ADDRESSES MATCH x CEn We taps) CEB Ny + 1BAC *+ tepc BUSY 2740 dew 15 Waveform of BUSY Arbitration Cycle Controlled by Address Match Timing (M/S = Vin) ADDR ADDRESS N SK taps?) ADDR's* MATCHING ADDRESS "N" l_ tBAA I+ tBDA BUSY 2740 drw 16 NOTES: 1. All timing is the same for left and right ports. Port A may be either the left or right port. Port B" is the port opposite from A. 2. If taps is not satisfied, the BUSY signal will be asserted on one side or another but there is no guarantee on which side BUSY will be asserted. AC Electrical Characteristics Over the Operating Temperature and Supply Voltage Rang) 7024X15 7024X17 7024X20 7024X25 Com'l Only Com! Only Com'l & Com! & Military Military Symbol Parameter Min. | Max. Min. | Max Min. | Max. Min. Max. Unit INTERRUPT TIMING tas Address Setup Time Oo | 0 ~s 0 ~ 0 _ ns wR Write Recovery Time 0 ~~ 0 0 _ 0 =o ns {Ns Interrupt Set Time - 1 _ 15 _ 20 20 ns tinR Interrupt Reset Time _ 15 ~ 15 ve 20 _ 20 ns 2740 tbl 15a 7024X35 7024X55 7024X70 Com'l & Com'l, Ind Military Only Military & Military Symbol Parameter Min. Max. Min. | Max. Min. Max. Unit INTERRUPT TIMING tas Address Setup Time G 0 o oO | ns twR Write Recovery Time 0 0 ~ 0 ns SNS Interrupt Set Time _ 25 _ 40 50 ns {NR Interrupt Reset Time - 25 40 ~ 50 ns 2740 ti 15b NOTES: 1. 'X' in part number indicates power rating (S or L). 2. Industrial temperature: for other speeds, packages and powers contact your sales office.eh Water hue ale tebe dolcn te Md a ME) SAReRT MES UR a1? RANTS METALS ot Waveform of Interrupt Timing ADDR'a" a INTERRUPT SET ADDRESS XK tas twr)) >} CEs RW a: A tins INT*B* 2740 dew 17 it i >| RIC > ADDR: INTERRUPT CLEAR ADDRESS ) eee tas ) CEs OE's- tnr) INT'2- 2740 drw 18 NOTES: 1, Alf timing is the same for left and right ports. Port "A" may be either the left or right port. Port B is the port opposite from A, 2. See interrupt Truth Table il. _ 3. Timing depends on which enable signal (CE or R/W) is asserted last. 4. Timing depends on which enable signai (CE or RAW) is de-asserted first. Truth Table Ill Interrupt Flag'* Left Port Right Port RW CEL OEL ANL-ADL INTL RiWr CER OER Asr-Aor INTR Function L L x FFF x x x x x L | Set Right INTr Flag X X X X x X L L FFF H | Reset Right INTr Flag x x X x L L L X FFE xX Set Left INTL Flag X L L FFE H?) Xx x X xX X Reset Left INTL Flag 2740 tol 16 NOTES: 1. Assumes BUSY: = BUSYe = Vin. 2. if BUSY: = Vu, then no change. 3. if BUSYe = Vu, then no change. 4. INTr and INTL must be initialized at power-up.IDT70245/ Cn PERUCE LE NEctee Lem vets hit 10 90- UME Sap ET oLE Leet MSP: Tine oe) High-Speed 4K x 36 Qual-Port Stalic HAL Truth Table lV Address BUSY Arbritration Inputs Outputs _ | Ao.-AniL CEL | CER Aor-AniR Busy." | BUSYR Function X X NO MATCH H H Normal H x MATCH H H Nomai X H MATCH H H Normal L L MATCH (2) (2) Write Inhibit) 2740 thl 17 NOTES: 1. Pins BUSY: and BUSYr are both outputs when the part is configured as a master. Both are inputs when configured as a slave. BUSYx outputs on the IDT7024 are push pull, not open drain outputs. On slaves, the BUSY asserted input internally inhibits write. 2. L" if the inputs to the opposite port were stable prior to the address and enable inputs of this port. H" if the inputs to the opposite port became stable after the address and enable inputs of this port. if taps is not met, either BUSYL or BUSYe = LOW will resut. BUSYL and BUSYe outputs cannot be LOW simultaneously. 3. Writes to the left port are internaily ignored when BUSY: outputs are driving LOW regardless of actual logic level on the pin. Writes to the right port are internally ignored when BUSYr outputs are driving LOW regardless of actual logic level on the pin. Truth Table V Example of Semaphore Procurement Sequenc**) Functions Do - Dis Left Do - Dis Right Status No Action 1 1 Semaphore free Left Port Writes "0" to Semaphore 0 1 Le port has semaphore token Right Port Writes "0" to Semaphore GO 1 No change. Right side has no write access to semaphore Left Port Writes "1" to Semaphore { 0 Right port obtains semaphore token Left Port Writes "0" to Semaphore 1 0 No change. Left port has no write access to semaphore Right Port Writes "1" to Semaphore 0 1 Left port obfains semaphore token Left Port Writes "1" to Semaphore 1 1 Semaphore free Right Port Writes "0" to Semaphore 4 0 Right port has semaphore token Right Port Writes "1" to Semaphore 1 1 Semaphore free Left Port Writes "0" to Semaphore 0 1 Left port has semaphore token Left Port Writes "1" to Semaphore 4 1 Semaphore free NOTES: 2740 tbl 18 1. This table denotes a sequence of events for only one of the eight semaphores on the [DT7024, 2. There are eight semaphore flags written to via /Oo and read from all the i/O's. These eight semaphores are addressed by A0-Az. 3. CE = Vin, SEM = Vit, to access the Semaphores. Refer to the Semaphore Read/Write Control Truth Table. Functional Description The IDT7024 provides two ports with separate control, address and 1/0 pins that permitindependent access for reads or writes to any location inmemory. TheiDT7024 has an automatic power down featurecontrolled by CE. The CE controls on-chip power down circuitry that permits the respective portto go into a standby mode when not selected (CE = Vin). Whenaportis enabled, access to the entire memory array is permitted. interrupts Ifthe user chooses the interruptfunction, a memory location (mail box of message center) is assigned to each port. The left port interrupt flag (INTL) is asserted when the right port writes to memory location FFE (HEX), where awriteis defined as the CE = R/W = Vi per the Truth Table lil. The left port clears the interrupt by access address location FFE access when CER = OER = Vi. RWW is a don't care. Likewise, the right port interrupt flag (INTR)is asserted when the left port writes to memory location FFF (HEX) and toclearthe interrupt flag (INTR), theright port mustaccess the memory location FFF. The message (16 bits) atFFE or FFF isuser- defined, since itisan addressable SRAMIocation. Ifthe interruptfunctionIDT7024S/1 High-Speed 4K x [6 Dual-Port Static RA Moitaiy iAdustria! and isnotused, address locations FFE and FFF are notused as mailboxes, but as partofthe random access memory. Refer to Truth Table lil for the interrupt operation. Busy Logic Busy Logic provides a hardware indication that both ports of the RAM haveaccessed the same location atthe same time. Italso allows one of the twoaccessesto proceed and signals the other side thatthe RAMis "busy". The BUSY pin can then be used tostallthe access until the operation on the other side is completed. Ifa write operation has been attempted from the side thatreceives a BUSY indication, the write signalis gated internally to prevent the write from proceeding. The use of BUSY logicis notrequired or desirable for all applications. Insome casesitmay be useful tologically OR the BUSY outputs together and use any BUSY indication as an interrupt source to flag the event of an illegal or illogical operation. Ifthe write inhibit function of BUSY logicis notdesirable, the BUSY logic can be disabled by placing the partin slave mode with the M/S pin. Once in slave mode the BUSY pin operates solely as a write inhibit input pin. Normal operation can be programmed by tying the BUSY pins HIGH. If desired, unintended write operations can be prevented to a port by tying the BUSY pin for that port LOW. TheBUSY outputs onthe IDT 7024 SRAMin master mode, are push- pull type outputs and do not require pull up resistors to operate. Ifthese RAMs are being expanded in depth, then the BUSY indication for the resulting array requires the use of an external AND gate. Width Expansion withBUSY Logic Master/Slave Arrays When expanding an!DT7024 RAM array in width while using BUSY logic, one master partis used to decide which side of the RAM array will receive a BUSY indication, and to output that indication. Any number of slaves to be addressed in the same address range as the master, use the BUSY signal as a write inhibit signal. Thus onthe {DT7024 RAMthe BUSY pinis an output ifthe partis used as a master (M/S pin = Vik), and the BUSY pinis an input f the partused asa slave (WS pin = Vit) as shown in Figure 3. if two or more master parts were used when expanding in width, a split decision could result with one master indicating BUSY on one side of the array and another master indicating BUSY on one other side of the array. This would inhibit the write operations from one port for part of a word and inhibit the write operations from the other port for the other partofthe word. The BUSY arbitration, on a master, is based onthe chip enable and address signals only. !tignores whether an access is aread or write. in a master/slave array, both address and chip enable must be valid long enough for aBUSY flag tobe output from the master before the actual write pulse can be initiated with either the R/W signal or the byte enables. Failure toobservethis timing can resuttin a glitched internal write inhibit signal and corrupted data in the slave. Semaphores TheiDT7024 is an extremely fast Dual-Port 4K x 16 CMOS Static RAM with an additional 8 address locations dedicated to binary semaphore flags. These flags allow either processor on the left or right side of the Dual-Port RAMtoclaima privilege over the other processor for functions defined by the system designer's software. As an example, the semaphore can be Commercial Temperature Ranges c TT MASTER CE SLAVE cE 5 Qual Port Dual Port Oo RAM _ RAM Wy BUSY (L) BUSY (R) COR MASTER cE SLAVE CE Dual Port Dual Port RAM RAM_ | BUSY (L} | BUSY (L) BUSY(R)} | BUSY (L) BUSY (A) ae <CE 2740 drw 19 Figure 3. Busy and chip enable routing for both width and depth expansion with 1DT7024 RAMs. used by one processor to inhibit the other from accessing a portion of the Duail-Port RAM or any other shared resource. The Dual-Port RAM features a fast access time, and both ports are completely independentof each other. This means thatthe activity onthe left port in no way slows the access time of the right port. Both ports are identical in function to standard CMOS Static RAM andcanberead from, or written to, atthe same time with the only possible conflict arising fromthe simultaneous writing of, or a simultaneous READ/WRITE of, a non- semaphore location. Semaphores are protected against such ambiguous situations and may be used by the system program to avoid any conflicts inthenon-semaphore portion of the Dual-Port RAM. These devices have an automatic power-down feature controlled by CI CE, the Dual-Port RAM enable, and SEM, the semaphore enable. The CE and SEM pins control on-chip power down circuitry that permits the respective port to go into standby mode when not selected. This is the condition whichis shown in Truth Table | where CE and SEM = ViH. Systems which can bestuse the IDT 7024 contain multiple processors of controllers and are typically very high-speed systems which are software controlled or software intensive. These systems can benefit from a performance increase offered by the DT 7024's hardware semaphores, which provide a lockout mechanism without requiring complex program- ming. Software handshaking between processors offers the maximum in system flexibility by permitting shared resources to be allocated in varying configurations. The IDT 7024 does notuse its semaphore flags tocontrol any resources through hardware, thus allowing the system designer total flexibility in system architecture. An advantage of using semaphores rather than the more common methods of hardware arbitration is that wait states are never incurred in either processor. This can prove to be a major advantage in very high-speed systems. How the Semaphore Flags Work The semaphore logic is a set of eight latches which are independent ofthe Dual-Port RAM. These latches canbe usedto passa flag, ortoken, from one portto the other toindicate thata shared resourceis inuse. The semaphores provide a hardware assist for a use assignment method called"Token Passing Allocation." In this method, the state of a semaphore latch isused as atoken indicating that shared resource isin use. Ifthe left processor wants to use this resource, itrequests the token by setting the latch. This processor then verifies its success in setting thelatch byreadingIDT7024S/A High-Speed 4K 16 Dual-Parl Stale HAM it. If it was successful, it proceeds to assume control over the shared resource. fitwas not successful in setting the latch, itdetermines thatthe right side processor has set thelatchfirst, has the token andis using the sharedresource. The left processor can then either repeatedly request thatsemaphore's status orremoveits request for thatsemaphoreto perform another task and occasionally attempt again to gain contral of the token via the setandtest sequence. Once the right side has relinquished the token, the left side should succeed in gaining control. The semaphoreflags are activeLOW. A token is requested by writing azerointo a semaphore latch andis released when the same side writes aoneto thatlatch, The eight semaphore flags reside within the IDT7024 in a separate memoryspace fromthe Dual-PortRAM. This address spaceis accessed by placinga LOWinputon the SEM pin (which acts asa chip select forthe semaphore flags) and using the other control pins (Address, OE, and R/W) as they would be used in accessing a standard Static RAM. Each of the flags has a unique address which can be accessed by either side through address pins Ao- Az. When accessing the semaphores, none of the other address pins has any effect. When writing toa semaphore, only data pin Dois used. If alow level iswritteninto an unused semaphore location, that flag will be set toa zero on that side and a one on the other side (see Truth Table Il). That semaphore cannow only be modified by the side showing the zero. When aaneis written into the same location fromthe same side, the flag willbe Settoa onefor both sides (unless a semaphorerequestirom the other side is pending) and then can be written toby both sides. The factthatthe side whichis ableto write a zerointoa semaphore subsequently locks outwrites fromthe other sideis what makes semaphore flags usefulininterprocessor communications. (Athorough discussion onthe use of this feature follows shortly.) A zero written into the same location from the other side will be stored inthe semaphore request latch for that side untilthe semaphores freed by the firstside. Whena semaphore flagisread, its valueis spread into all data bits so thataflag thatis a one reads as a one inall data bits and a flag containing azeroreads as ail zeros. Theread value is latched into one side's output register when that side's semaphore select (SEM) and output enable (OE) signals go active. This serves to disallow the semaphore from changing statein the middle of aread cycie due to a write cycle from the other side. Because of this latch, arepeated read of a semaphore ina testloop must cause either signal (SEM or OE) to go inactive or the output will never change. Asequence WRITE/READ must be used by the semaphore in order to guarantee that no system level contention will occur. A processor requests access to shared resources by attempting to write a zerointoa semaphore location. Ifthe semaphoreis already in use, the semaphore requestlatch will contain a Zero, yetthe semaphore flag will appear as one, afact which the processor will verify by the subsequent read (see Truth Tablelli), Asanexample, assumea processor writes a zeroto theleft port ata free semaphore location. On a subsequentread, the processor will verify that ithas written successfully to that location and willassume control over the resource in question. Meanwhile, ifa processor on the rightside attempts to write a zero to the same semaphore flag it will fail, as will be verified by the fact thata one will beread from that semaphore on the right side during subsequent read. Had a sequence of READ/AWRITE been used instead, system contention problems couldhave occurred during the gap between the read and write cycles. nidey. idistial aad Commercial lemperature Rages ltisimportantto note that a failed semaphore requestmustbe followed by either repeated reads or by writing a one into the same location. The reason for thisis easily understood by looking atthe simple logic diagram of the semaphore flagin Figure 4. Two semaphorerequest latches feed into a semaphore flag. Whichever latch is first to present a zero to the semaphore flag willforce its side ofthe semaphore flagL OW and the other side HIGH. This condition will continue until a one is written to the same semaphore requestlatch. Should the other side's semaphorerequestlatch have been written toa zero inthe meantime, the semaphore flag will flip over tothe other side as soon as a oneis written intothefirst sides request latch. The second sides flag willnowstay LOW untilits semaphore request latchis writtento.a one. From this itis easy to understand that, ifa semaphore is requested and the processor which requested it no longer needs the resource, the entire system can hang up until a one is written into that semaphorerequestlatch. The critical case of semaphore timing is when both sides request a single token by attempting to write a Zero into it at the same time. The semaphore logic is specially designed to resolve this problem. If simultaneous requests are made, the logic guarantees that only one side receives the token. If one side is earlier than the other in making the request, the first side to make the request will receive the token. If both requests arrive atthe same time, the assignment willbe arbitrarily made to one port or the other. One caution that should be noted when using semaphores is that semaphores alone donot guarantee that access toaresourceis secure. Aswith any powerful programming technique, ifsemaphores are misused of misinterpreted, a software error can easily happen. Initialization of the semaphores is not automatic andmust be handied via the initialization program at power-up. Since any semaphore request flag which contains a zero must beresettoa one, all semaphores onboth sides should have a one written intothem at initialization from both sides to assure that they will be free when needed. Using SemaphoresSome Examples Perhaps the simplest application of semaphoresis their application as resource markers for the IDT7024s Dual-Port RAM. Saythe 4Kx 16 RAM was to be divided into two 2K x 16 blocks which were to be dedicated at any one time to Servicing either the left or right port. Semaphore 0 could be used to indicate the side which would control the lower section of memory, and Semaphore 1 could be defined as the indicator for the upper section ofmemory. Totake a resource, in this example the lower 2K of Dual-Port RAM, the processor on the left port could write and then read a Zero in to Semaphore 0. Ifthis task were successfully completed (a Zero was read back rather than a one), the left processor would assume control of the lower 2K. Meanwhile the right processor was attempting to gain control of theresource alter the left processor, itwouldread back aoneinresponse tothe zero it had attempted to write into Semaphore 0. Atthis point, the software could choose to try and gain control ofthe second 2K section by writing, then reading a zerointo Semaphore 1. ifitsucceeded in gaining control, itwould lock out theieft side. Once the left side was finished with its task, it would write a one to Semaphore 0 and may then try to gain access to Semaphore 1. If Semaphore 1 was still occupied by theright side, the left side could undo its semaphore request and perform other tasks untilitwas abletowrite, theneh strc ict e High-Speed 4 16 Dua-Poit Static RAL read a zerointo Semaphore 1. Iftherightprocessor performs a similar task with Semaphore 0, this protocol would allow the two processors to swap 2K blocks of Dual-Port RAM with each other. The blocks do not have to be any particular size and can even be variable, depending upon the complexity of the software using the semaphore flags. Alleight semaphores could be used to divide the Duai- Port RAM or other shared resources into eight parts. Semaphores can even be assigned different meanings on differentsides rather than being given a common meaning as was shown in the example above. Semaphores are a useful form of arbitration in systems like disk interfaces where the CPU mustbe locked out ofa section of memory during atransfer and the /O device cannottolerate any wait states. With the use of semaphores, once the two devices has determined which memory area was off-limits tothe CPU, both the CPU andthe lO devices could access their assigned portions of memory continuously without any wait states. LPORT SEMAPHORE REQUEST FLIP FLOP Do D Q WRITE I SEMAPHORE READ Figure 4. IDT7024 Semaphore Logic SAUL ECE@ SUED LORE) Card) Mecr Ale ME SAR EL IRL 20ST CTE ECERIT SL 220 TESTER TT e 1-2) Semaphores are alsousefulin applications where nomemory"WAIT State is available on one or both sides. Oncea semaphore handshake has been performed, both processors can access their assigned RAM segments atfull speed. Another applications in the area of complex data structures. Inthis case, block arbitration is very important. For this application one processor may be responsible for building and updating a data structure. The other processor thenreads and interprets that data structure. Ifthe interpreting processor reads an incomplete data structure, a major error condition may exist. Therefore, some sort of arbitration must be used between the two different processors. The building processor arbitrates for the block, locks itandthenis able to goin and update the data structure. When the update is completed, the data structure block is released. This allows the interpreting processor tocome back andread the complete data structure, thereby guaranteeing a consistent data structure, APORT SEMAPHORE REQUEST FLIP FLOP Q of Do + WRITE SEMAPHORE READ 2740 drw 20Leh ways cyl e High-Speed 4K x 16 Dual-Port= eater Bhltary, ingusival aad Commercial Temperature Ranges Ordering Information IDT XXXXx A 999 A A Device Power Speed Package Process/ Type Temperature Range Blank Commercial (0C to +70C) ye industrial (-40C to +85C) B Military (-55C to +125C) Compliant to MIL-PRF-38535 QML PF 100-pin TQFP (PN100-1) G 84-pin PGA (G84-3) d 84-pin PLCC (J84-1) F 34-pin Flatpack (F84-2) 15 Commercial Only 17 Commercial Only 20 Commercial & Military 25 Commercial & Military Speed in nanoseconds 35 Commercial & Military 55 Commercial, industrial & Military 70 Military Only J is Standard Power Pk Low Power | 7024 64K (4K x 16) Dual-Port RAM 2740 drw 21 NOTE: 1. Industrial temperature range is available on selecled PLCC packages in standard power. For other speeds, packages and powers contact your sales office. Datasheet Document History 1/13/99: Initiated datasheet documenthistory Converted tonew format Cosmetic and typographical corrections Pages 2 and 3 Added additional notes to pin configurations CORPORATE HEADQUARTERS for SALES: for Tech Support: Tt) IDT 2975 Stender Way 800-345-7015 or 408-727-6116 | 831-754-4613 - Santa Clara, CA 95054 fax: 408-492-8674 DualPortHelp@idt.com www.idi.com The IDT fogo is a registered trademark of integrated Device Technology, inc. 4