87339AGI-11 www.idt.com REV. B AUGUST 2, 2010
1
ICS87339I-11
LOW SKEW,
÷
2/4,
÷
4/5/6,
DIFFERENTIAL-TO-3.3V LVPECL CLOCK GENERATOR
GENERAL DESCRIPTION
The ICS87339I-11 is a low skew, high performance
Differential-to-3.3V LVPECL Clock Generator/Divider. The
ICS87339I-11 has one differential clock input pair. The CLK,
nCLK pair can accept most standard differential input
levels. The clock enable isinternally synchronized to
eliminate runt pulses on theoutputs during asynchronous
assertion/deassertion of the clock enable pin.
Guaranteed output and part-to-part skew characteristics
make the ICS87339I-11 ideal for clock distribution
applications demanding well defined performance and
repeatability.
FEATURES
•Dual ÷2, ÷4 differential 3.3V LVPECL outputs;
Dual ÷4, ÷5, ÷6 differential 3.3V LVPECL outputs
•One differential CLK, nCLK input pair
•CLK, nCLK pair can accept the following differential
input levels: LVDS, LVPECL, LVHSTL, SSTL, HCSL
•Maximum clock input frequency: 1GHz
•Translates any single ended input signal (LVCMOS, LVTTL,
GTL) to LVPECL levels with resistor bias on nCLK input
•Output skew: 35ps (maximum)
•Part-to-part skew: 385ps (maximum)
•Bank skew: Bank A - 20ps (maximum)
Bank B - 20ps (maximum)
•Propagation delay: 2.1ns (maximum)
•LVPECL mode operating voltage supply range:
VCC = 3V to 3.6V, VEE = 0V
•Available in both standard (RoHS5) and lead-free (RoHS 6)
packages
BLOCK DIAGRAM PIN ASSIGNMENT
ICS87339I-11
20-Lead TSSOP
6.50mm x 4.40mm x 0.92 package body
G Package
Top View
20-Lead SOIC, 300MIL
7.5mm x 12.8mm x 2.25mm package body
M Package
Top View
VCC
nCLK_EN
DIV_SELB0
CLK
nCLK
RESERVED
MR
VCC
DIV_SELB1
DIV_SELA
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
VCC
QA0
nQA0
QA1
nQA1
QB0
nQB0
QB1
nQB1
VEE
QA0
nQA0
QA1
nQA1
D
Q
LE
DIV_SELA
nCLK_EN
CLK
nCLK
MR
DIV_SELB0
DIV_SELB1
QB0
nQB0
QB1
nQB1
÷2, ÷4
R
R
÷4, ÷5, ÷6
87339AGI-11 www.idt.com REV. B AUGUST 2, 2010
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ICS87339I-11
LOW SKEW,
÷
2/4,
÷
4/5/6,
DIFFERENTIAL-TO-3.3V LVPECL CLOCK GENERATOR
TABLE 2. PIN CHARACTERISTICS
TABLE 1. PIN DESCRIPTIONS
lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU
C
NI
ecnaticapaCtupnI 4Fp
R
PULLUP
rotsiseRpulluPtupnI 15kΩ
R
NWODLLUP
rotsiseRnwodlluPtupnI 15kΩ
rebmuNemaNepyTnoitpircseD
02,8,1V
CC
rewoP.snipylppusevitisoP
2NE_KLCntupnInwodlluP.3elbaTeeS.slevelecafretniLTTVL/SOMCVL.elbanekcolC
30BLES_VIDtup
nInwodlluP .3elbaTnidebircsedsastuptuoBknaBrofeulavedividstceleS
.slevelecafretniLTTVL/SOMCVL
4KLCtupnInwodl
luP.tupnikcolclaitnereffidgnitrevni-noN
5KLCntupnIpulluP.tupnikcolclaitnereffidgnitrevnI
6DEVRESERevreseR.nipev
reseR
7RMtupnInwodlluP
tesererasredividlanretnieht,HGIHcigolnehW.teseRretsaMhgiHevitcA
ogotxQnstuptuodetrev
niehtdnawologotxQstuptuoeurtehtgnisuac
.delbaneerastuptuoehtdnasredividlanretnieht,WOLcigolnehW.hgih
.s
levelecafretniLTTVL/SOMCVL
91BLES_VIDtupnInwodlluP .3elbaTnidebircsedsastuptuoBknaBrofeulavedividstceleS
.s
levelecafretniLTTVL/SOMCVL
01ALES_VIDtupnInwodlluP .3elbaTnidebircsedsastuptuoAknaBrofeulavedividstceleS
.s
levelecafretniLTTVL/SOMCVL
11V
EE
rewoP.nipylppusevitageN
31,211BQ,1BQntuptuO.slevelecafretniLCEPVL.riaptuptuolaitnereffiD
51,410BQ,0BQntuptuO.s
levelecafretniLCEPVL.riaptuptuolaitnereffiD
71,611AQ,1AQntuptuO.slevelecafretniLCEPVL.riaptuptuolaitneref
fiD
91,810AQ,0AQntuptuO.slevelecafretniLCEPVL.riaptuptuolaitnereffiD
:ETON pulluP dna nwodlluP .seulavlacipytr
of,scitsiretcarahCniP,2elbaTeeS.srotsisertupnilanretniotrefer
87339AGI-11 www.idt.com REV. B AUGUST 2, 2010
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ICS87339I-11
LOW SKEW,
÷
2/4,
÷
4/5/6,
DIFFERENTIAL-TO-3.3V LVPECL CLOCK GENERATOR
TABLE 3. CONTROL INPUT FUNCTION TABLE
stupnIstuptuO
RMNE_KLCnALES_VID0BLES_VID1BLES_VID1AQ,0AQ1AQn,0AQn1BQ,0BQ1BQn,0BQn
1X X X X WOLHGIHWOLHGIH
01 X X X toN
gnihctiwS
toN
gni
hctiwS
toN
gnihctiwS
toN
gnihctiwS
00 0 0 0 2÷2÷4÷4÷
00 0 0 1 2÷2÷5÷5÷
00 0 1 0 2÷2÷6÷6÷
00 0 1 1 2÷2÷5÷5÷
00 1 0 0 4÷4÷4÷4÷
00 1 0 1 4÷4÷5÷5÷
00 1 1 0 4÷4÷6÷6÷
00 1 1 1 4÷4÷5÷5÷
.egdekcolctupnignillafdnagnisir
agniwollofgnihctiwspotsstuptuokcolceht,sehctiwsNE_KLCnretfA:ETON
tRR
FIGURE 1A. MR TIMING DIAGRAM
CLK
MR
Q (÷n)
Enabled
Disabled
CLK
nCLK
nCLK_EN
QAx, QBx
nQAx, nQBx
FIGURE 1B. NCLK_EN TIMING DIAGRAM
87339AGI-11 www.idt.com REV. B AUGUST 2, 2010
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ICS87339I-11
LOW SKEW,
÷
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÷
4/5/6,
DIFFERENTIAL-TO-3.3V LVPECL CLOCK GENERATOR
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VCC = 3.3V±0.3V, TA = -40°C TO 85°C
TABLE 4B. LVCMOS / LVTTL DC CHARACTERISTICS, VCC = 3.3V±0.3V, TA = -40°C TO 85°C
TABLE 4C. DIFFERENTIAL DC CHARACTERISTICS, VCC = 3.3V±0.3V, TA = -40°C TO 85°C
lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU
V
CC
egatloVylppuSevitisoP 0.33.36.3V
I
EE
tnerruCylppuSrewoP 501Am
lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU
V
HI
egatloVhgiHtupnI 2V
CC
3.0+V
V
LI
egatloVwoLtupnI 3.0-8.0V
I
HI
tnerruChgiHtupnI ,RM,NE_KLCn
xBLES_VID,ALES_VID V
NI
V=
CC
V6.3=051Aµ
I
LI
tnerruCwoLtupnI ,RM,NE_KLCn
xBLES_VID,ALES_VID V
NI
V,V0=
CC
V6.3=5-Aµ
lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU
I
HI
tnerruChgiHtupnI KLCnV
NI
V=
CC
V6.3=5Aµ
KLCV
NI
V=
CC
V6.3=051Aµ
I
LI
tnerruCwoLtupnI KLCnV
NI
V,V0=
CC
V6.3=051-Aµ
KLCV
NI
V,V0=
CC
V6.3=5-Aµ
V
PP
egatloVtupnIkaeP-ot-kaeP 51.03.1V
V
RMC
;egatloVtupnIedoMnommoC
2,1ETON V
EE
5.0+V
CC
58.0-V
snoitacilppadedneelgnisroF:1ETON ,VsiKLCn,KLCrofegatlovtupnimumixameht
CC
.V3.0+
siegatlovedomnommoC:2ETONVsadenifed
HI
.
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, V
CC 4.6V
Inputs, VI-0.5V to VCC + 0.5 V
Outputs, IO
Continuous Current 50mA
Surge Current 100mA
Package Thermal Impedance, θ
JA
20 Lead TSSOP 73.2°C/W (0 lfpm)
20 Lead SOIC 46.2°C/W (0 lfpm)
Storage Temperature, T
STG -65°C to 150°C
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions be-
yond those listed in the DC Characteristics or AC Character-
istics is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
87339AGI-11 www.idt.com REV. B AUGUST 2, 2010
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ICS87339I-11
LOW SKEW,
÷
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÷
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DIFFERENTIAL-TO-3.3V LVPECL CLOCK GENERATOR
TABLE 5. AC CHARACTERISTICS, VCC = 3.3V±0.3V, TA = -40°C TO 85°C
TABLE 4D. LVPECL DC CHARACTERISTICS, VCC = 3.3V±0.3V, TA = -40°C TO 85°C
lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU
f
KLC
ycneuqerFtupnIkcolC 1zHG
t
DP
1ETON;yaleDnoitagaporP)ffiD(QotKLC6.11.2sn
t)o(ks5,2ETON;wekStuptuO 5153sp
t)b(ks ;wekSknaB
5,3ETON
AknaB0102sp
BknaB010
2sp
t)pp(ks5,4ETON;wekStraP-ot-traP 583sp
t
S
emiTputeSKLCotNE_KLCn053sp
t
H
emiTdloHNE_KLCnotKLC001sp
t
RR
emiTyrevoceRteseR 004sp
t
WP
htdiWesluPmuminiMKLC055sp
t
R
t/
F
emiTllaF/esiRtuptuO%08ot%02001006sp
cdoelcyCytuDtuptuO 8425%
.4÷stuptuohtiwnekatatadllA
.tniopgnissorctuptuolait
nereffidehtottniopgnissorctupnilaitnereffidehtmorfderusaeM:1ETON
.snoitidnocdaollauqehtiwdnaegatlovylp
pusemasehttastuptuoneewtebwekssadenifeD:2ETON
stniopssorclaitnereffidtuptuoehttaderusaeM
.snoitidnocdao
llauqehtiwdnastuptuofoknabanihtiwwekssadenifeD:3ETON
segatlovylppusemasehttagnitareposecivedtnereffidn
ostuptuoneewtebwekssadenifeD:4ETON
derusaemerastuptuoeht,ecivedhcaenostupnifoepytemasehtgnisU.snoitidn
ocdaollauqehtiwdna
.stniopssorclaitnereffidehtta
.56dradnatSCEDEJhtiwecnadroccanidenifedsiretemarapsihT
:5ETON
lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU
V
HO
1ETON;egatloVhgiHtuptuOV
CC
4.1-V
CC
9.0-V
V
LO
1ETON;egatloVwoLtuptuOV
CC
0.2-V
CC
7.1-V
V
GNIWS
gniwSegatloVtuptuOkaeP-ot-kaeP 6.00.1V
05htiwdetanimretstuptuO:1ETON ΩVot
CC
.V2-
87339AGI-11 www.idt.com REV. B AUGUST 2, 2010
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ICS87339I-11
LOW SKEW,
÷
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÷
4/5/6,
DIFFERENTIAL-TO-3.3V LVPECL CLOCK GENERATOR
PARAMETER MEASUREMENT INFORMATION
PART-TO-PART SKEW
BANK SKEW OUTPUT RISE/FALL TIME
DIFFERENTIAL INPUT LEVEL
OUTPUT SKEW
3.3V OUTPUT LOAD AC TEST CIRCUIT
PROPAGATION DELAY OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
SCOPE
Qx
nQx
LVPECL
2V
-1.3V ± 0.3V
V
CMR
Cross Points
V
PP
VCC
VEE
CLK
nCLK
tsk(o)
nQx
Qx
nQy
Qy
Clock
Outputs 20%
80% 80%
20%
t
R
t
F
V
SWING
Pulse Width
t
PERIOD
t
PW
t
PERIOD
odc =
QAx, QBx
nQAx, nQBx
QAx
nQAx
tsk(pp)
nQx
Qx
nQy
Qy
PART 1
PART 2
tsk(b)
QBx
nQBx
tPD
nCLK
CLK
nQAx,
nQBx
QAx,
QBx
VCC,
VCCO
VEE
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DIFFERENTIAL-TO-3.3V LVPECL CLOCK GENERATOR
APPLICATION INFORMATION
Figure 2 shows how the differential input can be wired to accept
single ended levels. The reference voltage V_REF = VCC/2 is
generated by the bias resistors R1, R2 and C1. This bias circuit
should be located as close as possible to the input pin. The ratio
FIGURE 2. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT
V
CC
- 2V
50Ω50Ω
RTT
Z
o
= 50Ω
Z
o
= 50Ω
FOUT FIN
RTT = Z
o
1
((V
OH
+ V
OL
) / (V
CC
– 2)) – 2
3.3V
125Ω125Ω
84Ω84Ω
Zo = 50Ω
Zo = 50Ω
FOUT FIN
The clock layout topology shown below is a typical termina-
tion for LVPECL outputs. The two different layouts mentioned
are recommended only as guidelines.
FOUT and nFOUT are low impedance follower outputs that gen-
erate ECL/LVPECL compatible outputs. Therefore, terminating
resistors (DC current path to ground) or current sources must
be used for functionality. These outputs are designed to drive
50Ω transmission lines. Matched impedance techniques should
be used to maximize operating frequency and minimize signal
distortion. Figures 3A and 3B show two different layouts which
are recommended only as guidelines. Other suitable clock lay-
outs may exist and it would be recommended that the board
designers simulate to guarantee compatibility across all printed
circuit and clock component process variations.
TERMINATION FOR LVPECL OUTPUTS
FIGURE 3B. LVPECL OUTPUT TERMINATIONFIGURE 3A. LVPECL OUTPUT TERMINATION
WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS
of R1 and R2 might need to be adjusted to position the V_REF in
the center of the input voltage swing. For example, if the input
clock swing is only 2.5V and VCC = 3.3V, V_REF should be 1.25V
and R2/R1 = 0.609.
V_REF
R1
1K
C1
0.1u R2
1K
Single Ended Clock Input
CLK
nCLK
VCC
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ICS87339I-11
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DIFFERENTIAL-TO-3.3V LVPECL CLOCK GENERATOR
FIGURE 4C. CLK/NCLK INPUT DRIVEN BY
3.3V LVPECL DRIVER
FIGURE 4B. CLK/NCLK INPUT DRIVEN BY
3.3V LVPECL DRIVER
FIGURE 4D. CLK/NCLK INPUT DRIVEN BY
3.3V LVDS DRIVER
3.3V
R1
50
R3
50
Zo = 50 Ohm
LVPECL
Zo = 50 Ohm
HiPerClockS
CLK
nCLK
3.3V
Input
R2
50
Zo = 50 Ohm
Input
HiPerClockS
CLK
nCLK
3.3V
R3
125
R2
84
Zo = 50 Ohm
3.3V
R4
125
LVPECL
R1
84
3.3V
DIFFERENTIAL CLOCK INPUT INTERFACE
The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL
and other differential signals. Both VSWING and VOH must meet the
VPP and VCMR input requirements. Figures 4A to 4E show
interface examples for the CLK/nCLK input driven by the most
common driver types. The input interfaces suggested here are
FIGURE 4A. CLK/NCLK INPUT DRIVEN BY
LVHSTL DRIVER
examples only. Please consult with the vendor of the driver
component to confirm the driver termination requirements. For
example in Figure 4A, the input termination applies for LVHSTL
drivers. If you are using an LVHSTL driver from another
vendor, use their termination recommendation.
1.8V
R2
50
Input
LVHSTL Driver
ICS
HiPerClockS
R1
50
LVHSTL
3.3V
Zo = 50 Ohm
Zo = 50 Ohm
HiPerClockS
CLK
nCLK
FIGURE 4E. CLK/NCLK INPUT DRIVEN BY
3.3V LVPECL DRIVER WITH AC COUPLE
Zo = 50 Ohm
R3
125
HiPerClockS
CLK
nCLK
3.3V
R5
100 - 200
3.3V
R2
84
3.3V
R6
100 - 200
Input
R5,R6 locate near the driver pin.
Zo = 50 Ohm
R1
84
R4
125
C2
LVPECL C1
Zo = 50 Ohm
R1
100
3.3V
LVDS_Driv er
Zo = 50 Ohm
Receiv er
CLK
nCLK
3.3V
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ICS87339I-11
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4/5/6,
DIFFERENTIAL-TO-3.3V LVPECL CLOCK GENERATOR
POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS87339I-11.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS87339I-11 is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for VCC = 3.3V + 0.3V = 3.6V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
•Power (core)MAX = VCC_MAX * ICC_MAX = 3.6V * 105mA = 378mW
•Power (outputs)MAX = 30mW/Loaded Output pair
If all outputs are loaded, the total power is 4 * 30mW = 120mW
Total Power_MAX (3.6V, with all outputs switching) = 378mW + 120mW = 498mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the
device. The maximum recommended junction temperature for the devices is 125°C.
The equation for Tj is as follows: Tj = θJA * Pd_total + TA
Tj = Junction Temperature
θJA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
TA = Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA
must be used. Assuming a
moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 66.6°C/W per Table 6A below.
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:
85°C + 0.498W * 66.6°C/W = 118.1°C. This is below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow,
and the type of board (single layer or multi-layer).
0 200 500
Single-Layer PCB, JEDEC Standard Test Boards 114.5°C/W 98.0°C/W 88.0°C/W
Multi-Layer PCB, JEDEC Standard Test Boards 73.2°C/W 66.6°C/W 63.5°C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
θθ
θθ
θ
JA
by Velocity (Linear Feet per Minute)
Table 6A. Thermal Resistance θθ
θθ
θJA for 20-pin TSSOP, Forced Convection
θθ
θθ
θ
JA
by Velocity (Linear Feet per Minute)
0 200 500
Single-Layer PCB, JEDEC Standard Test Boards 83.2°C/W 65.7°C/W 57.5°C/W
Multi-Layer PCB, JEDEC Standard Test Boards 46.2°C/W 39.7°C/W 36.8°C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
Table 6B. Thermal Resistance θθ
θθ
θJA for 20-pin SOIC, Forced Convection
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ICS87339I-11
LOW SKEW,
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DIFFERENTIAL-TO-3.3V LVPECL CLOCK GENERATOR
3. Calculations and Equations.
LVPECL output driver circuit and termination are shown in Figure 5.
To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load, and a termination
voltage of V
CC
- 2V.
• For logic high, VOUT = VOH_MAX = VCC_MAX – 0.9V
(VCC_MAX - VOH_MAX
) = 0.9V
• For logic low, VOUT = VOL_MAX = VCC_MAX
– 1.7V
(VCC_MAX - VOL_MAX
) = 1.7V
Pd_H is power dissipation when the output drives high.
Pd_L is the power dissipation when the output drives low.
Pd_H = [(VOH_MAX
– (VCC_MAX
- 2V))/R
L
] * (VCC_MAX
- VOH_MAX) = [(2V - (VCC_MAX - VOH_MAX
))/R
L
] * (VCC_MAX
- VOH_MAX) =
[(2V - 0.9V)/50Ω] * 0.9V = 19.8mW
Pd_L = [(VOL_MAX
– (VCC_MAX
- 2V))/R
L
] * (VCC_MAX
- VOL_MAX) = [(2V - (VCC_MAX - VOL_MAX
))/R
L
] * (VCC_MAX
- VOL_MAX) =
[(2V - 1.7V)/50Ω] * 1.7V = 10.2mW
Total Power Dissipation per output pair = Pd_H + Pd_L = 30mW
FIGURE 5. LVPECL DRIVER CIRCUIT AND TERMINATION
Q1
VOUT
VCC
RL
50
VCC - 2V
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4/5/6,
DIFFERENTIAL-TO-3.3V LVPECL CLOCK GENERATOR
RELIABILITY INFORMATION
TRANSISTOR COUNT
The transistor count for ICS87339I-11 is: 1745
Compatible with MC10EP139, MC100EP139
TABLE 7B. θJAVS. AIR FLOW SOIC TABLE
θθ
θθ
θ
JA
by Velocity (Linear Feet per Minute)
0 200 500
Single-Layer PCB, JEDEC Standard Test Boards 83.2°C/W 65.7°C/W 57.5°C/W
Multi-Layer PCB, JEDEC Standard Test Boards 46.2°C/W 39.7°C/W 36.8°C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
0 200 500
Single-Layer PCB, JEDEC Standard Test Boards 114.5°C/W 98.0°C/W 88.0°C/W
Multi-Layer PCB, JEDEC Standard Test Boards 73.2°C/W 66.6°C/W 63.5°C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
θθ
θθ
θ
JA
by Velocity (Linear Feet per Minute)
TABLE 7A. θJAVS. AIR FLOW TSSOP TABLE
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ICS87339I-11
LOW SKEW,
÷
2/4,
÷
4/5/6,
DIFFERENTIAL-TO-3.3V LVPECL CLOCK GENERATOR
PACKAGE OUTLINE - M SUFFIX FOR 20 LEAD SOIC
TABLE 8B. PACKAGE DIMENSIONS
Reference Document: JEDEC Publication 95, MS-013, MO-119
LOBMYS sretemilliM
muminiMmumixaM
N02
A--56.2
1A01.0--
2A50.255.2
B33.015.0
C81.023.0
D06.2100.31
E04.706.7
eCISAB72.1
H00.0156.01
h52
.057.0
L04.072.1
α°0°8
PACKAGE OUTLINE - G SUFFIX FOR 20 LEAD TSSOP
TABLE 8A. PACKAGE DIMENSIONS
Reference Document: JEDEC Publication 95, MO-153
LOBMYS sretemilliM
NIMXAM
N02
A--02.1
1A50.051.0
2A08.050.1
b91.003.0
c90.002.0
D04.606.6
ECISAB04.6
1E03.405.4
eCISAB56.0
L54.057.0
α°
0°8
aaa--01.0
87339AGI-11 www.idt.com REV. B AUGUST 2, 2010
13
ICS87339I-11
LOW SKEW,
÷
2/4,
÷
4/5/6,
DIFFERENTIAL-TO-3.3V LVPECL CLOCK GENERATOR
TABLE 9. ORDERING INFORMATION
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11-IGA9337811IA93378SCIPOSSTdael02ebuTC°58otC°04-
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ICIOSdael02ebuTC°58otC°04-
T11-IMA9337811-IMA93378SCICIOSdael02leeR&epaT0001C°58otC°04-
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While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology, Inc. (IDT) assumes no responsibility for either its use or for infringement of
any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and industrial
applications. Any other applications such as those requiring high reliability, or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT reserves
the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments.
87339AGI-11 www.idt.com REV. B AUGUST 2, 2010
14
ICS87339I-11
LOW SKEW,
÷
2/4,
÷
4/5/6,
DIFFERENTIAL-TO-3.3V LVPECL CLOCK GENERATOR
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87339AGI-11 www.idt.com REV. B AUGUST 2, 2010
15
ICS87339I-11
LOW SKEW,
÷
2/4,
÷
4/5/6,
DIFFERENTIAL-TO-3.3V LVPECL CLOCK GENERATOR
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