AT91M63200-12AJ-1.8 - Atmel Corporation

Features

•Utilizes the ARM7TDMI™ ARM Thumb Processor Core

– High-performance 32-bit RISC Architecture

– High-density 16-bit Instruction Set

– Leader in MIPS/Watt

– Embedded ICE (In-circuit Emulation)

•2K Bytes (M63200) or 3K Bytes (M43300) Internal RAM

•Fully-programmable External Bus Interface (EBI)

– Maximum External Address Space of 64M Bytes

– Up to 8 Chip Selects

– Software Programmable 8/16-bit External Data Bus

•Multi-processor Interface (M63200 Only)

– High-performance External Processor Interface

– 512 x 16-bit Dual-port RAM

•8-channel Peripheral Data Controller

•8-level Priority, Individually Maskable, Vectored Interrupt Controller

– 5 External Interrupts, Including a High-priority, Low-latency Interrupt Request

•58 Programmable I/O Lines

•6-channel 16-bit Timer/Counter

– 6 External Clock Inputs

– 2 Multi-purpose I/O Pins per Channel

•3 USARTs

– 2 Dedicated Peripheral Data Controller (PDC) Channels per USART

– Support for up to 9-bit Data Transfers

•Master/Slave SPI Interface

– 2 Dedicated Peripheral Data Controller (PDC) Channels

– 8- to 16-bit Programmable Data Length

– 4 External Slave Chip Selects

•Programmable Watchdog Timer

•Power Management Controller (PMC)

– CPU and Peripherals Can be Deactivated Individually

•IEEE 1149.1 JTAG Boundary-scan on All Active Pins

•Fully Static Operation: 0 Hz to 25 MHz (12 MHz at 1.8V Core, 25 MHz at 2.7V Core)

•1.8V to 3.6V Core Operating Voltage Range

•2.7V to 5.5V I/O Operating Voltage Range

•-40°C to +85°C Operating Temperature Range

•AT91M63200 in a 176-lead TQFP Package; AT91M43300 in a 144-ball BGA Package

Description

The AT91M63200 and AT91M43300 are members of the Atmel AT91 16/32-bit micro-

controller family which is based on the ARM7TDMI processor core.

This processor has a high-performance 32-bit RISC architecture with a high-density

16-bit instruction set and very low power consumption. In addition, a large number of

internally banked registers result in very fast exception handling, making the device

ideal for real-time control applications. The AT91 ARM-based MCU family also fea-

tures Atmel’s high-density, in-system programmable, nonvolatile memory technology.

Both products have a direct connection to off-chip memory, including Flash, through

the External Bus Interface.

For the AT91M63200, the Multi-processor Interface (MPI) provides a high-perfor-

mance interface with an external coprocessor or a high bandwidth peripheral.

Both products are manufactured using Atmel’s high-density CMOS technology. By

combining the ARM7TDMI microcontroller core with on-chip SRAM, a multi-processor

interface and a wide range of peripheral functions on a monolithic chip, the

AT91M63200 and AT91M43300 provide a highly-flexible and cost-effective solution to

many compute-intensive real-time applications.

AT91

ARM® Thumb®

Microcontrollers

AT91M63200

AT91M43300

Electrical

Characteristics

Rev. 1090B–06/00

AT91M63200/M43300

Absolute Maximum Ratings*

Notes: 1. See Table 4.

2. IO = Output current.

Operating Temperature (Industrial) .....-40°C to +85°C*NOTICE: Stresses beyond those listed under “Absolute Maxi-

mum Ratings” may cause permanent damage to

the device. This is a stress rating only and func-

tional operation of the device at these or other con-

ditions beyond those indicated in the operational

sections of this specification is not implied. Expo-

sure to absolute maximum rating conditions for

extended periods may affect device reliability.

Voltage on Any Input Pin

with Respect to Ground.......................-0.5V to +5.5V

Maximum Operating Voltage (Core) .....................3.6V

Maximum Operating Voltage (I/Os) ......................5.5V

DC Output Current ..............................................4 mA

DC Characteristics

Symbol Parameter Condition Min Typ Max Units

VDDCORE(1) DC Supply Voltage Core 1.8 3.6 V

VDDIO DC Supply I/Os

2.7V ≤ VDDCORE ≤ 3.6V VDDCORE

VDDCORE +

2.0 or 5.5 V

1.8V ≤ VDDCORE ≤ 2.7V 2.7 3.3

TAAmbient Temperature -40 85 °C

VIL Low-level Input Voltage -0.3 0.8 V

VIH High-level Input Voltage 2 VDDIO +

0.3 V

VOL Low-level Output Voltage

2.7 ≤ VDDIO ≤ 3.6; IO(2) = 2 mA 0.4 V

VDDCORE ≤ VDDIO ≤ 5.5V;

IO(2) = 4 mA 0.4 V

VOH High-level Output Voltage

2.7 ≤ VDDIO ≤ 3.6; IO(2) = 2 mA VDDIO - 0.4 V

VDDCORE ≤ VDDIO ≤ 5.5V;

IO(2) = 4 mA VDDIO - 0.4 V

ILEAK Input-leakage Current 100 nA

IPULL Input Pull-up Current 100 µA

ICAP Input Capacitance 12 pF

ISC Static Current VDDIO = VDDCORE = 3.6V

MCKI = 0 Hz, NRST = 1 60 µA

AT91M63200/M43300

Power Consumption

The values in the following tables are measured values in the operating conditions indicated (i.e. VDDIO = 3.3V, VDDCORE =

3.3V or 1.8V; T = 25°). They represent the power consumption on the VDDCORE power supply.

Table 1. Core Power Consumption

Mode Conditions

VDDCORE

Unit1.8V 3.3V

Reset 0.05 0.41

mW/MHz

Normal

Fetch in ARM mode out of Internal SRAM

All peripheral clocks activated 3.1 13.3

Fetch in ARM mode out of Internal SRAM

All peripheral clocks deactivated 1.8 7.4

Idle All peripheral clocks activated 2.0 8.7

All peripheral clocks deactivated 0.54 2.4

Table 2. Core Power Consumption per Peripheral

Peripheral

VDDCORE

Unit1.8V 3.3V

PIO Controller 0.07 0.32

mW/MHz

Timer Counter channel 0.07 0.28

Timer Counter Block (3 channels) 0.18 0.75

USART 0.22 0.99

SPI 0.22 1.02

AT91M63200/M43300

Conditions

Environment Constraints

The output delays are valid for a capacitive load of 50 pF as shown in Figure 1.

Figure 1. Output/Bidir Pad Capacitive Load

Timing Results

The output delays are for a capacitive load of 50 pF as shown in Figure 1.

In order to obtain the timing for other capacitance values, the following equation should be used.

In the tables that follow, the output delays are for industrial conditions only.

Volt age Ranges

Although the core may be supplied between 1.8V and 3.6V, there are two voltage ranges that have been characterized for

timing purposes.

These are from 1.8V to 2.2V (core at 2V), and 2.7V to 3.6V (core at 3.3V). Timing values are given for both sets of condi-

tions, as in Table 4.

PA D

CL = 50 pF

datasheet factor Cload 50pF–()×+=

Table 3. Derating Factor Due to Capacitive Load Variation

Parameter Industrial Units

Factor 0.058 ns/pF

Table 4. Voltage Ranges for Timing Characterization

Condition

VDDCORE VDDIO

UnitMinimum Maximum Minimum Maximum

Core at 2V 1.8 2.2 2.7 3.3 V

Core at 3.3V 2.7 3.6 2.7 5.5

AT91M63200/M43300

Clock Waveforms

Figure 2. Clock Waveform

Table 5. Clock Waveform Parameters

Symbol Parameter

Minimum Maximum

Units

Core at

3.3V

Core at

3.3V

1/(tCP) Oscillator Frequency 12 25 MHz

tCP Main Clock Period 83 40

tCH High Time TBD 18

tCL Low Time TBD 18

trRising Edge TBD 7

tfFalling Edge TBD 7

Table 6. Clock Propagation Times

Symbol Parameter

Minimum Maximum

Units

Core at

3.3V

Core at

3.3V

tCDLH Rising Edge Propagation Time TBD 20 TBD TBD ns

tCDHL Falling Edge Propagation Time TBD 18 TBD TBD

tCH

tCL tCP

MCKI

MCKO

tCDLH tCDHL

0.7 VDDIO

0.3 VDDIO

trtf

AT91M63200/M43300

AC Characteristics

EBI Signals Relative to MCKI

The following tables show timings relative to operating condition limits defined in Table 4. See Figure 3.

Table 7. General Purpose EBI Signals

Symbol Parameter

Minimum Maximum

UnitsCore at 2V Core at 3.3V Core at 2V Core at 3.3V

EBI1MCKI Falling to NUB Valid TBD 20 ns

EBI2MCKI Falling to NLB/A0 Valid TBD 20 ns

EBI3MCKI Falling to A7 - A1 Valid TBD 20 ns

EBI4MCKI Falling to A23 - A8 Valid TBD 20 ns

EBI5MCKI Falling to Chip Select TBD 5 TBD 20 ns

EBI6NWAIT Setup before MCKI Rising TBD 5 ns

EBI7NWAIT Hold after MCKI Rising TBD 4 ns

Table 8. EBI Write Signals

Symbol Parameter

Minimum Maximum

UnitsCore at 2V Core at 3.3V Core at 2V Core at 3.3V

EBI8MCKI Rising to NWR Active (No Wait

States)

TBD 20 ns

EBI9MCKI Rising to NWR Active (Wait

States)

TBD 20 ns

EBI10 MCKI Falling to NWR Inactive (No

Wait States)

TBD 20 ns

EBI11 MCKI Rising to NWR Inactive (Wait

States)

TBD 20 ns

EBI12 MCKI Rising to D0 - D15 Out Valid TBD 20 ns

EBI19 NWR High to A23 - A1, NUB/NLB/A0,

NCS, CS Changes (No Wait States)

TBD 2 ns

EBI20 NWR High to A23 - A1, NCS, CS

Changes (Wait States)

tCP/2 ns

EBI21 Data Out Valid before NWR High tCH - 5 ns

EBI22 Data Out Valid after NWR High tCP/2 ns

AT91M63200/M43300

Notes: 1. Early Read Protocol

2. Standard Read Protocol

Table 9. EBI Read Signals

Symbol Parameter

Minimum Maximum

UnitsCore at 2V Core at 3.3V Core at 2V Core at 3.3V

EBI13 MCKI Falling to NRD Valid(1) TBD 5 TBD 18

EBI14 MCKI Rising to NRD Valid(2) TBD 20

EBI15 D0 - D15 in Setup before MCKI Falling TBD 0

EBI16 D0 - D15 in Hold after MCKI Falling TBD 3

EBI17 NRD High to A23 - A1, NCS, CS

Changes

TBD 0

EBI18 Data Hold after NRD High TBD 0

AT91M63200/M43300

Figure 3. EBI Signals Relative to MCKI

Notes: 1. Early Read Protocol

2. Standard Read Protocol

NCS

A1 - A23

NRD(1)

D0 - D15 read

MCKI

NUB/NLB/A0

NRD(2)

NWAIT

NWR (No Wait States)

D0 - D15 to Write

NWR (Wait States)

No Wait Wait

EBI1/EBI2

EBI3/EBI4

EBI5

EBI6EBI7

EBI8EBI10

EBI9EBI11

EBI12

EBI13

EBI14

EBI15 EBI16

EBI13

EBI5

No Wait Wait

EBI17

EBI18

EBI19

EBI21 EBI22

EBI20

EBI22

AT91M63200/M43300

Peripheral Signals Relative to MCKI

USART Signals

The inputs can be used synchronously or asynchronously (in relation to MCKI).

For synchronous and asynchronous USART inputs, certain setup/hold constraints must be met. These constraints are

shown in Tables 11 and 12 and are represented in Figure 4.

For asynchronous inputs, a minimum pulse-width is necessary as shown in Table 13 and as represented in Figure 4.

Table 10. USART Outputs

Symbol Parameter

Minimum Maximum

UnitsCore at 2V Core at 3.3V Core at 2V Core at 3.3V

US1MCKI Rising to SCK Output

Rising/Falling

TBD TBD TBD 25 ns

US2MCKI Rising to TXD Toggling TBD TBD TBD 35 ns

US3SCK Output Falling to TXD Toggling TBD TBD TBD 10 ns

US4SCK Input Falling to TXD Toggling TBD TBD TBD 2(tCP) + 35 ns

Table 11. USART Synchronous Input Setup/Hold Constraints

Symbol Type of Input Parameter Setup Hold Units

US5Synchronous RXD Toggling Relative to MCKI Falling 0 5 ns

US6Synchronous SCK Input Rising Relative to MCKI Rising 0 5 ns

US7Synchronous SCK Input Falling Relative to MCKI Rising 0 5 ns

Table 12. USART Asynchronous Input Setup/Hold Constraints

Symbol Type of Input Parameter Setup Hold Units

US8Asynchronous RXD Toggling Relative to SCK Input Rising tCP/2 - 2 tCP/2 + 2 ns

Table 13. USART Asynchronous Input Minimum Pulse-width

Symbol Type of Input Parameter Pulse-width Units

US9Asynchronous RXD/SCK Minimum Pulse-width 3(tCP/2) ns

AT91M63200/M43300

Figure 4. USART Signals Relative to MCKI

SCK Output

MCKI

SCK Input

TXD

RXD

US5S US5H

US2

US1

US3

US1

US4

US6H

US7H

US8S

US6S

US7S

US8H

RXD/SCK

(Asynchronous)

US9

AT91M63200/M43300

SPI Signals

Figure 5. SPI Signals

Table 14. SPI Signals in Master Mode

Symbol Parameter

Minimum Maximum

UnitsCore at 2V Core at 3.3V Core at 2V Core at 3.3V

tSPCK SPI Operating Period 4(tCP) 16320(tCP)ns

fSPCK SPI Operating Frequency 1/16320(tCP)1/4(t

CP)GHz

SP1Delay before NPCS[3:0] 4(tCP) 261120(tCP)ns

SP2Delay between Chip Selects 6(tCP) 8160(tCP)ns

SP3Delay before SPCK 2(tCP) 8160(tCP)ns

SP4MISO/SPCK Setup Time TBD 18 ns

SP5MISO/SPCK Hold Time TBD 0 ns

SP6MOSI Valid after SPCK Edge TBD 7 ns

SP1

SP2

SP3

tSPCK

SP4SP5

SP6

MSB In Data LSB In

MSB Out Data LSB Out

NPCS[3:0]

output

SPCK

Output

CPOL = 0

SPCK

Output

CPOL = 1

MISO

Input

MOSI

Output

AT91M63200/M43300

Timer Counter Signals

Due to internal synchronization of input signals, there is a delay between an input event and a corresponding output event.

This delay is 3(tCP) in Waveform Event Detection mode and 4(tCP) in Waveform Total-count Detection mode. In addition

there are the following delays relative to MCKI waveforms.

The inputs can be used synchronously or asynchronously (in relation to MCKI).

For synchronous Timer inputs, certain setup/hold constraints must be met. These constraints are shown in the Table 16

and are represented in Figure 6.

For asynchronous inputs, a minimum pulse-width and a minimum input period are necessary as shown in Tables 17 and 18

and as represented in Figure 6.

Table 15. Timer Outputs

Symbol Parameter

Maximum

UnitsCore at 2V Core at 3.3V

TC1MCKI Rising to TIOA Rising TBD 22

TC2MCKI Rising to TIOA Falling TBD 22

TC3MCKI Rising to TIOB Rising TBD 22

TC4MCKI Rising to TIOB Falling TBD 22

Table 16. Synchronous Timer Inputs

Symbol Type of Input Parameter

Setup Hold

Units

Core at

3.3V

Core at

3.3V

TC5Synchronous TIOA/TIOB Rising Relative to MCKI Rising TBD 2 TBD 5

TC6Synchronous TIOA/TIOB Falling Relative to MCKI

Rising

TBD 2 TBD 5

TC7Synchronous TCLK Rising Relative to MCKI Rising TBD 2 TBD 5

TC8Synchronous TCLK Falling Relative to MCKI Rising TBD 2 TBD 5

Table 17. Asynchronous Timer Input Minimum Pulse-width

Symbol Type of Inputs Parameter Pulse-width Units

TC9 Asynchronous TCLK/TIOA/TIOB Minimum Pulse-width 3(tCP/2) ns

Table 18. Asynchronous Timer Input Minimum Input Period

Symbol Type of Inputs Parameter Input Period Units

TC10 Asynchronous TCLK/TIOA/TIOB Minimum Input Period 5(tCP/2) ns

AT91M63200/M43300

Figure 6. Timer Relative to MCKI

TC1TC2

TC3TC4

MCKI

TIOA/TIOB/TCLK

Asynchronous In

TCLK

Synchronous Input

TIOA/TIOB

Synchronous Inputs

TIOA

Output

TIOB

Output

TC5H TC5S TC6S

TC6H

TC7H TC7S TC8H TC8S

TC9

3(tCP/2) 1(tCP)

Detect

TC10

AT91M63200/M43300

Watchdog Timer Signals

Figure 7. Watchdog Signals Relative to MCKI

Reset Signals

Certain setup constraints must be met. These constraints are shown in Table 20 and are represented in Figure 8.

A minimum pulse width is necessary as shown in Table 21 and as represented in Figure 8.

Figure 8. Reset Signals Relative to MCKI

Only the NRST rising edge is synchronized. The falling edge is asynchronous.

Table 19. Watchdog Timer Outputs

Symbol Parameter

Maximum

UnitsCore at 2V Core at 3.3V

WD1MCKI Rising to NWDOVF Rising TBD 20 ns

WD2MCKI Rising to NWDOVF Falling TBD 20

MCKI

NWDOVF Output

WD1WD2

Table 20. Reset Setup Constraints

Symbol Parameter

Setup

UnitsCore at 2V Core at 3.3V

RST1NRST Rising Related to MCKI Rising TBD 5 ns

Table 21. Reset Minimum Pulse-width

Symbol Parameter Pulse-width Units

RST3NRST Minimum Pulse-width 10(tCP)ns

MCKI

NRST

RST1H RST1S

RST3

AT91M63200/M43300

Advanced Interrupt Controller Signals

The inputs can be used synchronously or asynchronously (in relation to MCKI).

For synchronous AIC inputs, certain setup/hold constraints must be met. These constraints are shown in Table 22 and are

represented in Figure 9.

For asynchronous inputs, a minimum pulse width is necessary as shown in Table 23 and as represented in Figure 9.

Figure 9. AIC Signals Relative to MCKI

Table 22. AIC Synchronous Input Setup/Hold Constraints

Symbol Type Parameter

Setup Hold

Units

Core

at 2V

Core

at 3.3V

Core

at 2V

Core

at 3.3V

AIC1Synchronous FIQ/IRQ0/IRQ1/IRQ2/IRQ3 Rising.

Relative to MCKI Rising TBD 0 TBD 4 ns

AIC2Synchronous FIQ/IRQ0/IRQ1/IRQ2/IRQ3 Falling.

Related to MCKI Rising TBD 0 TBD 4 ns

Table 23. AIC Asynchronous Input Minimum Pulse-width

Symbol Type Parameter Pulse-width Units

AIC5Asynchronous FIQ/IRQ0/IRQ1/IRQ2/IRQ3 Minimum Pulse-width 3(tCP/2) ns

Table 24. AIC Asynchronous Input Minimum Input Period

Symbol Type Parameter Input Period Units

AIC6Asynchronous AIC Minimum Input Period 5(tCP/2) ns

MCKI

AIC1H

FIQ/IRQ0/IRQ1/IRQ2/IRQ3

Synchronous Input

FIQ/IRQ0/IRQ1/IRQ2/IRQ3

Asynchronous Input

AIC1S AIC2H AIC1S

AIC5

AIC6

AT91M63200/M43300

Parallel I/O Signals

The inputs can be used synchronously or asynchronously (in relation to MCKI).

For synchronous PIO inputs, certain setup/hold constraints must be met. These constraints are shown in the Table 26 and

are represented in Figure 10.

For asynchronous inputs, a minimum pulse width is necessary as shown in Table 27 and as represented in Figure 10.

Figure 10. PIO Signals Relative to MCKI

Table 25. PIO Outputs

Symbol Parameter

Maximum

UnitsCore at 2V Core at 3.3V

PIO1MCKI Falling to PIO Output Rising TBD 22 ns

PIO2MCKI Falling to PIO Output Falling TBD 22 ns

Table 26. PIO Synchronous Input Setup/Hold Constraints

Symbol Type Parameter

Setup Hold

Units

Core

at 2V

Core

at 3.3V

Core

at 2V

Core

at 3.3V

PIO3Synchronous PIO Input Rising Related to MCKI Rising TBD 2 TBD 5 ns

PIO4Synchronous PIO Input Falling Related to MCKI Rising TBD 2 TBD 5 ns

Table 27. PIO Asynchronous Input Minimum Pulse-width

Symbol Type Parameter Pulse-width Units

PIO5Asynchronous PIO Input Minimum Pulse-width 3(tCP/2) ns

MCKI

PIO

Synchronous Inputs

PIO

Asynchronous Inputs

PIO

Outputs

PIO1PIO2

PIO3H PIO3S PIO4H PIO4S

PIO5

AT91M63200/M43300

Multi-processor Interface Signals (AT91M63200 Only)

Figure 11. External Arbitration

Data Transfer

MPI_BR

MPI_BG

MPI_D[15:0]

Table 28. External Arbitration

Symbol Parameter

Minimum Maximum

UnitsCore at 2V Core at 3.3V Core at 2V Core at 3.3V

MPI_BR High to MPI_BG High Delay

(30 pf) tCP 2 x tCP + 12 ns

t2MPI_BR Low to MPI_BG Low TBD 12

AT91M63200/M43300

Figure 12. MPI Read Access

Table 29. MPI Read Access

Symbol Parameter

Minimum Maximum

UnitsCore at 2V Core at 3.3V Core at 2V Core at 3.3V

tRC Read Cycle Time TBD 22 ns

tAA Address Access Time TBD 22 ns

tACS Chip Select Access Time TBD 22 ns

tOE Output Enable to Output Valid TBD 10 ns

tLB, tUB Byte Select to Output Valid TBD 10 ns

tOH Output Hold from Address Change TBD 0 ns

tCLZ Chip Select to Output in Low-Z TBD 0 ns

tOLZ Output Enable to Output in Low-Z TBD 0 ns

tLBLZ,

tUBLZ

Byte Select to Output in Low-Z TBD 0 ns

tCHZ Chip Deselect to Output in High-Z TBD 7 ns

tOHZ Output Disable to Output in High-Z TBD 7 ns

tLBHZ,

tUBHZ

Byte Deselect to Output in High-Z TBD 7 ns

MPI_A[9:1]

MPI_NCS

MPI_D[15:0] High Impedance Valid Data

MPI_NOE

MPI_NLB, MPI_NUB

Valid Address

tRC

tOH

tCHZ

tOHZ

tLBHZ

tAA

tACS

tUBHZ

tUB

tLB

tOE

tOLZ tLBLZ tUBLZ

tCLZ

AT91M63200/M43300

Figure 13. MPI Write Access (MPI_RNW Controlled)

Table 30. MPI Write Access

Symbol Parameter

Minimum Maximum

UnitCore at 2V Core at 3.3V Core at 2V Core at 3.3V

tWC Write Cycle Time TBD 10 ns

tAW Address Valid to End of Write TBD 10 ns

tCW Chip Select to End of Write TBD 10 ns

tWP Write pulse-width TBD 10 ns

tLBW, tUBW Byte Select to End of Write TBD 10 ns

tAS Address Setup Time TBD 0 ns

tWR Write Recovery Time TBD 0 ns

tDW Data Valid to End of Write TBD 10 ns

tDH Data Hold Time from End of Write TBD 0 ns

tOW Write Disable to Output in Low-Z TBD 10 ns

tWHZ Write Enable to Output in High-Z TBD 7 ns

MPI_A[9:1]

MPI_RNW

Valid Data

Valid Address

high-Z

High-ZHigh-Z

MPI_NCS

MPI_NLB, MPI_NUB

MPI_Dout[15:0]

MPI_Din[15:0]

tWC

tAW

tAS

tWR

tWP

tCW

tLBW tUBW

tWHZ tOW

tDH

tDW

AT91M63200/M43300

Figure 14. MPI Write Access (MPI_NCS Controlled)

Figure 15. MPI Write Access (MPI_NLB, MPI_NUB Controlled)

MPI_A[9:1]

MPI_RNW

Valid Data

Valid Address

High-ZHigh-Z

MPI_NCS

MPI_NLB, MPI_NUB

MPI_Din[15:0]

LBW

UBW

MPI_A[9:1]

MPI_RNW

Valid Data

Valid Address

High-ZHigh-Z

MPI_NCS

MPI_NLB, MPI_NUB

MPI_Din[15:0]

tWC

tAW

tAS

tWR

tWP

tLBW tUBW

tDH

tDW

tCW

Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company’s standard war-

ranty which is detailed in Atmel’s Terms and Conditions located on the Company’s web site. The Company assumes no responsibility for

any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without

notice, and does not make any commitment to update the information contained herein. No licenses to patents or other intellectual prop-

erty of Atmel are granted by the Company in connection with the sale of Atmel products, expressly or by implication. Atmel’s products are

not authorized for use as critical components in life support devices or systems.

Atmel Headquarters Atmel Operations

Corporate Headquarters

2325 Orchard Parkway

San Jose, CA 95131

TEL (408) 441-0311

FAX (408) 487-2600

Europe

Atmel U.K., Ltd.

Coliseum Business Centre

Riverside Way

Camberley, Surrey GU15 3YL

England

TEL (44) 1276-686-677

FAX (44) 1276-686-697

Asia

Atmel Asia, Ltd.

Room 1219

Chinachem Golden Plaza

77 Mody Road Tsimhatsui

East Kowloon

Hong Kong

TEL (852) 2721-9778

FAX (852) 2722-1369

Japan

Atmel Japan K.K.

9F, Tonetsu Shinkawa Bldg.

1-24-8 Shinkawa

Chuo-ku, Tokyo 104-0033

Japan

TEL (81) 3-3523-3551

FAX (81) 3-3523-7581

Atmel Colorado Springs

1150 E. Cheyenne Mtn. Blvd.

Colorado Springs, CO 80906

TEL (719) 576-3300

FAX (719) 540-1759

Atmel Rousset

Zone Industrielle

13106 Rousset Cedex

France

TEL (33) 4-4253-6000

FAX (33) 4-4253-6001

Fax-on-Demand

North America:

1-(800) 292-8635

International:

1-(408) 441-0732

e-mail

literature@atmel.com

Web Site

http://www.atmel.com

BBS

1-(408) 436-4309

Printed on recycled paper.

1090B–06/00/0M

ARM, Thumb and ARM Powered are registered trademarks of ARM Limited.

ARM7TDMI is a trademark of ARM Ltd.

All other marks bearing ® and/or ™ are registered trademarks and trademarks of Atmel Corporation.

Terms and product names in this document may be trademarks of others.