1 February 29, 2000
U62H256S
Features
F32768 x 8 bi t static CMOS RAM
F35 and 55 ns Access Time
FCommon data inputs and
data outputs
FThree-state outputs
FTyp. operating supply current
35 ns: 45mA
55 ns: 30mA
FStandby current < 1mA at 125°C
FTTL/CMOS-compatible
FAutomatic reducti on of power
dissipation in long Read or Write
cycles
FPower s upply voltage 5 V
FOperating temperature range
-40 °C to 85 °C
-40 °C to 125 °C
FCECC 90000 Qua lity Standard
FESD protection > 2000 V
(MIL STD 883C M3015.7)
FLatch-up im mun ity >100 mA
FPackage: SOP28 (300/330 mil)
Description
The U62H256S is a static RAM
manufactured using a CMOS pro-
cess technology with the following
operating modes:
- Read - Standby
- Write - Data Retention
The memory array is based on a
MI XMOS ce ll.
The circuit is activated by the fal-
ling edge of E. The address and
control inputs open simultaneously.
According to the information of W
and G, the data inputs, or outputs,
are active. During the active state
E = L each address change leads
to a new Read or Write cycle. In a
Read cycle, the data outputs are
activated by the falling edge of G,
afterwards the data word will be
available at the outputs DQ0-DQ7.
After the address change, the data
outputs go High-Z until the new
information is available. The data
outputs have no preferred state. If
the memory is driven by CMOS
levels in the active state, and if
there is no change of the address,
data input and control signals W or
G, the operating current (IO = 0 mA)
drops to the value of the operating
current in the Standby mode. The
Read cycle is finished by the falling
edge of W, or by the rising edge of
E, respectively.
Data retention is guaranteed down
to 2 V. With the exception of E, all
inputs consist of NOR gates, so that
no pull-up/pull-down resistors are
required.
Automotive Fast 32K x 8 SRAM
Pi n Configu rati on
Top View
Signal Name Signal Descripti on
A0 - A14 Address Inputs
DQ0 - DQ7 Data In/Out
EChip Enabl e
GOutput Enable
WWr it e Enable
VCC Power Supply Voltage
VSS Ground
Pi n De scr i pt ion
1
A14 VCC28
2A12 W
27
4A6 A825
5A5 A924
3A7 A1326
6A4 A1123
7A3 G
22
8A2 A1021
12DQ1 DQ517
9A1 E
20
10
A0 DQ719
11DQ0 DQ618
13DQ2 DQ416
14VSS DQ315
SOP
2 February 29, 200 0
U62H256S
*H or L
Ope rat in g Mode E W G DQ0 - DQ7
Standby/not selected H * * High-Z
Internal Read L H H High-Z
Read L H L Data Output s Low-Z
Write L L * Data Inputs Hi gh-Z
Truth Table
Block Diagram
Maxim um Ratings Symb ol Min. Max. Unit
Power Supply Voltage VCC -0.5 7 V
Input Voltage VI-0.5 VCC + 0.5 V
Outpu t Vol tage VO-0.5 VCC + 0.5 V
Power Dissipa tion PD-1W
Operating Temperature K-Type
A-Type Ta-40
-40 85
125 °C
Storage Temperature Tstg -65 150 °C
Outpu t Short-Circuit Current
at VCC = 5 V and VO = 0 V** | IOS | 200 mA
Characteristics
**Not more than 1 ou tput should be shorted at the same time. Duration of the short circuit should n ot excee d 30 s.
All voltages are referenced to VSS = 0 V (ground).
All characteristics are valid in the power supply voltage range and in the operating temperature range specified.
Dynamic measurement s are based on a rise and fall time of £ 5 ns, measured between 10 % and 90 % of VI,as well as
input levels of VIL = 0 V and VIH = 3 V. The timing reference level of all input and outp ut sign als is 1.5 V,
with the ex ception of the tdis-time s and ten-times, in which ca ses transition i s measur ed ±200 mV from steady-state voltage.
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
VCC VSS W GE
Row Address
Inputs
Column Address
Inputs
Address
Change
Detector
Column Decoder Row Decode r
Sense Amplifier/
Write Control Logic
Clock
Generator
Com mon Data I/O
Memory Cell
Array
256 Rows x
128 x 8 Columns
A0
A1
A2
A3
A10
A5
A6
A7
A8
A9
A4
A11
A12
A13
A14
3 February 29, 2000
U62H256S
* -2 V at Pu ls e Wi dth 10 ns
Recommended
Operatin g Condi tions Symbol Conditions Min. Max. Unit
Power Supply Voltage VCC 4.5 5.5 V
Input Low Voltage*VIL -0.3 0.8 V
Input High Voltage VIH 2.2 VCC + 0.3 V
Electrical Characteri stics Symbol Condition s Min. Max. Unit
Supply Current - Operating Mode
Supply Current - Standby Mode
(CMOS level)
Supply Current - Standby Mode
(TTL level)
ICC(OP)
ICC(SB)
ICC(SB)1
VCC
VIL
VIH
tcW
tcW
VCC
VE
T
T
T
T
VCC
VE
K-Type
A-Type
= 5.5 V
= 0.8 V
=2.2 V
= 35 ns
= 55 ns
=5.5 V
= VCC - 0.2 V
= 40 °C
= 85 °C
= 110 °C
= 125 °C
= 5.5 V
= 2.2 V
90
70
8
150
500
1000
10
20
mA
mA
µA
µA
µA
µA
mA
mA
Output High Volt age
Output Low Voltage
VOH
VOL
VCC
IOH
VCC
IOL
= 4.5 V
=-4.0 mA
=4.5 V
=8.0 mA
2.4
0.4
V
V
Input High Leakage Current
Input Low Leakage Curren t
IIH
IIL
VCC
VIH
VCC
VIL
= 5.5 V
= 5.5 V
= 5.5 V
= 0 V -2
2µA
µA
Output High Current
Output Low Current
IOH
IOL
VCC
VOH
VCC
VOL
=4.5 V
=2.4 V
=4.5 V
=0.4 V 8
-4 mA
mA
Output Leakage Current
High at Three-State Outputs
Low at Three-State Out puts
IOHZ
IOLZ
VCC
VOH
VCC
VOL
=5.5 V
=5.5 V
=5.5 V
=0 V -2
2µA
µA
4 February 29, 200 0
U62H256S
Switching Characteristics
Read Cycle
Symbol 35 55 Unit
Alt. IEC Min. Max. Min. Max.
Read Cycle T i me tRC tcR 35 55 ns
Addre ss Acce ss Time to Data Val i d tAA ta(A) 35 55 ns
Chip Enable Access Time to Data Valid tACE ta(E) 35 55 ns
G LOW to Data Valid tOE ta(G) 15 25 ns
E HIGH to Output in High-Z tHZCE tdis(E) 12 15 ns
G HIGH to Output in High-Z tHZOE tdis(G) 12 15 ns
E LOW to Ou tp ut in L o w -Z tLZCE ten(E) 33ns
G LOW to Output in Low-Z tLZOE ten(G) 00ns
Output Hold Time from Address Change tOH tv(A) 33ns
E LOW to Power-Up Time tPU 00ns
E HIGH to Po wer-Down T ime tPD 35 55 ns
Switching Characteristics
Write Cycle
Symbol 35 55 Unit
Alt. IEC Min. Max. Min. Max.
Write Cycle Time tWC tcW 35 55 ns
Write Pulse Width tWP tw(W) 20 35 ns
Write Setup Time tWP tsu(W) 20 35 ns
Address Setup Time tAS tsu(A) 00ns
Address Valid to End of Write tAW tsu(A-WH) 20 40 ns
Chip Enable Setup Time tCW tsu(E) 25 40 ns
Pulse Width Chip Enable to End of Wri te tCW tw(E) 25 40 ns
Da ta Setup Ti m e tDS tsu(D) 15 25 ns
Data Hold Time tDH th(D) 00ns
Address Hold from End of Write tAH th(A) 00ns
W LOW to Output in High-Z tHZWE tdis(W) 15 20 ns
G HIGH to Output in High-Z tHZOE tdis(G) 12 15 ns
W HIGH to Output in Low-Z tLZWE ten(W) 00ns
G LOW to Output in Low-Z tLZOE ten(G) 00ns
5 February 29, 2000
U62H256S
Data Retention Mode
Data Retention
Characteristics Symbol Conditions Min. Typ. Max. Unit
Alt. IEC
Data Retent i on Supply Voltage VCC(DR) 25.5V
Data Retention Supply Current ICC(DR) VCC(DR) = 3 V
VE = VCC(DR) - 0.2 V
T = 40 °C
T = 85 °C
T = 110 °C
T = 125 °C
5
90
300
600
µA
µA
µA
µA
Data Retention Setup Time tCDR tsu(DR) See Data Retention
Waveforms (above) 0ns
Operat ing Recovery Time tRtrec tcR ns
Data Retention
4.5 V
tsu(DR) trec
VCC
E
VCC(DR) ³ 2 V
0 V
2.2 V
2.2 V
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
Test Con figura tion for Functional Check
VIH
VIL
VSS
VCC
5 V
481
255
30 pF1)
VO
1) In measurement of tdis(E),tdis(W), ten(E), ten(W), ten(G) the capacitance is 5 pF.
Input level according to the
relevant test measurem ent
Simultaneo us measure-
ment of all 8 output pins
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
E
W
G
E - controlled
VCC(DR) - 0. 2 V £ VE(DR) £ VCC(DR) + 0.3 V
6 February 29, 200 0
U62H256S
All pins not under test must be connec ted with ground by capacitors.
Capacitance Conditions Symbol Min. Max. Unit
Input Capacitance VCC
VI
f
Ta
= 5.0 V
= VSS
= 1 MHz
= 25 °C
CI7pF
Output Cap acitance Co7pF
IC Code Numbers
U62H256 SA35
Type
Package
S = SOP28 300 mil
S1 = SOP2 8 33 0 mi l
Operating Temp eratu re Range
K = -40 to 85 °C
A = -40 to 125 °C
Access Time
35 = 35 ns
55 = 55 ns
The date of manufacture is given by the last 4 digits of the mark, the f irst 2 digits indicating the year, and the last 2
digits the calendar week.
7 February 29, 2000
U62H256S
tPU
tdis(G)
tdis(E)
tcR
Previous
Data Va lid Output Data
Valid
Ad dress Va lid
Addres s Valid
tsu(A)
High-Z
ten(E)
ten(G)
ta(G)
ta(E)
Read Cycle 1: Ai-cont rol le d (d uri ng Read Cy cl e : E = G = VIL, W = VIH)
Read Cycle 2: G-, E-cont rolled (during Read Cycle: W = VIH)
ta(A)
tcR
tv(A)
Ai
DQi
Output
Ai
G
DQi
Output tPD
ICC(OP)
ICC(SB) 50 % 50 %
Output Data
Valid
E
8 February 29, 200 0
U62H256S
L- to H-level undefined H- to L-level
The information describes the type of component an d shall not be c onsidered as assured characteristics.Terms of delivery and
rights to change design reserved.
In p ut Dat a
Valid
Write Cycl e1: W-controlled
Write Cycle 2: E-contro lled
tsu(A)
th(D)
Ai
E
W
DQi
Input
G
DQi
Output
tcW
tw(E) th(A)
tsu(W)
tsu(D)
tdis(W)
t
en(E)
High-Z
th(D)
Ai
E
W
DQi
Input
G
DQi
Output
tcW
tsu(E) th(A)
tw(W)
tsu(A)
tsu(D)
tdis(W) ten(W)
Address Valid
Input Data
Valid
High-Z
tsu(A-WH)
Address Vali d
Zentrum Mikroelektronik Dresden GmbH
Grenzstra ße 28 · D-01109 Dresden · P. O. B. 80 01 34 · D-01101 Dresden · Ge rmany
Phone: +49 351 8822 306 · Fax: +49 351 8822 337 · Email: sales@zmd.de · http://www.zmd.de
February 29, 2000
U62H256S
LIFE SUPPORT POL ICY
ZMD products are not designed, intended, or authorized for use as components in
systems intended for surgical implant into the body, or other applications intended
to s upport or sustain life, or for any other a pplication in which the failure of the
ZMD product could create a situation where personal injury or death may occur.
Components used in l ife-support devices or systems must be expressly authorized
by ZMD for such purpose.
LIMITED WARRANTY
The information in this document has been carefully checked and is believed to be
reliable. However Zentrum Mikroelektronik Dresden GmbH (ZMD) makes no
guarantee or warranty concerning the accuracy of said information and shall not
be resp onsible for any loss or damage of whatever nature resulting from the use
of, or reliance upon it. The information in this document describes the type of com-
ponent and shall not be considered as assured characteristics.
ZMD does not guarantee that the use of any in formation con t aine d h erein will not
infringe upon the patent, trademark, copyright, mask work right or other rights of
third p arties, and no patent or licence is implied hereby. This document does not in
any way extent ZMD’ s warranty on any product beyond that set forth in its stan-
dard ter ms and condi t ions of sale.
ZMD reserves terms of delivery and reserves the right to make changes in the
products or specifications, or both, presented in this publication at any time and
witho ut notice.
32
Dimensions in millimetres
Based on IEC 191-2Q: Type 075E06 B
1 Dimensions
Dimensions of Sub-Group B1 Dimensions of Sub-Group C1
Amax 2,65 Amin 2,35
bPmin 0,35 A1min 0,10
bPmax 0,49 A1max 0,30
enom 1,27 A2min 2,25
HEmin 10,00 A2max 2,45
HEmax 10,65 cmin 0,23
LPmin 0,40 cmax 0,32
Zmax 0,81 Dmin* 17,70
Dmax* 18,10
2 Weight ≤ 0,8 g Emin* 7,40
3 Package Body Material Low Stress Epoxy Emax* 7,60
4 Lead Material FeNi-Alloy or Cu-Alloy kmin 0,25
5 Lead Finish solder plating θmin 0°
6 Lead Form Z-bends θmax 8°
* without mold-flash
View X
θ
LP
A1
c
X
0,1
A
A2
Zbp
e
E
M
0,2
D
HE
1
28
k x 45°
ZMD-Standard November 1995
Supersedes
Edition 06.92
1. Amendment 09.93
Package SOP28
(300 mil) MDS
715
Zentrum Mikroelektronik Dresden
Doc-No.
QS-000715-HD-02
33
Dimensions in millimetres
Based on JEDEC: JEP95 MO-059 AC
1 Dimensions
Dimensions of Sub-Group B1 Dimensions of Sub-Group C1
Amax 2,54 Amin 2,25
bPmin 0,35 A1min 0,10
bPmax 0,50 A1max 0,30
enom 1,27 cmin 0,14
HEmin 11,76 cmax 0,32
HEmax 12,12 Dmin 17,90
LPmin 0,50 Dmax* 18,30
Emin 8,60
2 Weight ≤ 0,8 g Emax* 8,90
3 Package Body Material Low Stress Epoxy θmin 0°
4 Lead Material FeNi-Alloy or Cu-Alloy θmax 8°
5 Lead Finish solder plating * without mold-flash
6 Lead Form Z-bends
0,1
X
A
bp
e
E
M
0,2
D
HE
1
28
ZMD-Standard November 1995
Supersedes
Edition 09.93
Package SOP28
(330 mil) MDS
733
Zentrum Mikroelektronik Dresden
Doc-No.
QS-000733-HD-02
View X
θ
LP
A1
c
