LP2902MNOPB - NATIONAL SEMICONDUCTOR

LMX2541

LMX2541 Ultra-Low Noise PLLatinum Frequency Synthesizer with Integrated VCO

Literature Number: SNOSB31G

LMX2541

November 1, 2010

Ultra-Low Noise PLLatinum Frequency Synthesizer with

Integrated VCO

General Description

The LMX2541 is an ultra low noise frequency synthesizer

which integrates a high performance delta-sigma fractional N

PLL, a VCO with fully integrated tank circuit, and an optional

frequency divider. The PLL offers an unprecedented normal-

ized noise floor of -225 dBc/Hz and can be operated with up

to 104 MHz of phase-detector rate (comparison frequency) in

both integer and fractional modes. The PLL can also be con-

figured to work with an external VCO.

The LMX2541 integrates several low-noise, high precision

LDOs and output driver matching network to provide higher

supply noise immunity and more consistent performance,

while reducing the number of external components. When

combined with a high quality reference oscillator, the

LMX2541 generates a very stable, ultra low noise signal.

The LMX2541 is offered in a family of 6 devices with varying

VCO frequency range from 1990 MHz up to 4 GHz. Using a

flexible divider, the LMX2541 can generate frequencies as

low as 31.6 MHz. The LMX2541 is a monolithic integrated

circuit, fabricated in a proprietary BiCMOS process. Device

programming is facilitated using a three-wire MICROWIRE

interface that can operate down to 1.6 volts. Supply voltage

ranges from 3.15 to 3.45 volts. The LMX2541 is available in

a 36 pin 6x6x0.8 mm Lead-Free Leadless Leadframe Pack-

age (LLP).

Device VCO Frequency

LMX2541SQ2060E 1990 - 2240

LMX2541SQ2380E 2200 - 2530

LMX2541SQ2690E 2490 - 2865

LMX2541SQ3030E 2810 - 3230

LMX2541SQ3320E 3130 - 3600

LMX2541SQ3740E 3480 - 4000

Features

■Very Low RMS Noise and Spurs

—-225 dBc/Hz Normalized PLL Phase Noise

—Integrated RMS Noise (100 Hz - 20 MHz)

■2 mrad (100 Hz - 20 MHz) at 2.1 GHz

■3.5 mrad (100 Hz - 20 MHz) at 3.5 GHz

■Ultra Low-Noise Integrated VCO

■External VCO Option (Internal VCO Bypassed)

■VCO Frequency Divider 1 to 63 (all values)

■Programmable Output Power

■Up to 104 MHz Phase Detector Frequency

■Integrated Low-Noise LDOs

■Programmable Charge Pump Output

■Partially Integrated Loop Filter

■Digital Frequency Shift Keying (FSK) Modulation Pin

■Integrated Reference Crystal Oscillator Circuit

■Hardware and Software Power Down

■FastLock Mode and VCO-Based Cycle Slip Reduction

■Analog and Digital Lock Detect

■1.6 V Logic Compatibility

Target Applications

■Wireless Infrastructure (UMTS, LTE, WiMax)

■Broadband Wireless

■Wireless Meter Reading

■Test and Measurement

System Diagram

30073322

LMX2541 Ultra-Low Noise PLLatinum Frequency Synthesizer with Integrated VCO

LMX2541 Frequency Coverage

VCO

_DIV

2060E 2380E 2690E 3030E 3320E 3740E

Start Stop Start Stop Start Stop Start Stop Start Stop Start Stop

1 1990.0 2240.0 2200.0 2530.0 2490.0 2865.0 2810.0 3230.0 3130.0 3600.0 3480.0 4000.0

2 995.0 1120.0 1100.0 1265.0 1245.0 1432.5 1405.0 1615.0 1565.0 1800.0 1740.0 2000.0

3 663.3 746.7 733.3 843.3 830.0 955.0 936.7 1076.7 1043.3 1200.0 1160.0 1333.3

4 497.5 560.0 550.0 632.5 622.5 716.3 702.5 807.5 782.5 900.0 870.0 1000.0

5 398.0 448.0 440.0 506.0 498.0 573.0 562.0 646.0 626.0 720.0 696.0 800.0

6 331.7 373.3 366.7 421.7 415.0 477.5 468.3 538.3 521.7 600.0 580.0 666.7

7 284.3 320.0 314.3 361.4 355.7 409.3 401.4 461.4 447.1 514.3 497.1 571.4

8 248.8 280.0 275.0 316.3 311.3 358.1 351.3 403.8 391.3 450.0 435.0 500.0

…………………………………

63 31.6 35.6 34.9 40.2 39.5 45.5 44.6 51.3 49.7 57.1 55.2 63.5

All devices have continuous frequency coverage below a di-

vide value of 8 (7 for most devices) down to their minimum

frequency achievable with divide by 63. The numbers in bold

show the upper end of this minimum continuous frequency

range. For instance, the LMX2541SQ3740E option offers

continuous frequency coverage from 55.2 MHz to 571.4 MHz

and LMX2541SQ2060E offers continuous frequency cover-

age from 31.6 MHz to 280 MHz. If using the part in External

VCO mode, all parts have roughly the same performance and

any option will do.

Determining the Best Frequency Option of the LMX2541 to Use

When there are multiple devices that can satisfy the frequen-

cy requirement, performance characteristics can sometimes

be used to make a decision. Consider the following example

of where an output frequency of 1200 to 1250 MHz is desired

with a channel spacing of 100 kHz. From the frequency table,

the LMX2541SQ2380E could be used with with a divide value

of 2, or the LMX2541SQ3740E option could be used with a

divide value of 3. This raises the question: Which one has

better performance? The following table is helpful in compar-

ing the performance.

Performance

Characteristic

What Makes

it Better Why

Fractional Spurs

and

Fraction Noise

Larger Value

of VCO_DIV

Fractional spurs at the VCO are independent of VCO frequency, but when the VCO frequency

is divided down by a factor of VCO_DIV, the fractional spurs improve by a factor of 20·log

(VCO_DIV). Also, the fractional channel spacing can be made wider at the VCO, which makes

the fractional spurs farther from the carrier.

The fractional noise of the modulator is divided down in a similar way as fractional spurs. In

applications where this is dominant, this larger division can have an impact. Consult the

applications section for more information on the fractional phase noise.

VCO Phase

Noise

Operating in

the lower

frequency

range of the

VCO

At the lower end of the tuning range, the VCO phase noise is less because the tuning gain is

less. This provides better phase noise, even accounting for the difference in frequency.

Considering the fractional spurs and phase noise, the channel

spacing at the 2380E VCO would be 200 kHz. When this is

divided by two, the offset of these spurs does not change and

the spurs at the VCO output would be reduced by a factor of

20·log(2) = 6 dB. The channel spacing at the 3740E VCO

would be 300 kHz and these spurs would be reduced by a

factor of 20·log(3) = 9.5 dB. So the spurs of the 3740E option

would probably be better by virtue of the fact that they are

farther from the carrier and easier to filter and also that they

are divided down more by the VCO divider. The fractional

phase noise would also be (9.5 - 6) = 3.5 dB better by the

same reasoning.

Now consider the VCO phase noise. For the 3740E option,

1200 - 1250 MHz corresponds to a VCO frequency of 3600 -

3750 MHz, which is closer to the lower end of the tuning range

for this device. For the 2380E option, this would correspond

to 2400 - 2500 MHz, which is closer to the higher end of the

tuning range.. To verify this, take the phase noise numbers

from the electrical specifications, extrapolate them to the ac-

tual frequencies, and then subtract a factor of 20·log

(VCO_DIV). For the 2380E option, this works out to -116 dBc/

Hz at 1200 MHz and -115.4 dBc/Hz at 1250 MHz. For the

3740E option, this works out to -117.4 dBc/Hz at 1200 MHz

and -116.9 dBc/Hz at 1250 MHz.

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LMX2541

Functional Block Diagram

30073301

Connection Diagram

36-Pin SQ Package (Top View)

30073302

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LMX2541

Pin Descriptions

Pin # Name Type Description

0 GND GND The DAP pad must be grounded.

1 GND GND

2 VregRFout LDO Output LDO Output for RF output buffer.

3 VccRFout Supply

(LDO Input) Supply for the RF output buffer.

4 L1 NC Do not connect this pin.

5 Lmid NC Do not connect this pin.

6 L2 NC Do not connect this pin.

7 VccVCO Supply

(LDO Input) Supply for the VCO.

8 VregVCO LDO Output LDO Output for VCO

9 VrefVCO LDO Bypass LDO Bypass

10 GND GND

11 CE CMOS Chip Enable.

The device needs to be programmed for this pin to properly power down the device.

12 ExtVCOin RF Input Optional input for use with an external VCO.

This pin should be AC coupled if used or left open if not used.

13 VccPLL1 Supply Power supply for PLL.

14 VccCP1 Supply Power supply for PLL charge pump.

15 Vtune High-Z Input Tuning voltage input to the VCO.

16 CPout Output Charge pump output.

17 FLout Output Fastlock output.

18 VccCP2 Supply Power supply for PLL charge pump.

19 VccPLL2 Supply Power supply for PLL.

20 Ftest/LD Output Software controllable multiplexed CMOS output.

Can be used to monitor PLL lock condition.

21 OSCin High-Z Input Oscillator input signal. If not being used with an external crystal, this input should be AC

coupled.

22 OSCin* High-Z Input Complementary oscillator input signal. Can also be used with an external crystal. If not

being used with an external crystal, this input should be AC coupled.

23 VccOSCin Supply Supply for the OSCin buffer.

24 RFoutEN Input Software programmable output enable pin.

25 VccFRAC Supply

(LDO Input) Power Supply for the PLL fractional circuitry.

26 VregFRAC LDO Output Regulated power supply used for the fractional delta-sigma circuitry.

27 GND GND

28 VccDig Supply Supply for digital circuitry, such the MICROWIRE.

29 VccBias Supply Supply for Bias circuitry that is for the whole chip.

30 Bypass Bypass Put a cap to the VccBias pin.

31 VccDiv Supply Supply for the output divider

32 DATA High-Z Input MICROWIRE serial data input. High impedance CMOS input.

33 CLK High-Z Input MICROWIRE clock input. High impedance CMOS input.

This pin is used for the digital FSK modulation feature.

34 LE High-Z Input MICROWIRE Latch Enable input. High impedance CMOS input.

35 NC NC No connect.

36 RFout RF Output RF output. Must be AC coupled if used.

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LMX2541

Absolute Maximum Ratings (Note 1, Note 2, Note 3)

If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors

for availability and specifications.

Parameter Symbol Ratings Units

Power Supply Voltage Vcc -0.3 to 3.6 V

Input Voltage to pins other than Vcc Pins

(Note 4)VIN -0.3 to (Vcc+0.3) VIN

Storage Temperature

Range TSTG -65 to 150 °C

Lead Temperature (solder 4 sec.) TL+ 260 °C

Recommended Operating Conditions

Parameter Symbol Min Typ Max Units

Power Supply Voltage

(All Vcc Pins) Vcc 3.15 3.3 3.45 V

Ambient Temperature TA-40 +85 °C

Note 1: “Absolute Maximum Ratings” indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device

is intended to be functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics.

The guaranteed specifications apply only to for the test conditions listed.

Note 2: This device is has a ESD rating of ≥ 2500 V Human Body Model (HBM), ≥ 1750 V Charged Device Model (CDM), and ≥400 V Machine Model (MM).

It should only be assembled and handled in ESD-free workstations.

Note 3: Stresses in excess of the absolute maximum ratings can cause permanent or latent damage to the device. These are absolute stress ratings only.

Functional operation of the device is only implied at these or any other conditions in excess of those given in the

Note 4: Never to exceed 3.6 V.

Package Thermal Resistance

Package θJA θJC

9 Thermal Vias

(Recommended for Most Reliable Solderability) 31.7 °C/W 7.3 °C/W

13 Thermal Vias

(Compromise Between Solderability, Heat Dissipation, and

Fractional Spurs)

30.3 °C/W 7.3 °C/W

16 Thermal Vias

(Recommended for Optimal Heat Dissipation and Fractional

Spurs)

29.8 °C/W 7.3 °C/W

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LMX2541

Electrical Characteristics (3.15 V ≤ VCC ≤ 3.45 V, -40°C ≤ TA ≤ 85 °C; except as specified. Typical values are

at Vcc = 3.3 V, 25 C.)

Symbol Parameter Conditions Min Typ Max Units

Current Consumption

ICC

Entire Chip Supply Current with

all blocks enabled

Default Power

Mode

(Note 5)

VCO_DIV>1 170 204

VCO_DIV=1 130 156

IPLL Current for External VCO Mode RFoutEN = LOW 72 94 mA

IDIV Current for Divider Only Mode

VCO_DIV >1

Default Power Mode

(Note 5)

84 110 mA

ICCPD Power Down Current CE = 0 V, Device Initialized 100 250 µA

Oscillator (Normal Mode Operation with XO=0)

IIHOSC

Oscillator Input High Current for

OSCin and OSCin* VIH = 2.75 V 300 µA

IILOSCin Oscillator Input Low Current for

OSCin and OSCin* pins VIL = 0 -100 µA

fOSCin

OSCin Frequency Range

(Note 7)

OSC_2X = 1 5 52

MHz

OSC_2X = 0 MODE = 0 5 700

MODE = 1 5 900

dvOSCin Slew Rate (Note 7) 150 V/µs

vOSCin Oscillator Sensitivity dvOSCin ≥ 150 V/µs Single-Ended 0.2 2.0 Vpp

Differential 0.4 3.1

Oscillator (Crystal Mode with XO=1)

fXTAL Crystal Frequency Range VIH = 2.75 V 5 20 MHz

ESRXTAL

Crystal Equivalent Series

Resistance

This a requirement for the crystal,

not a characteristic of the LMX2541. 100 Ω

PXTAL Power Dissipation in Crystal This requirement is for the crystal,

not a characteristic of the LMX2541. 200 µW

COSCin Input Capacitance of OSCin 6 pF

PLL

fPD Phase Detector Frequency 104 MHz

ICPout

Charge Pump

Output Current Magnitude

CPG = 1X

100

µA

CPG = 2X 200

CPG = 3X 300

... ...

CPG=32X 3200

ICPoutTRI CP TRI-STATE Current 0.4 V < VCPout < Vcc - 0.4 1 5 nA

ICPoutMM Charge Pump

Sink vs. Source Mismatch

VCPout = Vcc / 2

TA = 25°C 3 10 %

ICPoutV

Charge Pump

Current vs. CP Voltage

Variation

0.4 V < VCPout < Vcc - 0.4

TA = 25°C 4 %

ICPoutTCP Current vs. Temperature

Variation VCPout = Vcc / 2 8 %

LN(f)

(Note 8)

Normalized PLL 1/f Noise

LNPLL_flicker(10 kHz)

CPG = 1X -116 dBc/Hz

CPG = 32X -124.5

Normalized PLL Noise Floor

LNPLL_flat(1 Hz)

CPG = 1X -220.8 dBc/Hz

CPG = 32X -225.4

fExtVCOin PLL Input Frequency RFout Buffer Enabled and VCO_DIV > 1 400 4000 MHz

RFout Buffer Disabled and VCO_DIV = 1 400 6000

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LMX2541

Symbol Parameter Conditions Min Typ Max Units

pExtVCOin

PLL Input Sensitivity

((Note 7) applies to Max Limit

Only)

fExtVCOin ≤ 4 GHz -15 10

dBm

fExtVCOin > 4 GHz -5 10

VCO Specifications

fVCO Internal VCO Frequency Range

Mode = Full Chip Mode

This is the frequency before the

VCO divider.

2060E 1990 2240

MHz

2380E 2200 2530

2690E 2490 2865

3030E 2810 3230

3320E 3130 3600

3740E 3480 4000

ΔTCL

Maximum Allowable

Temperature Drift for

Continuous Lock

(Note 7),(Note 9) 125 °C

pRFout

RF Output Power

(Note 6)

Maximum Frequency

Default Power Mode

VCO_DIV=1

2060E 3.5

dBm

2380E 2.8

2690E 1.6

3030E 1.2

3320E 0.2

3740E - 0.3

ΔPRFout Change in Output Power

Fixed Temperature with 100 MHz frequency change at

the output 0.3

Fixed frequency with a change over the entire

temperature range 0.4

KVtune Fine Tuning Sensitivity

The lower number in the range

applies when the VCO is at its

lowest frequency and the higher

number applies when the VCO is

at its highest frequency. A linear

approximation can be used for

frequencies between these two

cases.

2060E 13 - 23

MHz/V

2380E 16 - 30

2690E 17 - 32

3030E 20 - 37

3320E 21 - 37

3740E 24 - 42

HSRFout

Second Harmonic

(Note 12)

Default Power Mode

(Note 5)

50 Ω Load

VCO_DIV = 2 -20

dBc

VCO_DIV = 3 -20

DERFout

Duty Cycle Error

(Note 12)

Default Power Mode

(Note 5)

50 Ω Load

VCO_DIV = 2 3

VCO_DIV = 3 3

PSHVCO VCO Frequency Pushing CVregVCO = 4.7 µF, Open Loop 600 kHz/V

PULVCO VCO Frequency Pulling VSWR 1.7 to 1

(6 dB Pad)

VCO_DIV = 1 ±800 kHz

VCO_DIV > 1 ±60

σΦRMS Phase Error

Integration Bandwidth

= 100 Hz to 20 MHz

Middle VCO Frequency

100 MHz Wenzel Crystal

Reference

Integer Mode

Optimized Loop Bandwidth

2060E 1.6

mRad

2380E 1.8

2690E 2.1

3030E 2.1

3320E 2.3

3740E 2.6

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LMX2541

Symbol Parameter Conditions Min Typ Max Units

VCO Phase Noise (Note 10)

L(f)Fout

Phase Noise

2060E

fRFout =

Min VCO

Frequency

10 kHz Offset

-89.7

dBc/Hz

100 kHz Offset -113.7

1 MHz Offset -134.9

10 MHz Offset -155.4

20 MHz Offset -160.3

fRFout =

Max VCO

Frequency

10 kHz Offset

-86.5

100 kHz Offset -111.4

1 MHz Offset -132.8

10 MHz Offset -153.4

20 MHz Offset -158.5

L(f)Fout

Phase Noise

2380E

fRFout =

Min VCO

Frequency

10 kHz Offset

-87.9

dBc/Hz

100 kHz Offset -112.7

1 MHz Offset -133.8

10 MHz Offset -154.2

20 MHz Offset -159.5

fRFout =

Max VCO

Frequency

10 kHz Offset

-83.4

100 kHz Offset -109.1

1 MHz Offset -130.8

10 MHz Offset -151.8

20 MHz Offset -157.5

L(f)Fout

Phase Noise

2690E

fRFout =

Min VCO

Frequency

10 kHz Offset

-86.9

dBc/Hz

100 kHz Offset -111.8

1 MHz Offset -133.3

10 MHz Offset -154.2

20 MHz Offset -159.4

fRFout =

Max VCO

Frequency

10 kHz Offset

-82.3

100 kHz Offset -108.4

1 MHz Offset -130.3

10 MHz Offset -151.1

20 MHz Offset -156.7

L(f)Fout

Phase Noise

3030E

fRFout =

Min VCO

Frequency

10 kHz Offset

-86.1

dBc/Hz

100 kHz Offset -110.5

1 MHz Offset -132.0

10 MHz Offset -152.2

20 MHz Offset -157.1

fRFout =

Max VCO

Frequency

10 kHz Offset

-82.2

100 kHz Offset -107.7

1 MHz Offset -129.4

10 MHz Offset -150.5

20 MHz Offset -156.1

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LMX2541

Symbol Parameter Conditions Min Typ Max Units

L(f)Fout

Phase Noise

3320E

fRFout =

Min VCO

Frequency

10 kHz Offset

-84.1

dBc/Hz

100 kHz Offset -109.1

1 MHz Offset -130.7

10 MHz Offset -151.6

20 MHz Offset -156.9

fRFout =

Max VCO

Frequency

10 kHz Offset

-82.0

100 kHz Offset -107.0

1 MHz Offset -128.5

10 MHz Offset -149.6

20 MHz Offset -155.2

L(f)Fout

Phase Noise

3740E

fRFout =

Min VCO

Frequency

10 kHz Offset

-83.9

dBc/Hz

100 kHz Offset -108.3

1 MHz Offset -129.9

10 MHz offset -150.6

20 MHz Offset -156.5

fRFout =

Max VCO

Frequency

10 kHz Offset

-81.6

100 kHz Offset -106.5

1 MHz Offset -127.7

10 MHz Offset -148.6

20 MHz Offset -154.2

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LMX2541

Symbol Parameter Conditions Min Typ Max Units

Digital Interface (DATA, CLK, LE, CE, Ftest/LD, FLout,RFoutEN)

VIH High-Level Input Voltage 1.6 Vcc V

VIL Low-Level Input Voltage 0.4 V

IIH High-Level Input Current VIH = 1.75, XO = 0 -5 5 µA

IIL Low-Level Input Current VIL = 0 V , XO = 0 -5 5 µA

VOH High-Level Output Voltage IOH = 500 µA 2.0 V

VOL Low-Level Output Voltage IOL = -500 µA 0.0 0.4 V

ILeak Leakage Current Ftest/LD and FLout Pins Only -5 5 µA

MICROWIRE Timing

tCE Clock to Enable Low Time See Data Input Timing 25 ns

tCS Data to Clock Set Up Time See Data Input Timing 25 ns

tCH Data to Clock Hold Time See Data Input Timing 20 ns

tCWH Clock Pulse Width High See Data Input Timing 25 ns

tCWL Clock Pulse Width Low See Data Input Timing 25 ns

tCES Enable to Clock Set Up Time See Data Input Timing 25 ns

tEWH Enable Pulse Width High See Data Input Timing 25 ns

Note 5: The LMX2541 RFout power level is programmable with the program words of VCOGAIN, OUTTERM, and DIVGAIN. Changing these words can change

the output power of the VCO as well as the current consumption of the output buffer. For the purpose of consistency in electrical specifications, "Default Power

Mode" is defined to be the settings of VCOGAIN = OUTTERM = DIVGAIN = 12.

Note 6: The measurement of the output power is sensitive to the test circuit. All the numbers in the electrical specifications and typical performance curves were

obtained from a characterization setup that accomodated temperature testing and changing of parts. In a more optimized setup the measured RF output power

is typically on the order of 1.5 to 2.4 dB higher.

Note 7: Not tested in production. Guaranteed by characterization. OSCin is tested only to 400 MHz.

Note 8: Consult the applications section for more details on these parameters.

Note 9: Maximum Allowable Temperature Drift for Continuous Lock is how far the temperature can drift in either direction from the value it was at the time that

the R0 register was last programmed, and still have the device stay in lock. The action of programming the R0 register, even to the same value, activates a

frequency calibration routine. This implies that the device will work over the entire frequency range, but if the temperature drifts more than the maximum allowable

drift for continuous lock, then it will be necessary to reload the R0 register to ensure that it stays in lock. Regardless of what temperature the device was initially

programmed at, the temperature can never drift outside the frequency range of -40°C ≤TA≤ 85°C without violating specifications.

Note 10: The VCO phase noise is measured assuming that the loop bandwidth is sufficiently narrow that the VCO noise dominates. The phase noise is measured

with AC_TEMP_COMP = 5 and the device is reloaded at each test frequency. The typical performance characteristics section shows how the VCO phase noise

varies over temperature and frequency.

Note 11: See Typical Performance Characteristics for more information.

Note 12: The duty cycle error (DE) and second harmonic (HS) are theoretically related by the equation HS = 10·log| 2π·DE | - 6 dB. A square wave with 3% duty

cycle theoretically has a second harmonic of -20 dBc.

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LMX2541

Serial Data Timing Diagram

30073303

There are several other considerations for programming:

•The DATA is clocked into a shift register on each rising edge of the CLK signal. On the rising edge of the LE signal, the data is

sent from the shift registers to an actual counter.

•A slew rate of at least 30 V/μs is recommended for the CLK, DATA, and LE signals.

•After the programming is complete, the CLK, DATA, and LE signals should be returned to a low state.

•When using the part in Full Chip Mode with the Integrated VCO, LE should be kept high no more than 1 us after the programming

of the R0 register. Failure to do so may interfere with the digital VCO calibration.

•If the CLK and DATA lines are toggled while the in VCO is in lock , as is sometimes the case when these lines are shared with

other parts, the phase noise may be degraded during the time of this programming.

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LMX2541

Typical Performance Characteristics (Not Guaranteed)

LMX2541SQ3740E Raw Phase Noise Measurement

30073307

The above plot demonstrates the PLL phase noise of the LMX2541SQ3700E operating at 3700 MHz output frequency, phase detector frequency of 100 MHz,

and charge pump gain of 32X. The loop bandwidth was made as wide as possible to fully expose the PLL phase noise and reference source was a 100 MHz

Wenzel crystal. This measurement was done in integer mode. To better understand the impact of using fractional mode, consult the applications section.

The measured noise is the sum of the PLL 1/f noise and noise floor. At offsets below 1 kHz, the PLL 1/f noise dominates and changes at a rate of 10 dB/decade.

The noise at 1 kHz is dominated by this 1/f noise and has a value of -103 dBc/Hz. In the 100 - 200 kHz offset range, the noise is -113.7 dBc/Hz and is dominated

by the PLL noise floor. It can be shown that if the effects of the loop filter peaking and the 1/f noise are subtracted away from this measurement, it would be about

0.6 dB better.

If the phase detector frequency is changed with the VCO frequency held constant, the PLL noise floor will change, but the 1/f noise will remain the same. If the

VCO frequency is changed, both the 1/f noise and PLL noise floor change at a rate of 20 dB/decade.

LMX2541SQ2690 System Phase Noise

30073327

For this plot, a third order modulator with dithering disabled was used with a fractional denominator of 500000. The charge pump gain was 32X and the loop filter

components were C1 = 2.2 nF, C2 = 22 nF, R2 = 470 Ω. The internal loop filter components were C3_LF = 20 pF, C4_LF = 100 pF, R3_LF = 1 kΩ, R4_LF = 200

Ω. The VCO frequency is 2720.1 MHz. The OSCin signal was a 500 MHz differential LVPECL output of the LMK04033.

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LMX2541

LMX2541SQ3320E System Phase Noise

30073328

For this plot, a third order modulator with dithering disabled was used with a fractional denominator of 500000. The charge pump gain was 32X and the loop filter

components were C1 = 2.2 nF, C2 = 22 nF, R2 = 470 Ω. The internal loop filter components were C3_LF = 20 pF, C4_LF = 100 pF, R3_LF = 1 kΩ, R4_LF = 200

Ω. The VCO frequency is 3320.1 MHz. The OSCin signal was a 500 MHz differential LVPECL output of the LMK04033.

LMX2541SQ3740E System Phase Noise

30073329

For this plot, a third order modulator with dithering disabled was used with a fractional denominator of 500000. The charge pump gain was 32X and the loop filter

components were C1 = 2.2 nF, C2 = 22 nF, R2 = 470 Ω. The internal loop filter components were C3_LF = 20 pF, C4_LF = 100 pF, R3_LF = 1 kΩ, R4_LF = 200

Ω. The VCO frequency is 3840.2 MHz, but the VCO Divider is set to two, so the RFout frequency is 1720.1 MHz. The OSCin signal was a 500 MHz differential

LVPECL output of the LMK04033.

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LMX2541

Divider Noise Floor vs. Divider Value

(fVCO = 3700 MHz, Various values for VCO_DIV)

30073326

When the divider is engaged (VCO_DIV >0), then the entire system phase noise is reduced by a factor of 20 × log(VCO_DIV). However, the noise floor of the

divider will also add to this noise as is visible at far offsets. Note that the noise floor for Bypass mode is lower because the VCO divider is not engaged.

Divider Noise Floor vs. Frequency

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Provided the VCO divider is not bypassed, the actual value of it does not impact the divider noise floor; it is the frequency at the RFout pin that impacts the divider

noise floor. The above plot shows how this noise floor changes as a function of the frequency of the RFout pin.

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LMX2541

PLL Normalized Noise Floor vs. OSCin Slew Rate

(KPD = 32X)

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PLL Normalized Noise Floor vs. Charge Pump Gain

(Slew Rate = 2000 V/μs)

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PLL Normalized 1/f Noise vs. OSCin Slew Rate

(KPD = 32X)

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PLL Normalized 1/f Noise vs. Charge Pump Gain

(Slew Rate = 2000 V/μs)

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LMX2541

VCO Phase Noise Degradation vs. Temperature and Offset

(VCO Relocked at Each Temperature

Vcc = 3.3 V, AC_TEMP_COMP = 5)

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The above plot shows how much the VCO phase noise typically change over temperature relative to room temperature. The typical values for represent an

average over all frequencies and part options and therefore there are some small variations over part options and frequencies that are not shown .VCO phase

noise numbers room temperature are reported in the electrical specifications. A negative value indicates a phase noise improvement.

Relative VCO Phase Noise Over Temperature Drift

(AC_TEMP_COMP = 24, Vcc = 3.3 V)

Temperature Phase Noise Change in Celsius for Various Offsets

Lock Current 10 kHz 100 kHz 1 MHz 10 MHz 20 MHz

-40 -40 +0.4 -2.0 -1.6 -1.8 -1.6

-40 25 +0.3 +0.5 +0.5 +0.5 +0.4

-40 85 +0.9 +2.0 +2.4 +2.5 +2.3

25 -40 +0.2 -2.2 -1.7 -2.0 -1.8

25 25 This is the default condition to which these other numbers are normalized to.

25 85 +0.6 +1.5 +2.0 +2.0 +1.9

85 -40 +0.2 -2.2 -1.7 -1.9 -1.8

85 25 +0.2 +0.2 +0.3 +0.2 +0.2

85 85 +0.6 +1.8 +2.2 +2.3 +2.1

The above table shows the typical degradation for VCO phase noise when the VCO is locked at one temperature and the tem-

perature is allowed to drift to another temperature. A negative value indicates a phase noise improvement.

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LMX2541