IDT5V996 3.3V PROGRAMMABLE SKEW PLL CLOCK DRIVER TURBOCLOCK II PLUS INDUSTRIAL TEMPERATURE RANGE IDT5V996 3.3V PROGRAMMABLE SKEW PLL CLOCK DRIVER TURBOCLOCKTM II PLUS FEATURES: DESCRIPTION: * * * * The IDT5V996 is a high fanout PLL based clock driver intended for high performance computing and data-communication applications. The IDT5V996 has eight programmable skew outputs organized in four banks of two. Skew is controlled by 3-level input signals that may be hard wired to appropriate HIGH-MID-LOW levels. The IDT5V996 provides up to 18 programmable levels of output skew, prescaling, and other features. Other features of IDT5V996 are synchronous output enable (G), TEST, and lock detect indicator (LOCK). When G is held low, all the outputs are synchronously enabled, however, if G is held high, all outputs except 3Q0 and 3Q1 are in the state designated by SE (HIGH or LOW). When TEST is held low, the chip operates in normal condition. When held high, the PLL is shut off and the chip functions as a buffer. The lock detect indicator asserts high when the phase lock loop has acquired lock. During acquisition, the indicator is in the low state. Once the PLL has reached the steady-state condition within a specified frequency range, LOCK is asserted high. The PLL is closed externally to provide more flexibility by allowing the user to control the delay between the input clock and the outputs. The IDT5V996 has LVTTL outputs with 12mA balanced drive outputs. The IDT5V996 is characterized for operation from -40C to +85C. 3.3V operation 4 pairs of programmable skew outputs Low skew: 150ps same pair, 350ps all outputs Selectable positive or negative edge synchronization: Excellent for DSP applications Synchronous output enable Input frequency: 25MHz to 225MHz Output frequency: 25MHz to 225MHz 2x, 4x, 1/2, and 1/4 outputs (of VCO frequency) 3-level inputs for skew control PLL bypass for DC testing External feedback, internal loop filter 12mA balanced drive outputs Low Jitter: <150ps peak-to-peak Available in 144-pin BGA package * * * * * * * * * * FUNCTIONAL BLOCK DIAGRAM G Enable Logic SE 1Q0 Skew Select 3 3 1Q 1 3 1F2:0 TEST 2Q0 Skew Select 3 3 2Q1 3 REF 2F2:0 PLL FB 3Q 0 Skew Select 3 3 3Q1 3 3F2:0 LOCK 4Q0 Skew Select 3 3 4Q 1 3 4F2:0 The IDT logo is a registered trademark of Integrated Device Technology, Inc. INDUSTRIAL TEMPERATURE RANGE NOVEMBER 2004 1 c 2004 Integrated Device Technology, Inc. DSC 5855/6 IDT5V996 3.3V PROGRAMMABLE SKEW PLL CLOCK DRIVER TURBOCLOCK II PLUS INDUSTRIAL TEMPERATURE RANGE PIN CONFIGURATION 1 2 3 4 5 6 7 8 9 10 11 12 A V DDQ V DDQ V DDQ GND GND LOCK GND GND GND V DDQ V DDQ V DDQ A B V DDQ V DDQ V DDQ GND 2Q1 2Q0 1Q1 1Q0 GND V DDQ V DDQ V DDQ B C V DDQ V DDQ V DD V DD V DD V DD V DD V DD V DD V DD V DDQ V DDQ C D V DDQ V DDQ V DD GND GND GND GND GND GND V DD 2F2 2F1 D E V DDQ G V DD GND GND GND GND GND GND V DD 2F0 1F2 E F TEST REF V DD GND GND GND GND GND GND V DD 1F1 1F0 F G V DDQ FB V DD GND GND GND GND GND GND V DD 4F1 4F0 G H V DDQ SE V DD GND GND GND GND GND GND V DD 3F0 4F2 H J V DDQ V DDQ V DD GND GND GND GND GND GND V DD 3F2 3F1 J K V DDQ V DDQ V DD V DD V DD V DD V DD V DD V DD V DD V DDQ V DDQ K L V DDQ V DDQ V DDQ GND 3Q1 3Q0 4Q1 4Q0 GND V DDQ V DDQ V DDQ L M V DDQ V DDQ V DDQ GND GND GND GND GND GND V DDQ V DDQ V DDQ M 1 2 3 4 5 6 7 8 9 10 11 12 BGA TOP VIEW 2 IDT5V996 3.3V PROGRAMMABLE SKEW PLL CLOCK DRIVER TURBOCLOCK II PLUS ABSOLUTE MAXIMUM RATINGS(1) VDDQ, VDD VI (2) (2) VO CAPACITANCE(1,2)(TA = +25C, f = 1MHz, VIN = 0V) Description Max Unit Parameter Supply Voltage Range -0.5 to +4.6 V CIN Input Voltage Range -0.5 to 4.6 V Voltage range applied to any -0.5 to V output in the high or low state VDDQ + 0.5 Symbol -50 INDUSTRIAL TEMPERATURE RANGE IIK (VI < 0) Input Clamp Current IO (VO = 0 to VDDQ) Continuous Output Current 50 mA VDDQ or GND Continuous Current 100 mA TSTG Storage Temperature Range -65 to +150 C Description Min Typ. Max. Unit Input Capacitance -- 8 -- pF VI = VDDQ or GND NOTES: 1. Unused inputs must be held high or low to prevent them from floating. 2. Capacitance applies to all inputs except nF2:0. This value is characterized but not production tested. mA NOTES: 1. Stresses beyond those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolutemaximum-rated conditions for extended periods may affect device reliability. 2. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed. PIN DESCRIPTION Pin Name Type Description REF IN Reference Clock Input SE IN Selectable positive or negative edge control. When LOW / HIGH, the outputs are synchronized with the negative/positive edge of the reference clock. When outputs are synchronously stopped with the G pin, SE determines the level at which outputs stop. When SE is LOW/HIGH, outputs synchronously stop HIGH/LOW. FB IN Feedback Input G IN Output gate for "true" nQ[1:0] outputs. When G is LOW, the "true" nQ[1:0] outputs are enabled. When G is HIGH, the "true" nQ[1:0] outputs are in the state designated by SE (HIGH or LOW) (except 3Q0 and 3Q1) - 3Q0 and 3Q1 may be used as the feedback signal to maintain phase lock. TEST IN TEST = LOW means normal operation. TEST = HIGH means that the PLL is powered down and REF is routed to all the outputs. The skews selected with the nF[2:0] pins are still in effect. (The TEST pin is a TTL input.) nF[2:0] IN 3-level inputs for selecting 1 of 18 skew taps or frequency functions nQ[1:0] OUT Clock Output Pairs VDDQ PWR Power supply for output buffers VDD PWR Power supply for phase locked loop and other internal circuitry GND PWR Ground LOCK OUT Lock Detect. Asserted (HIGH) when the PLL is locked. The REF input must be oscillating. (For more information on application specific use of the LOCK pin, please see AN237.) PROGRAMMABLE SKEW Output skew with respect to the REF input is adjustable to compensate for PCB trace delays, backplane propagation delays or to accommodate requirements for special timing relationships between clocked components. Skew is selectable as a multiple of a time unit (tU) which ranges from 278ps to 625ps (see Programmable Skew Range and Resolution Table). There are 16 skew configurations available for each output pair. These configurations are chosen by the nF2:0 control pins. In order to minimize the number of control pins, 3-level inputs (HIGH-MID-LOW) are used, they are intended for but not restricted to hard-wiring. Undriven 3-level inputs default to the MID level. Where programmable skew is not a requirement, the control pins can be left open for the zero skew default setting. The Control Summary Table shows how to select specific skew taps by using the nF2:0 control pins. 3 IDT5V996 3.3V PROGRAMMABLE SKEW PLL CLOCK DRIVER TURBOCLOCK II PLUS INDUSTRIAL TEMPERATURE RANGE EXTERNAL FEEDBACK By providing external feedback, the IDT5V996 gives users flexibility with regard to skew adjustment. The FB signal is compared with the input REF signal at the phase detector in order to drive the VCO. Phase differences cause the VCO of the PLL to adjust upwards or downwards accordingly. An internal loop filter moderates the response of the VCO to the phase detector. The loop filter transfer function has been chosen to provide minimal jitter (or frequency variation) while still providing accurate responses to input frequency changes. PLL PROGRAMMABLE SKEW RANGE AND RESOLUTION TABLE Comments Timing Unit Calculation (tU) 1/(16 x FNOM) VCO Frequency Range (FNOM)(1) 100 to 225 MHz Skew Adjustment Range(2) Max Adjustment: 4.375ns ns 157.5 Phase Degrees 43.75% % of Cycle Time Example 1, FNOM = 100MHz tU = 0.625ns -- Example 2, FNOM = 167MHz tU = 0.374ns -- Example 3, FNOM = 225MHz tU = 0.278ns -- NOTES: 1. The VCO frequency always appears at nQ1:0 outputs when they are operated in their undivided modes. The frequency appearing at the REF and FB inputs will be FNOM when the output connected to FB is undivided. The frequency of the REF and FB inputs will be FNOM /2 or FNOM /4 when the part is configured for frequency multiplication by using a divided output as the FB input. Using the nF[2:0] inputs allows a different method for frequency multiplication (see Control Summary Table for Feedback Signals). 2. Skew adjustment range assumes that a zero skew output is used for feedback. If a skewed Q output is used for feedback, then adjustment range will be greater. For example if a 4tU skewed output is used for feedback, all other outputs will be skewed -4tU in addition to whatever skew value is programmed for those outputs. `Max adjustment' range applies to all output pairs where 7tU skew adjustment is possible and at the lowest FNOM value. CONTROL SUMMARY TABLE FOR FEEDBACK SIGNALS(1) nF2 nF1 nF0 Output Skew L L L Disable(2) L H L -7tU L H M -6tU L H H -5tU M L L -4tU M L M -3tU M L H -2tU M M L -1tU M M M Zero Skew M M H +1tU M H L +2tU M H M +3tU M H H +4tU H L L +5tU H L M +6tU H L H +7tU H M L Inverted H M M Divide by 2 H M H Divide by 4 NOTES: 1. All unused/unnoted combinations are reserved. 2. When G is LOW, all output pairs are individually disabled to the level designated by SE. When SE is LOW/HIGH, output pairs disable HIGH/LOW. 4 IDT5V996 3.3V PROGRAMMABLE SKEW PLL CLOCK DRIVER TURBOCLOCK II PLUS INDUSTRIAL TEMPERATURE RANGE RECOMMENDED OPERATING RANGE Symbol VDD / VDDQ TA Description Power Supply Voltage Ambient Operating Temperature Min. Typ. Max. Unit 3 3.3 3.6 V -40 +25 +85 C DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE Symbol Conditions Min. Max. Unit VIH Input HIGH Voltage Guaranteed Logic HIGH (REF, FB Inputs Only) 2 -- V VIL Input LOW Voltage Guaranteed Logic LOW (REF, FB Inputs Only) -- 0.8 V VIHH Input HIGH Voltage Level(1) 3-Level Inputs Only VDD-0.6 -- V V VIMM Parameter (1) Input MID Voltage Level VILL Input LOW Voltage Level IIN Input Leakage Current (1) (REF, FB Inputs Only) 3-Level Inputs Only VDD/2-0.3 VDD/2+0.3 3-Level Inputs Only -- 0.6 V VIN = VCC or GND -5 +5 A VCC = Max. VIN = VDD HIGH Level -- +200 3-Level Input DC Current (nF2:0) VIN = VDD/2 MID Level -50 +50 VIN = GND LOW Level -200 -- VOH Output HIGH Voltage Level VDD = Min., IOH = -12mA 2.4 -- V VOL Output LOW Voltage Level VDD = Min., IOL = 12mA -- 0.4 V I3 A NOTE: 1. These inputs are normally wired to VDDQ, GND, or unconnected. Internal termination resistors bias unconnected inputs to VDDQ/2. If these inputs are switched, the function and timing of the outputs may be glitched, and the PLL may require an additional tLOCK time before all datasheet limits are achieved. POWER SUPPLY CHARACTERISTICS Symbol Parameter IDDQ Quiescent Power Supply Current Test Conditions(1) VDDQ = Max., REF = FB = SE = G = LOW, TEST = HIGH, All nF2:0 = Typ.(2) Max. Unit -- 30 mA A/MHz HHM(3), All outputs floating IDDD ITOT Dynamic Power Supply Current per Output Total Power Supply Current VDDQ = Max., CL = 0pF 410 650 VDDQ = 3.3V, FVCO = 100MHz, CL = 20pF 124 -- VDDQ = 3.3V, FVCO = 167MHz, CL = 20pF 197 -- VDDQ = 3.3V, FVCO = 225MHz, CL = 20pF 253 -- NOTES: 1. Measurements are for divide-by-1 outputs. 2. For nominal voltage and temperature. 3. This configuration is only specific for IDDQ measurements. 5 mA IDT5V996 3.3V PROGRAMMABLE SKEW PLL CLOCK DRIVER TURBOCLOCK II PLUS INDUSTRIAL TEMPERATURE RANGE SWITCHING CHARACTERISTICS OVER OPERATING RANGE(1) Symbol Parameter Min. Typ. Max. Unit FNOM VCO Frequency Range FREF REF Clock Input Frequency 25 -- 225 MHz tREF REF Clock Duty Cycle 10 -- 90 % tU tSKEWPR See PLL Programmable Skew Range and Resolution Table Programmable Skew Time Unit See Control Summary Table Matched-Pair Skew (xQ0, xQ1)(1,2,3) (1,2) -- -- 150 tSK(0) Output Skew (Rise-Rise, Fall-Fall, Same Frequency and Phase) -- -- 350 tSK() Multiple Frequency Skew(1,2) -- -- 550 -- -- 500 tSK(INV) Inverting Skew Between Nominal and Inverted (1,2,4) (1,2) tSKEW1 Output Skew (Rise-Fall, Inverted-Divided) -- -- 500 tSKEW4 Output Skew (Rise-Fall, Divided-Divided)(1,2,4) -- -- 500 tDEV t tODCV Device-to-Device Skew(2,5) ps -- -- 250 REF Input to FB Static Phase Offset (VTH = VDDQ/2) -250 -- +250 Output Duty Cycle Variation from 50%(1,7) -0.75 -- +0.75 ns (1) tR Output Rise Time (0.8V to 2V) -- -- 2.2 ns tF Output Fall Time (2V to 0.8V)(1) -- -- 2.2 ns tLOCK (6) PLL Lock Time -- -- 0.5 ms Cycle-to-Cycle Output Jitter, Peak-to-Peak(1) -- -- 150 ps tJ NOTES: 1. Measured at VTH = VDDQ/2, output load CL = 20pF. 2. Skew is the time between the earliest and the latest output transition among all outputs for which the same tU delay has been selected when all are loaded with the specified load. 3. tSKEWPR is the skew between a pair of outputs (xQ0 and xQ1) when all eight outputs are selected for 0tU. 4. There are 3 classes of outputs: Nominal (multiple of tU delay), Inverted, and Divided (Divide-by-2 or Divide-by-4 mode). 5. tDEV is the output-to-output skew between any two devices operating under the same conditions (VDD and VDDQ, ambient temperature, air flow, etc.) 6. tLOCK is the time that is required before synchronization is achieved. This specification is valid only after VDD and VDDQ are stable and within normal operating limits. This parameter is measured from the application of a new signal or frequency at REF or FB until tPD is within specified limits. 7. tODCV is measured with nF[2:0] = MMM. 6 IDT5V996 3.3V PROGRAMMABLE SKEW PLL CLOCK DRIVER TURBOCLOCK II PLUS INDUSTRIAL TEMPERATURE RANGE AC TEST LOADS AND WAVEFORMS 150 OUTPUT 150 20pF AC Load 3V V TH =V DDQ /2 0V Input Waveform tR tF 2 V TH 0.8 Output Waveform 150 nQn REF C L = 20pF IDT5V996 FB 3Q 0 F BOUT CF PCB TR ACE Static Phase Offset and Skew Calculations (2,3) NOTES: 1. VTH = VDDQ/2. 2. CF = CL - CFBIN - CPCBTRACE; CFBIN 6pF 3. Calculations were done by adjusting the input slew rate to match with the output slew rate. 7 150 IDT5V996 3.3V PROGRAMMABLE SKEW PLL CLOCK DRIVER TURBOCLOCK II PLUS INDUSTRIAL TEMPERATURE RANGE AC TIMING DIAGRAM t R PW L t R EF t RP W H RE F t ( ) t O DC V t O DC V FB tJ Q t S KE W P R t S K(O ) t S KE W P R t SK(O) OTH ER Q tSK (INV) tSK(INV) INV ER TE D Q tS K( ) tSK( ) tSK( ) REF D IVIDE D B Y 2 tSKE W 1,4 tSKE W 1,4 REF D IVIDE D B Y 4 NOTES: SE: The AC Timing Diagram applies to SE=VDD. For SE=GND, the negative edge of FB aligns with the negative edge of REF, divided outputs change on the negative edge of REF, and the positive edges of the divide-by-2 and the divide-by-4 signals align. Skew: The time between the earliest and the latest output transition among all outputs for which the same tU delay has been selected when all are loaded with 20pF and terminated with 75 to VDDQ/2. tSKEWPR: The skew between a pair of outputs (xQ0 and xQ1) when all eight outputs are selected for 0tU. tSK(0): The skew between outputs when they are selected for 0tU. tDEV: The output-to-output skew between any two devices operating under the same conditions (VDDQ, VDD, ambient temperature, air flow, etc.) tODCV: The deviation of the output from a 50% duty cycle. Output pulse width variations are included in tSKEW1 and tSKEW4 specifications. tSK(): The skew between outputs of different frequencies. tSK(INV): The skew between inverting and non-inverting outputs. tR and tF are measured between 0.8V and 2V. tLOCK: The time that is required before synchronization is achieved. This specification is valid only after VDD/VDDQ is stable and within normal operating limits. This parameter is measured from the application of a new signal or frequency at REF or FB until tPD is within specified limits. 8 IDT5V996 3.3V PROGRAMMABLE SKEW PLL CLOCK DRIVER TURBOCLOCK II PLUS INDUSTRIAL TEMPERATURE RANGE ORDERING INFORMATION IDT XX XXXXX Device Type Package X Process CORPORATE HEADQUARTERS 6024 Silver Creek Valley Road San Jose, CA 95138 I -40C to +85C (Industrial) BB Plastic Ball Grid Array 5V996 3.3V Programmable Skew PLL Clock Driver TurboClock II Plus for SALES: 800-345-7015 or 408-284-8200 fax: 408-284-2775 www.idt.com 9 for Tech Support: clockhelp@idt.com