Press release (November 1997):
High-Speed Clock and Data Recovery with
Demultiplexer IC CDR3300
Siemens AG herewith announces that its 2.5 to 3.3 Gb/s Clock and Data Recovery
with Demultiplexer IC (CDR-DEMUX-IC) is now available.
The high-speed CDR-DEMUX-IC receives scrambled NRZ signals, recovers the
clock from the data and demultiplexes these to a customized ratio.
It is dedicated for the use in high-speed communication systems such as fiber-optic
data links.
The CDR-part is realized as a macro on the analog part of Siemens’ commercially
available bipolar Gate Array SH100G.
It utilizes an on-chip PLL which consists of a frequency and a phase detector with bit
error detection and a VCO.
Furthermore, the CDR-part features a level-independent SDH-compatible loss-of-
signal (LOS) detection. It is possible to configurate the hysteresis of LOS switching
function matched to the user requirements
The differential input sensitivity of the CDR is < 20 mVpp at a BER = 10-12.
In connection with a high gain transimpedance amplifier, e. g. Siemens’
TIA2500, that allows the user to realize a two chip high-speed receiver very easily.
To check the performance of such two chip receiver an evaluation board can be
ordered.
Caused by the given flexibility of the Gate Array SH100G, it is possible to combine
the CDR-part with different demultiplexer configurations. Thus, according to
customer needs a 1:2, 1:4, 1:8, or 1:16 demultiplexer is integrated additionally to the
CDR-macro.
After data processing, the recovered parallel data is available to the user at ECL or
LVDS level or via open collector output.
On request the CDR-DEMUX Gate Array is also as 622 Mb/s- or 1.25 Gb/s-version
available.
