APEK4491EES-01-T - Allegro MicroSystems, LLC

Description

Designed to provide the power supply requirements of printers,

office automation, industrial, and portable equipment, the

A4491 provides three high current, high performance, switching

regulator outputs in a single package, saving space, cost and

component count.

High frequency switching allows selection of inexpensive

inductors and small ceramic output capacitors. The turn-on

cycles of the regulators are interleaved to minimize stresses on

the input capacitors and to reduce EMI. Independent Enable

pins simplify power sequencing and shutdown capabilities,

and a power-on-reset (POR) circuit with user configurable

delay indicates when enabled regulators are in specification.

4491-DS, Rev. 1

Features and Benefits

▪ Three buck converters in a single package

▪ 4.5 to 23 V input voltage range

▪ 550 kHz fixed frequency

▪ Multiphase switching for smaller components and

lower EMI

▪ Independent control of each converter for sequencing and

shutdown control

▪ Power-on-reset flag with adjustable delay

▪ Internal compensation to minimize components and

simply design

▪ 4 × 4 mm QFN Package, small PCB footprint

Triple Output Step-Down Switching Regulator

Package: 20-contact QFN (suffix ES)

Applications:

▪ Photo, inkjet, and portable printers

• Set-top boxes

• Tablet computing

• Other Consumer Electronics applications

• Point-of-sale applications

• Security systems

• Gaming machines

• Other Industrial applications

A4491

Approximate size

Microcontroller or

Controller Logic

VBB

GND

CP1 CP2 VCP

PGND

PORZ

ENB1

ENB2

ENB3

CPOR VREG1

VREG2

VREG3

VDD

A4491

VBB2

LX2

FB2

VBB3

LX3

FB3

VBB1

LX1

FB1

Typical Application

Continued on the next page…

Triple Output Step-Down Switching Regulator

A4491

Allegro MicroSystems, LLC

115 Northeast Cutoff

Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

Selection Guide

Part Number Packing Operating Temperature Range

(°C)

A4491EESTR-T 1500 pieces per 7-in. reel –40 to 85

Thermal Characteristics may require derating at maximum conditions, see application information

Characteristic Symbol Test Conditions* Value Units

Package Thermal Resistance RθJA On 4-layer PCB based on JEDEC standard 37 ºC/W

*Additional thermal information available on the Allegro website.

Absolute Maximum Ratings (reference to GND)

Characteristic Symbol Notes Rating Units

Load Supply Voltage VBB 24 V

LX1, LX2, and LX3 Pins VLXn–1 to 24 V

PORZ and VDD Pins VIN –0.3 to 7 V

ENBx Pin Input Current IENBx Driven by a current-limited voltage source 1 mA

Operating Ambient Temperature TARange E –40 to 85 ºC

Maximum Junction Temperature TJ(max) 150 ºC

Storage Temperature Tstg –55 to 150 ºC

Recommended Operating Conditions

Characteristic Symbol Conditions Min. Typ. Max. Units

Load Supply Voltage VBB

To operate at VBB < 6 V, connect VDD

supply to the VBB supply. See Powering

Configurations section.

4.5 – 23 V

LX1, LX2, and LX3 Pins VLXn–0.7 – 23 V

Operating Ambient Temperature TA–40 – 85 ºC

Junction Temperature TJ–40 – 125 ºC

Description (continued)

The POR flag also indicates when the input voltage drops below

specification, giving the system controller advance warning while

the switchers continue to operate down to the shutdown level.

Internal diagnostics provide comprehensive protection against

overloads, input undervoltages, and overtemperatures.

Output current capability is ≈ 4.5A total for all 3 outputs, depending

on the combinations of VIN and each VOUT level.

The A4491 is provided in a 20-contact, 4 mm × 4 mm, 0.75 mm

nominal overall height QFN, with exposed pad for enhanced

thermal dissipation. It is lead (Pb) free, with 100% matte tin

leadframe plating.

Triple Output Step-Down Switching Regulator

A4491

Allegro MicroSystems, LLC

115 Northeast Cutoff

Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

Functional Block Diagram

ENB2

FB2

GND

Switcher #2

LX2

5 V / 1.5 A

VBB3

FB3

LX3

3.3 V / 1.5 A

Switcher #3

ENB1

4.7 H

10 F

10 H

ENB3

PORZ

VBB1

FB1

Switcher #1

Switcher Control

LX1

VCP

Bias Supply

PGND

VCP

CP1

CP2

Charge Pump

VCP

Regulator

VDD

Switch

POR Block

CPOR

C10

C14

10 F

C11

10 F

C12

10 F

C13

10 F

15 H

100 nF

47 nF

470 nF

10 FV

REG1

REG2

REG3

1.0 V / 1.5 A

10 F

VBB2

10 F

100 k

Note: All capacitors ceramic X5R.

Triple Output Step-Down Switching Regulator

A4491

Allegro MicroSystems, LLC

115 Northeast Cutoff

Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

Terminal List

Number Name Function

1 FB1 Feedback REG1

2 VDD Bias supply

3 GND1 Ground

4 FB2 Feedback REG2

5 ENB2 Enable REG2, logic input, active high

6 LX2 Switch node REG2

7 VBB22 Input supply for REG2

8 CPOR POR delay adjustment

9 PORZ Power on reset output, active low

10 VCP Charge pump reservoir

11 CP2 Charge pump capacitor terminal

12 CP1 Charge pump capacitor terminal

13 PGND1 Ground for charge pump circuitry

14 FB3 Feedback REG3

15 ENB3 Enable REG3, logic input, active high

16 LX3 Switch node REG3

17 VBB32 Input supply for REG3

18 VBB12 Input supply for REG1

19 LX1 Switch node REG1

20 ENB1 Enable REG1, logic input, active high

–PAD

3Exposed pad for enhanced thermal dissipation

1GND and PGND should be connected externally.

2The three VBBx pins should be connected together externally.

3Thermal pad should be connected to the ground (0 V) plane using thermal vias.

PAD

ENB1

LX1

VBB1

VBB3

LX3

LX2

VBB2

CPOR

PORZ

VCP

ENB3

FB3

PGND

CP1

CP2

FB1

VDD

GND

FB2

ENB2

Pin-out Diagram

Triple Output Step-Down Switching Regulator

A4491

Allegro MicroSystems, LLC

115 Northeast Cutoff

Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

ELECTRICAL CHARACTERISTICS* at TA = 25°C, VBB = 12 V, VDD supplied externally, unless noted otherwise

Characteristics Symbol Test Conditions Min. Typ. Max. Units

General

VBB Quiescent Current IBBON ENBx = high, ILOAD = 0 mA, VBB = 12 V,

current drawn by feedback resistors ignored – 1 2 mA

IBBOFF ENBx = 0 V – 1 – A

VDD Supply Range VDD 3.3 – 5.5 V

VDD Quiescent Current IDD ENBx = high – – 6 mA

ENBx = 0 V – 1 – A

REG1, REG2, and REG3

Feedback Input Bias Current IBIAS –400 –100 100 nA

Feedback Voltage VFB With respect to 0.8 V target voltage; VBB = 6 to 23 V – ±1 – %

Fixed Frequency fSW 470 550 630 kHz

Maximum Duty Cycle DCmax 90 – – %

Minimum Duty Cycle DCmin – 5 – %

Buck Switch On-Resistance RDS(on)

TJ = 25°C, ILOAD = 1.5 A, VBB = 6.0 V – 450 – m

TJ = 125°C, ILOAD = 1.5 A, VBB = 6.0 V – 700 – m

TJ = 25°C, ILOAD = 1.5 A, VBB = 4.5 V – 560 – m

TJ = 125°C, ILOAD = 1.5 A, VBB = 4.5 V – 870 – m

Current Limit Threshold ILIM Peak current through switch with D = 0.9 2.0 A

Soft Start Duration tss 0.625 1.25 1.875 ms

Logic Inputs and Outputs

ENBx Input Voltage VIL – – 0.8 V

VIH 2.0 – – V

ENBx Input Hysteresis VI(hys) 300 500 – mV

ENBx Input Current IIL V

IH  5 V –1 – 1 A

PORZ Output (Open Drain) VPORZL I

PORZL = 1 mA, fault asserted – – 0.4 V

PORZ Output Leakage Current IPORZH V

PORZ = 5 V, fault not asserted –1 – 1 A

Power-On Reset Duration tPOR C

POR = 470 nF 75 115 155 ms

Protection

VREGx Undervoltage Lockout Startup VREGUV(su) FB1, FB2, and FB3 rising – 85 – %VFB

VREGx Undervoltage Lockout Shutdown VREGUV(sd) FB1, FB2, and FB3 falling – 80 – %VFB

VREGx Undervoltage Lockout

Startup Hysteresis VREGUV(suhys) –5 –%

VBB Undervoltage Lockout Startup VBBUV(su) No external VDD supply, VBB rising 3.7 4.3 4.7 V

VBBCPUV(su) External VDD supply, VBB rising 3.8 4.2 4.6 V

VBB Undervoltage Lockout Shutdown VBBUV(sd) No external VDD supply, VBB falling 3.6 4.1 4.7 V

VBBCPUV(sd) External VDD supply, VBB falling 3.0 3.5 4.3 V

VBB Undervoltage Lockout

Shutdown Hysteresis

VBBUV(sdhys) No external VDD supply – 500 – mV

VBBCPUV(sdhys) External VDD supply – 600 – mV

VBB Undervoltage Warning Threshold VBBUV(por)

VBB falling (forces PORZ low); switchers continue

to operate – 3.6 – V

Junction Overtemperature Shutdown TJTSD Temperature rising – 165 – °C

Junction Overtemperature Shutdown

Hysteresis TJTSD(hys) Recovery = TJTSD –TJTSD(hys) – 15 – °C

*For input and output current specifications, negative current is defined as coming out of (sourcing) the specified pin.

Triple Output Step-Down Switching Regulator

A4491

Allegro MicroSystems, LLC

115 Northeast Cutoff

Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

Basic Operation

The A4491 contains three fixed frequency, buck switching con-

verters with peak current-mode control, including slope compen-

sation. Each converter can be independently turned on and off via

the enable inputs (EN1, EN2, and EN3), which are active high.

When enabled, the corresponding output is brought-up under the

control of a soft start routine, which avoids output voltage over-

shoot and minimizes input inrush current.

The output voltage is typically divided down by an external

potential divider, and is compared against an internal reference

voltage to produce an error signal, also known as the current

demand signal. The current signal through the buck switch is

converted into a voltage. This signal is then compared against the

current demand signal to create the required duty cycle.

At the beginning of each switching cycle, the buck switch is

turned on. When the current signal through the switch reaches the

level of the current demand signal, the on-time of the switch is

terminated. On the next switching cycle, the switch is turned on

again and the cycle is repeated.

One shared clock is used to define the switching frequency for

each regulator. Each of the three switching cycles (REG1, REG2,

and REG3) are phase shifted with respect to one another by 120°

in an attempt to minimize the pulsed current drawn from the

input filter capacitors. Under certain conditions, for example at

low VBB conditions and relatively high user-set output voltages,

switching overlap between channels is inevitable.

Under conditions, such as light loads or high VBB voltages, that

cause duty cycles (DC) of less than the minimum value, the

converter enters a pulse-skipping mode to ensure regulation is

maintained.

A charge pump regulator is provided to ensure a sufficient gate

drive is available for all three power switches across the full input

voltage range. This regulator allows operation even at very wide

operating duty cycles. On initial power-up, an internal regulator

is used to provide the bias supply for on-chip control functions.

Each regulator channel utilizes pulse-by-pulse current limiting in

the event of either a short circuit or an overload. If the overload

is applied long enough, the IC temperature may rise sufficiently

to cause the thermal shutdown circuit to operate. The part will

auto-restart under control of the soft start circuit after the thermal

disable condition is removed, and assuming all other conditions

are met. See the Shutdown section for more information.

Power Configuration

The A4491 supports alternative schemes for providing logic sup-

ply voltage on the VDD pin. In addition, the IC can be powered

up and down using either the VBB or ENB pins.

Powering VDD To minimize power dissipation, especially at

high input voltages, it is recommended that an external sup-

ply be applied to the VDD input pin. Typically, this voltage is

derived from one of the three regulated outputs that are set-up for

between 3.3 and 5 V (VREGx).

Another advantage of powering the VDD externally is that the

VBB undervoltage lockout level is lowered. To maximize the

run time of the switchers during a VBB power-down condition,

two alternative undervoltage shutdown conditions are supported,

depending on which VDD-powering configuration has been

implemented. When no external VDD is applied, the minimum

VBB, VBBUV(sd)

, is 4.1 V typical. When an external VDD is

applied, the minimum VBB, VBBCPUV(sd)

, is 3.5 V typical.

One note of caution when deriving VDD from a VREG output:

during initial application of VBB, the internal bias supply auto-

matically starts from the internal regulator because VREG has not

yet reached regulation. This means the startup threshold is deter-

mined by VBBUV(su) (4.3 V typical) because there is no external

VDD. When VREG has begun to supply VDD externally, the

shutdown threshold reduces to VBBCPUV(sd) (3.5 V typical). This

assumes that VREG is present.

Powering Up and Down with VBB Referring to figure 1,

each of the enable inputs (ENBx) are held high by being tied to

the VBB rail via a 100 kΩ resistor and the VDD is supplied from

one of the regulator outputs. When the VBB voltage reaches the

minimum threshold, VBBUV(su) , the charge pump supply (VCP)

ramps up. When VBB + VCP has reached the minimum thresh-

old VBBCPUV(su), the soft start routines are initiated (tSS) for all

three regulator channels (VREGx). When all three regulators

have reached the 85% FBx threshold, the power-on-reset timer

is initiated. After the power-on-reset period, tPOR

, has elapsed,

PORZ goes high, indicating that all the regulators and VBB are in

specification.

Functional Description

Triple Output Step-Down Switching Regulator

A4491

Allegro MicroSystems, LLC

115 Northeast Cutoff

Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

VBB

BBUV(su)

BBUV(por)

BBCPUV(su)

POR

BBCPUV(sd)

VBB+VCP

VREG1

VREG2

VREG3

PORZ

+5.5 V

85%FB1

85%FB3

85%FB2

ENB1

VBB

VREG1

VREG2

VREG3

POR

PORZ

85%FB1

85%FB3

85%FB2

ENB3

ENB2

80%FB2 85%FB2

Figure 1. Timing diagram for powering up and down using the VBB pin

Figure 2. Timing diagram for powering up and down using the ENB pin

Triple Output Step-Down Switching Regulator

A4491

Allegro MicroSystems, LLC

115 Northeast Cutoff

Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

When the VBB voltage starts to fall below the undervoltage warn-

ing level, VBBUV(por) , of 3.6 V typical, the PORZ flag resets.

This gives advance warning to the system controller that the VBB

voltage is falling. Note that this feature is only guaranteed when

VDD is supplied externally. During this interval, the three switch-

ers continue to operate.

While VBB falls further, the VCP supply also tends to fall, which

degrades the drive voltage to the series switches. In addition,

the higher voltage rails start to fall out of regulation first, as the

corresponding maximum duty cycle (Dmax) for these particular

converters is reached.

The regulators that have the lower output voltages achieve some

level of steady state, before the A4491 powers down when all

of the corresponding VBB undervoltage thresholds have been

reached. For example, it may be possible for a 1 V output to

continue to operate down to a VBB of 3.4 V typical, if the VDD

supply is derived externally. The extent of this effect depends on

a myriad of factors, including input and output filter capacitance,

output loads, gate drive amplitude, MOSFET RDS(on), and so

forth.

Powering Up and Down with Enable Referring to figure 2,

VBB is present and the UVLO start-up thresholds, VBBUV(su)

and VBBCPUV(su) have been reached. Each of the regulators are

enabled in turn. Initially, VREG1 is enabled and is brought-up

under the control of the soft start circuit (tSS). Before VREG1

reaches 85% FB1, VREG2 is enabled and is brought-up under a

separate soft start control.

When both regulators have reached their respective 85% FB

thresholds, the power-on-reset (POR) timer is initiated. Note that

the POR timer is only enabled after all of the enabled regulators

reach their corresponding 85% FB levels. After the power-on-

reset time, tPOR , has elapsed, if the FB levels of VREG1 and

VREG2 are not below their respective 80% FB levels, then the

PORZ signal will go high.

At some point later, if VREG3 is enabled, then the PORZ is

reset and VREG3 is brought-up under the control of the soft start

circuit. When the 85% FB3 threshold is reached, the POR timer

is initiated. After tPOR has elapsed, if all the FB levels are above

their respective 80% FB levels, then the PORZ signal will go

high.

Note that if any regulator channel is not enabled, the channel

will not influence PORZ. To avoid multiple signal changes of the

PORZ signal, it is recommended that the system be designed such

that all three regulator channels are within specification before

tPOR has elapsed.

If any regulator channel drops below 80% FB, the PORZ signal

will be reset. If the voltage then recovers to within 85% FB, the

POR timer is initiated again. Note that a soft start is not initiated

when the feedback voltage drops below the 80% FB level. This is

to allow a rapid auto-restart in the event of an overload or similar

fault. If a soft start is required, it is recommended that on receipt

of the PORZ reset signal, the system controller disables and then

re-enables the relevant regulator channels again. As soon as the

last regulator is disabled the PORZ signal is reset.

Power on Reset The power-on-reset duration, tPOR , is deter-

mined by selecting an appropriate capacitor connected to the

CPOR pin. The value of tPOR can be determined by the following

formula:

tPOR = 2.131 ×105 × CPOR . (1)

The PORZ output goes high when both VBB is above the under-

voltage warning levels, and the FB pins of the regulators that are

enabled are > 85% of the V

REG voltage.

Because the external capacitor is charged via a 5 μA current

source, care must be taken in the layout to avoid additional leak-

age paths. The capacitor should be positioned adjacent to the

CPOR pin, and the ground connection to the A4491 GND pin

should be as short as possible.

It is recommended that the tPOR period be set to exceed the

start-up phases of all three regulators, to avoid the possibility of

multiple triggerings of the PORZ output.

Output Voltage Selection The output voltage on each of the

three regulators is set by the following relationship, shown here

for the VREG1 channel:

R1R2

⎟

⎠

⎞

⎜

⎝

⎛

VFB

VREG1 – 1

(2)

where R2 (connected between GND and the FB1 pin) should

be a value between 4.7 and 12 kΩ. R1 is connected between the

output rail and the FB1 pin. VREG1 is the set output regulator

voltage. VFB is the reference voltage.

The tolerances of the feedback resistors influence the voltage set-

point. It is therefore important to consider the tolerance selection

when targeting an overall regulation figure.

Triple Output Step-Down Switching Regulator

A4491

Allegro MicroSystems, LLC

115 Northeast Cutoff

Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

The bias current, IBIAS

, flowing out of the FB1 node into R2, will

introduce a small voltage offset to the output.

Enable Each regulator channel can be individually enabled via

the corresponding ENBx pin. If any channel is required to start-

up automatically after the VBB voltage is applied, that particu-

lar channel should have the ENB pin tied to the VBB rail via a

pull up resistor.

This resistor should be selected to limit the current to less than

the maximum specified value, 1 mA. This prevents the internal

protection clamps from turning on. It is recommended that a

100 kΩ pull-up resistor be used. This would ensure the current

remains below the maximum value when VBB = 24 V.

Soft Start Each regulator channel contains a soft start circuit. A

soft start cycle is initiated when the appropriate regulator enable

input is set to high; the VBB, charge pump, and bias supply volt-

ages are above the minimum values; and no thermal shutdown

condition exists. Note that an overload or short circuit will not

cause a soft start cycle, unless a thermal shutdown event occurs.

During a soft start cycle, the reference voltage is ramped from

0 to 0.8 V typical, which in turn forces the current demand signal

to increase in a linear fashion.

Shutdown All converter channels are disabled in the event of

either a thermal shutdown event or an undervoltage on VBB

(VBBUV(sd) or VBBCPUV(sd)).

As soon as the above fault conditions have been removed, and

assuming the ENB inputs are enabled, the appropriate channels

will auto-restart under control of the soft start.

Current Limit The typical peak current limit for each channel is

specified as 2.5 A minimum, with a duty cycle of 0.9. The mini-

mum current limit occurs at maximum duty cycle (0.9), because

the slope compensation has a maximum effect under this condi-

tion. As the duty cycle reduces, the current limit increases. This

means for applications that operate with a narrow duty cycle, it is

possible to operate with a load current greater than 2.0 A.

Figure 3 illustrates the typical peak current limit versus duty

cycle. For example, it is possible to operate with a peak current

limit of 3.75 A with a duty cycle of 0.3.

As well as ensuring the peak current limit is not exceeded, under

worst case load and input voltage conditions, it is also important

to check the implications on the thermal performance. See the

Thermal Considerations section.

Component Selection

Inductor The inductance value, L, determines the ripple current.

It is important to ensure that the minimum current limit is not

exceeded under worst-case conditions: VBB(min), ILOAD(max),

fSW(min), and L(min).

It is recommended that gapped ferrite solutions be used as

opposed to powdered iron solutions, the latter of which exhibit

relatively high core losses that can have a large impact on long

term reliability.

Inductors are typically specified at two current levels, rms cur-

rent and saturation current. With regard to the rms current, it is

important to understand how the rms current level is specified,

in terms of ambient temperature. Some manufacturers quote an

ambient only, whilst others quote a temperature that includes a

self-induced temperature rise. For example, if an inductor is rated

for 85°C and includes a self-induced temperature rise of 25°C

at maximum load, then the inductor cannot be safely operated

beyond an ambient temperature of 60°C at full load. The rms cur-

rent can be assumed to be simply the maximum load current, with

perhaps some margin to allow for overloads, and so forth.

The first stage of determining the inductor value is to specify a

peak-to-peak ripple current of typically about 20% to 25% of the

maximum load.

5.0

4.5

4.0

3.5

3.0

2.5

2.0

1.5

0.5

1.0

0.5

020406080100

Duty Cycle (%)

Current Limit (A)

Figure 3. Current limit versus duty cycle

Triple Output Step-Down Switching Regulator

A4491

Allegro MicroSystems, LLC

115 Northeast Cutoff

Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

The maximum peak-to-peak ripple current, IRIPPLE , occurs at the

maximum input voltage. Therefore the duty cycle, D, should be

found under these conditions (for the VREG1 channel):

D(min) =.

VREG1+Vf

VBB(max)+Vf

(3)

where Vf is the forward voltage drop of the recirculation diode.

The required inductance can be found:

(min)

D(min)

IRIPPLE

VBB(max) – VREG1 fSW(min)

××

(4)

Note that the manufacturers inductance tolerance should also

be taken into account. This value may be as high as ±20%. The

peak-to-peak current should not exceed 1 A, to avoid instability

in the innermost circuit loops due to insufficient slope compensa-

tion.

The maximum peak current can be found from to ensure that the

saturation current level of the chosen inductor is not exceeded:

Isat ILOAD +

IRIPPLE

(5)

Recommended inductor manufacturers and ranges are:

• Taiyo Yuden: NR6045 series for 1.5 A outputs

• Taiyo Yuden: NRG4026 series for 1.0 A outputs

• Sumida: CDH74 series for 1.5 A outputs

Output Capacitor In the interests of size, cost and perfor-

mance, it is highly recommended that ceramic X5R or X7R

capacitor types be used. When using ceramic capacitors another

important consideration is the E-field effects on the actual value

of the capacitor. To minimize the effects of the capacitance

reducing with output voltage, it is recommended that the working

voltage of the capacitor be considerably more than the set output

voltage. As a suggestion, it is recommended that 6.3 V-rated

capacitors should be used for output voltages of 3.3 V and below.

For output voltages of 5 V, a 10 V-rated capacitor should be used.

The output capacitor determines the output voltage ripple and is

used to close the control loop. To guarantee stability, the capaci-

tance has to increase as the output voltage is reduced. This is

actually reasonable from a ripple voltage point of view, as the

ripple voltage is typically specified as a percentage of output

voltage.

The following table outlines what the minimum output capaci-

tance should be for a given output voltage:

Output Voltage

(V)

Minimum Output Capacitance

(μF)

510

3.3 20

1.8 to 2.5 30

<1.8 40

Capacitance values with greater than the above values can be

used with the effect of reducing the bandwidth. This may be nec-

essary in systems that have extremely low ripple/noise require-

ments.

The output ripple is largely determined by the output capacitance

and the effects of ESR and ESL can largely be ignored assuming

good layout practice is observed.

The output voltage ripple can be approximated to:

VRIPPLE ≈,

IRIPPLE

8 × fSW × COUT

(6)

When using ceramic capacitors, there is generally no need to con-

sider the current carrying capability due to the negligible heating

effects of the ESR. Also, the rms current flowing into the output

capacitor is extremely low.

Input Capacitor Again it is highly recommended that ceramic,

X5R or X7R capacitors be used.

The value of the input capacitance determines the amount of

current ripple (EMI) that appears at the source (VBB supply)

terminals. The amounts of current flowing in and out of the input

capacitor depend on the relative impedances between the input

capacitor impedance and the source impedance. To achieve a low

impedance filter solution it is recommended to place at least two

capacitors in parallel.

Triple Output Step-Down Switching Regulator

A4491

Allegro MicroSystems, LLC

115 Northeast Cutoff

Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

Again, there is generally no need to consider the heating effects

of the rms current flowing through the ESR. Also, the phase-

shifting of the input current drawn by each of the regulators helps

to reduce the overall rms current.

Flyback Diode This diode conducts during the switch off-time.

A Schottky diode is recommended to minimize both the forward

drop and switching losses.

The worst case dissipation occurs at maximum VBB

, when the

duty cycle, D, is a minimum. The average current through the

diode can be found:

IDIODE(av) = ILOAD × (1 – D(min)) . (7)

The forward voltage drop, Vf , can be found from the diode

characteristics by using the actual load current (not the average

current).

The static power dissipation can be found:

PSTAT = ILOAD(av) × Vf . (8)

It is also important to take into account the thermal rating of

the package, RθJA

, and the ambient temperature, to ensure that

enough heatsinking is provided to maintain the diode junction

temperature within the safe operating area for the device.

To minimize the heating effects from the A4491 on the diode and

vice-versa, it is recommended that the diode be mounted on the

reverse side of the printed circuit board.

Support Components POR capacitor (C11), charge pump

capacitor (C1), reservoir capacitor (C2) and VDD filter capacitor

(C12) should be ceramic X5R or X7R.

Thermal Considerations

To ensure the A4491 operates in the safe operating area, which

effectively means restricting the junction temperature to less than

150°C, several checks should be made. The general approach

is to work out what thermal impedance (RJA) is required to

maintain the junction temperature at a given level, for a particular

power dissipation.

Another factor worth considering is that other power dissipating

components on the system PCB may influence the thermal per-

formance of the A4491. For example, the power loss contribution

from the recirculation diode and the sense resistor may cause the

junction temperature of the A4491 to be higher than expected.

The following steps can be used as a guideline for determining a

suitable thermal solution. It should be noted that this process is

usually an iterative one to achieve the optimum solution. These

factors can be considered as follows:

Step 1. Estimate the maximum ambient temperature, TA(max) , of

the application.

Step 2. Define the maximum junction temperature, TJ(max). Note

that the absolute maximum is 150°C.

Step 3. Determine the worst case power dissipation, PD(max).

The evaluation should consider these at maximum load and mini-

mum VBB. Contributors are switch static and dynamic losses, and

control losses. These are described in the following sections

Switch Static Losses The following steps can be used to

determine switch static losses:

Estimate the maximum duty cycle:

D(max) =,

VREG

+ Vf

VBB

(min) + Vf

(9)

where Vf is the forward voltage drop of the Schottky diode under

the given load current.

Estimate the RDS(on) of the each regulator switch at the given

junction temperature:

RDS(on)TJ RDS(on)25C 1+

⎟

⎠

⎞

⎜

⎝

⎛

200

TJ – 25

(10)

Note that if the VBB range is restricted to between 4.5 and 5.5 V,

the RDS(on) increases. For example, the RDS(on) at 25°C with a

VBB greater than 6 V is 450 mΩ typical, as stated in the Electri-

cal Characteristics table. Under the same temperature conditions,

with the VBB = 4.5 V, the RDS(on) is 560 mΩ typical. For VBB

voltages between 4.5 and 6 V, the RDS(on) can be found by linear

approximation. For more information on operating the A4491

between a VBB voltage of 4.5 and 5.5 V, see the Power Configu-

rations section.

The static loss for each switch can be determined:

PSTAT = ILOAD2 × D(max) × RDS(on)TJ , (11)

where ILOAD is the load for that particular regulator channel.

Triple Output Step-Down Switching Regulator

A4491

Allegro MicroSystems, LLC

115 Northeast Cutoff

Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

Switch Dynamic Losses The following can be used to deter-

mine switch dynamic losses:

Both turn on and turn off losses can be estimated:

PDYN VBB

(min)

fSW

10–9

ILOAD

(12)

where fSW is the switching frequency.

Control Losses The following steps can be used to determine

control losses:

PVBB = IBBON × VBB , (13)

where IBBON is the quiescent current assuming all three regulators

are on.

PVDD = IVDD × VDD , (14)

where IVDD and is the quiescent current on VDD.

Total Losses The total losses can now be estimated:

PTOTAL = PSTAT1 + PSTAT2 + PSTAT2

+PDYN1 +PDYN2 + PDYN3

+PVBB + PVDD . (15)

Thermal Impedance The thermal impedance required for the

solution can now be determined:

RQJA =

– TA

PTOTAL

(16)

Example

Selected parameters:

VBB(min) = 6 V

VREG1 = 5 V at 1 A

VREG2 = 3.3 V at 1 A

VREG3 = 1.8 V at 800 mA

TA= 70°C

TJ = 115°C

Vf = 0.4 V

(a) Switch static losses

VREG1 duty cycle, D10.84

5+0.4

6+0.4

VREG2 duty cycle, D20.58

3.3+0.4

6+0.4

VREG3 duty cycle, D30.34

1.8+0.4

6+0.4

The RDS(on) of each switch can be found:

RDS(on)TJ 450×10–3 1+

=0.653 Ω

⎟

⎠

⎞

⎜

⎝

⎛

200

115 – 25

The static loss of each switch can be found:

PSTAT1 = 12 × 0.84 × 0.653 = 0.55 W

PSTAT2 = 12 × 0.58 × 0.653 = 0.379 W

PSTAT3 = 0.82 × 0.34 × 0.653 = 0.14 W

(b) Switch dynamic losses

PDYN1 0.045 W

10–9

500

103

PDYN2 0.045 W

10–9

500

103

PDYN3 0.036 W

0.8

10–9

500

103

PVBB = 0.005 × 6 = 0.03 W

PVDD = 0.001 × 3.3 = 0.003 W

(d) The total power dissipation can now be found:

PTOTAL = 0.55 + 0.379 + 0.14 + 0.045

+ 0.045 + 0.036 + 0.03 + 0.003 = 1.228 W

(e) The thermal impedance required for the solution can be

found:

RQJA 36.6 °C/W

115

– 70

1.228

For this particular solution a high thermal efficiency board is

required to ensure the junction temperature is kept below 115°C.

For maximum effectiveness, the PCB pad area underneath the

thermal pad of the A4491 should be exposed copper. Several

thermal vias (say between 4 and 8) should be used to connect

the thermal pad to the internal ground plane. If possible, an

additional thermal copper plane should be applied to the bottom

side of the PCB and connected to the thermal pad of the A4491

through the vias.

Triple Output Step-Down Switching Regulator

A4491

Allegro MicroSystems, LLC

115 Northeast Cutoff

Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

This calculation assumes no thermal influence from other compo-

nents. If possible, it is advisable to mount the flyback diodes on

the reverse side of the printed circuit board. Ensure low imped-

ance electrical connections are implemented between board

layers.

PCB Layout Guidelines The ground plane is largely dictated

by the thermal requirements described in the previous section.

The ground referenced power components should be referenced

to a star ground, located away from the A4491 to minimize

ground bounce issues.

A small, local, relatively quiet ground plane near the A4491 should

be used for the ground referenced support components, to mini-

mize interference effects of ground noise from the power circuitry.

Figure 4 illustrates the recommended grounding architecture.

To avoid ground bounce and offset issues, it is highly recom-

mended that the ground referenced feedback resistors (R2, R4,

and R6) should be connected as close to the GND connection of

the A4491 as possible.

A local quiet ground plane around these components can be

implemented, however, this ground plane should have a high

impedance connection to the star connection of the power stages.

If a ground plane is used, it is recommended that it does not

overlap the switching nodes (LX1, LX2, and LX3) to avoid the

possibility of noise pick-up. To minimize the possibility of noise

injection issues, it is recommended to isolate the ground plane

around high impedance nodes such as: FBx, ENBx and CPOR.

In terms of grounding the power components, a star connection

should be made to minimize the ground loop impedances. Note

that although a ground plane may be required to meet the thermal

characteristics of the solution it is still imperative to implement

a ground star connection for the power components. The ground

for the charge pump (PGND) should be connected to the thermal

vias.

Figures 5 and 6 below illustrates the importance of keeping the

ground connections as short as possible and forming good star

connections.

Figure 5 also illustrates the current conduction paths during the

on-cycle of the switching FET. The following points should be

noted:

• The capacitor CIN should be placed as close as possible to the

LOAD

REG

OUT

Star Connection

Figure 5. FET on-cycle current conduction paths

LOAD

REG

OUT

Star Connection

Figure 6. FET off-cycle current conduction paths

Cin Cout

Star Connection

A4491

Internal Ground Plane

Thermal Vias

Power Circuitry

A4491 Support

Com

onents

Local “Quiet’

Ground Plane GND PGND

Figure 4. Ground plane configurations

Triple Output Step-Down Switching Regulator

A4491

Allegro MicroSystems, LLC

115 Northeast Cutoff

Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

VBB

VDD

Only VBB supplied

6 to 23 V

REG

Comments:

-Simple configuration, only one supply required

-Increased power losses at higher VBB voltages

-V

start-up = 4.3 V (typical), shutdown = 4.1 V

(typical)

VBB

VDD

VDD applied externally (first option)

6 to 23 V

REG

Comments:

-Reduced power losses at higher VBB voltages

-V

start-up = 4.2 V (typical), shutdown = 3.5 V

(typical). In this case, the start-up threshold

BBUV(su)

) is lower because V

REG

is not present

VBB

VDD

VDD applied externally (second option)

4.5 to 5.5 V

REG

Comments:

-Power restricted as V

< 6 V, due to increase in

DS(on)

of buck switches

-V

start-up = 4.2 V (typical), shutdown = 3.5 V (typical)

VBB terminals. The capacitance should be split between the VBB

terminals for VREG1 and VREG3 and the VBB terminal for VREG2.

The VBB terminals for VREG1 and VREG2 should be connected

via short and wide traces to the VBB terminal for VREG3.

• Each inductor should be connected as close as possible to the

respective switching FET (LX1, LX2, and LX3) and output

capacitors.

Figure 6 shows the current conduction path during the off-cycle

of the switching FET. The following points should be noted:

• The diode D should be placed as close as possible to both the

switching FET and the inductor.

• Support components: POR capacitor (C11), charge pump ca-

pacitor (C1), reservoir capacitor (C2), and VDD filter capacitor

(C12) should be located as close as possible to their respective

terminal connections. The ground referenced capacitors should

be connected as close to the GND terminal as possible.

Powering Configurations The following three diagrams show

typical configurations for providing power to the application. The

middle diagram corresponds to the typical application shown on

the front page.

Triple Output Step-Down Switching Regulator

A4491

Allegro MicroSystems, LLC

115 Northeast Cutoff

Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

Package ES, 20-Pin QFN

0.95

SEATING

PLANE

C0.08

21X

ATerminal #1 mark area

Coplanarity includes exposed thermal pad and terminals

BExposed thermal pad (reference only, terminal #1

identifier appearance at supplier discretion)

For Reference Only

(reference JEDEC MO-220WGGD)

Dimensions in millimeters

Exact case and lead configuration at supplier discretion within limits shown

Reference land pattern layout (reference IPC7351

QFN50P400X400X80-21BM)

All pads a minimum of 0.20 mm from all adjacent pads; adjust as necessary

to meet application process requirements and PCB layout tolerances; when

mounting on a multilayer PCB, thermal vias at the exposed thermal pad land

can improve thermal dissipation (reference EIA/JEDEC Standard JESD51-5)

4.10

0.30

0.50

4.10

0.50

0.75 ±0.05

2.60

0.25 +0.05

–0.07

0.40 +0.15

–0.10

4.00 ±0.15

4.00 ±0.15 2.60

2.60

PCB Layout Reference View

Triple Output Step-Down Switching Regulator

A4491

Allegro MicroSystems, LLC

115 Northeast Cutoff

Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

For the latest version of this document, visit our website:

www.allegromicro.com

Allegro MicroSystems, LLC reserves the right to make, from time to time, such de par tures from the detail spec i fi ca tions as may be required to

permit improvements in the per for mance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that

the information being relied upon is current.

Allegro’s products are not to be used in life support devices or systems, if a failure of an Allegro product can reasonably be expected to cause the

failure of that life support device or system, or to affect the safety or effectiveness of that device or system.

The in for ma tion in clud ed herein is believed to be ac cu rate and reliable. How ev er, Allegro MicroSystems, LLC assumes no re spon si bil i ty for its

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Revision History

Revision Revision Date Description of Revision

Rev. 1 June 26, 2012 Update IDD and undervoltage lockout