1. General description
The 74HC165; 74HCT165 is an 8-bit serial or parallel-in/serial-out shift register. The
device features a serial data input (DS), eight parallel data inputs (D0 to D7) and two
complementary serial outputs (Q7 and Q7). When the parallel load input (PL) is LOW the
data from D0 to D7 is loaded into the shi ft regi ster asynchronously. When PL is HIGH data
enters the register serially at DS. When the clock enable input (CE) is LOW dat a is shifted
on the LOW-to-HIGH transitions of the CP input. A HIGH on CE will disable the CP input.
Inputs include clamp diodes, this enables the use of current limiting resistors to interface
inputs to voltages in excess of VCC.
2. Features and benefits
Asynchronous 8-bit parallel load
Synchronous serial input
Complies with JEDEC standard no. 7A
Input levels:
For 74HC165: CMOS level
For 74HCT165: TTL level
ESD protection:
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A ex ce ed s 200 V
Specified from 40 Cto+85C and from 40 Cto+125C
3. Applications
Parallel-to-serial data conversion
4. Ordering information
74HC165; 74HCT165
8-bit parallel-in/serial out shift register
Rev. 4 — 28 December 2015 Product data sheet
Table 1. Ordering information
Type number Package
Temperature range Name Description Version
74HC165D 40 C to +125 C SO16 plastic small outline package; 16 leads; body width 3.9 mm SOT109-1
74HCT165D
74HC165DB 40 C to +125 C SSOP16 plastic shrink small outline package; 16 leads;
body width 5.3 mm SOT338-1
74HCT165DB
74HC_HCT165 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet Rev. 4 — 28 December 2015 2 of 21
NXP Semiconductors 74HC165; 74HCT165
8-bit parallel-in/serial out shift register
5. Functional diagram
74HC165PW 40 C to +125 C TSSOP16 plastic thin shrink small outline package; 16 leads; body
width 4.4 mm SOT403-1
74HCT165PW
74HC165BQ 40 C to +125 C DHVQFN16 plastic dual in-line compatible thermal enhanced very thin
quad flat package; no leads; 16 terminals; body
2.5 3.5 0.85 mm
SOT763-1
74HCT165BQ
Table 1. Ordering information …continued
Type number Package
Temperature range Name Description Version
Fig 1. Logic symbol Fig 2. IEC logic symbol
PQD
'
'
'
'
'
'
'
'
&3 &(
'6
4
4
3/
PQD
&
&>/2$'@
*>6+,)7@
'
'
'
65*
Fig 3. Functional di agram
PQD
%,76+,)75(*,67(5
3$5$//(/,16(5,$/287
3/
'6
&3
4
' ' ' ' ' ' ' '
4
&(
74HC_HCT165 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet Rev. 4 — 28 December 2015 3 of 21
NXP Semiconductors 74HC165; 74HCT165
8-bit parallel-in/serial out shift register
6. Pinning information
6.1 Pinning
6.2 Pin description
(1) This is not a supply pin. The substrate is attached to this
pad using conductive die attach material. There is no
electrical or mechanical requirement to solder this pad.
However, if it is soldered, the solder land should remain
floating or be connected to GND.
Fig 4. Pin configuration (SO16 and (T)SSOP16) Fig 5. Pin configuration (DHVQFN16)
+&
+&7
3
/
9&&
&
3
&(
'
'
'
'
'
'
'
'
4
'6
*1' 4
DDK
DDK
+&
+&7
4 '6
*1'
' '
' '
' '
' '
&3 &(
*1'
4
3/
9&&
7UDQVSDUHQWWRSYLHZ
WHUPLQDO
LQGH[DUHD
Table 2. Pin description
Symbol Pin Description
PL 1 asynchronous parallel load input (active LOW)
CP 2 clock input (LOW-to-HIGH edge-triggered)
Q7 7 complementary output from the last stage
GND 8 ground (0 V)
Q7 9 serial output from the last stage
DS 10 serial data input
D0 to D7 11, 12, 13, 14, 3, 4, 5, 6 parallel data inputs (also referred to as Dn)
CE 15 clock enable input (active LOW)
VCC 16 positive supply voltage
74HC_HCT165 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet Rev. 4 — 28 December 2015 4 of 21
NXP Semiconductors 74HC165; 74HCT165
8-bit parallel-in/serial out shift register
7. Functional description
[1] H = HIGH voltage level;
h = HIGH voltage level one set-up time prior to the LOW-to-HIGH clock transition;
L = LOW voltage level;
l = LOW voltage level one set-up time prior to the LOW-to-HIGH clock transition;
q = state of the referenced output one set-up time prior to the LOW-to-HIGH clock transition;
X = don’t care;
= LOW-to-HIGH clock transition.
Table 3. Function table[1]
Operating modes Inputs Qn registers Outputs
PL CE CP DS D0 to D7 Q0 Q1 to Q6 Q7 Q7
parallel load L X X X L L L to L L H
L X X X H H H to H H L
serial shift H L l X L q0 to q5 q6 q6
HLh X H q0 to q5 q6 q6
HL l X L q0 to q5 q6 q6
HL h X H q0 to q5 q6 q6
hold “do nothing” H H X X X q0 q1 to q6 q7 q7
HXHXXq0q1 to q6q7q7
Fig 6. Timing diagram
&(
&3
'6
3/
'
'
'
'
'
'
'
'
4
4
PQD
LQKLELW VHULDOVKLIW
ORDG
74HC_HCT165 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet Rev. 4 — 28 December 2015 5 of 21
NXP Semiconductors 74HC165; 74HCT165
8-bit parallel-in/serial out shift register
8. Limiting values
[1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2] Ptot derates linearly with 8 mW/K above 70 C.
[3] Ptot derates linearly with 5.5 mW/K above 60 C.
[4] Ptot derates linearly with 4.5 mW/K above 60 C.
9. Recommended operating conditions
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V)
Symbol Parameter Conditions Min Max Unit
VCC supply voltage 0.5 +7 V
IIK input clamping current VI < 0.5 V or VI>V
CC +0.5V [1] -20 mA
IOK output clamping current VO < 0.5 V or VO>V
CC +0.5V [1] -20 mA
IOoutput current 0.5 V < VO< VCC +0.5V - 25 mA
ICC supply current - 5 0 mA
IGND ground current 50 - mA
Tstg storage temperature 65 +150 C
Ptot total power dissipation Tamb = 40 C to +125 C
SO16 package [2] -500mW
(T)SSOP16 package [3] -500mW
DHVQFN16 package [4] -500mW
Table 5. Recommended operating con ditions
Voltages are referenced to GND (ground = 0 V)
Symbol Parameter Conditions 74HC165 74HCT165 Unit
Min Typ Max Min Typ Max
VCC supply voltage 2.0 5.0 6.0 4.5 5.0 5.5 V
VIinput voltage 0 - VCC 0-V
CC V
VOoutput voltage 0 - VCC 0-V
CC V
Tamb ambient temperature 40 - +125 40 - +125 C
t/V input transition rise and fall rate VCC = 2.0 V - - 625 - - - ns/V
VCC = 4.5 V - 1.67 139 - 1.67 139 ns/V
VCC = 6.0 V - - 83 - - - ns/V
74HC_HCT165 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet Rev. 4 — 28 December 2015 6 of 21
NXP Semiconductors 74HC165; 74HCT165
8-bit parallel-in/serial out shift register
10. Static characteristics
Table 6. Static characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions 25 C40 C to +85 C40 C to +125 CUnit
Min Typ Max Min Max Min Max
74HC165
VIH HIGH-level
input voltage VCC = 2.0 V 1.5 1.2 - 1.5 - 1.5 - V
VCC = 4.5 V 3.15 2.4 - 3.15 - 3.15 - V
VCC = 6.0 V 4.2 3.2 - 4.2 - 4.2 - V
VIL LOW-level
input voltage VCC = 2.0 V - 0.8 0.5 - 0.5 - 0.5 V
VCC = 4.5 V - 2.1 1.35 - 1.35 - 1 .3 5 V
VCC = 6.0 V - 2.8 1.8 - 1.8 - 1.8 V
VOH HIGH-level
output voltage VI = VIH or VIL
IO = 20 A; VCC = 2.0 V 1.9 2.0 - 1.9 - 1.9 - V
IO = 20 A; VCC = 4.5 V 4.4 4.5 - 4.4 - 4.4 - V
IO = 20 A; VCC = 6.0 V 5.9 6.0 - 5.9 - 5.9 - V
IO = 4.0 mA; VCC = 4.5 V 3.98 4.32 - 3.84 - 3.7 - V
IO = 5.2 mA; VCC = 6.0 V 5.48 5.81 - 5.34 - 5.2 - V
VOL LOW-level
output voltage VI = VIH or VIL
IO = 20 A; VCC = 2.0 V - 0 0.1 - 0.1 - 0.1 V
IO = 20 A; VCC = 4.5 V - 0 0.1 - 0.1 - 0.1 V
IO = 20 A; VCC = 6.0 V - 0 0.1 - 0.1 - 0.1 V
IO = 4.0 mA; VCC = 4.5 V - 0.15 0.26 - 0.33 - 0.4 V
IO = 5.2 mA; VCC = 6.0 V - 0.16 0.26 - 0.33 - 0.4 V
IIinput leakage
current VI = VCC or GND;
VCC =6.0V --0.1 - 1-1A
ICC supply current VI = VCC or GND; IO=0A;
VCC =6.0V - - 8.0 - 80 - 160 A
CIinput
capacitance -3.5- - - - -pF
74HCT165
VIH HIGH-level
input voltage VCC = 4.5 V to 5.5 V 2.0 1.6 - 2.0 - 2.0 - V
VIL LOW-level
input voltage VCC = 4.5 V to 5.5 V - 1.2 0.8 - 0.8 - 0.8 V
VOH HIGH-level
output voltage VI = VIH or VIL; VCC = 4.5 V
IO = 20 A 4.4 4.5 - 4.4 - 4.4 - V
IO = 4.0 mA 3.98 4.32 - 3.84 - 3.7 - V
VOL LOW-level
output voltage VI = VIH or VIL; VCC = 4.5 V
IO = 20 A; VCC = 4.5 V - 0 0.1 - 0.1 - 0.1 V
IO = 5.2 mA; VCC = 6.0 V - 0.16 0.26 - 0.33 - 0.4 V
IIinput leakage
current VI = VCC or GND;
VCC =6.0V --0.1 - 1-1A
74HC_HCT165 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet Rev. 4 — 28 December 2015 7 of 21
NXP Semiconductors 74HC165; 74HCT165
8-bit parallel-in/serial out shift register
11. Dynamic characteristics
ICC supply current VI = VCC or GND; IO=0A;
VCC =6.0V - - 8.0 - 80 - 160 A
ICC additional
supply current per input pin;
VI=V
CC 2.1 V;
other inputs at VCC or GND;
VCC = 4.5 V to 5.5 V
Dn and DS inputs - 35 126 - 157.5 - 171.5 A
CP CE, and PL inputs - 65 234 - 292.5 - 318.5 A
CIinput
capacitance -3.5- - - - -pF
Table 6. Static characteristics …continued
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions 25 C40 C to +85 C40 C to +125 CUnit
Min Typ Max Min Max Min Max
Table 7. Dynamic characteristics
GND (ground = 0 V); CL = 50 pF unless otherwise specified; for test circuit, see Figure 12
Symbol Parameter Conditions 25 C40 C to +85 C40 C to +125 CUnit
Min Typ Max Min Max Min Max
74HC165
tpd propagation
delay CP or CE to Q7, Q7;
see Figure 7 [1]
VCC = 2.0 V - 52 165 - 205 - 250 ns
VCC = 4.5 V - 19 33 - 41 - 50 ns
VCC = 6.0 V - 15 28 - 35 - 43 ns
VCC = 5.0 V; CL=15pF - 16 - - - - - ns
PL to Q7, Q7; see Figure 8
VCC = 2.0 V - 50 165 - 205 - 250 ns
VCC = 4.5 V - 18 33 - 41 - 50 ns
VCC = 6.0 V - 14 28 - 35 - 43 ns
VCC = 5.0 V; CL=15pF - 15 - - - - - ns
D7 to Q7, Q7; see Figure 9
VCC = 2.0 V - 36 120 - 150 - 180 ns
VCC = 4.5 V - 13 24 - 30 - 36 ns
VCC = 6.0 V - 10 20 - 26 - 31 ns
VCC = 5.0 V; CL=15pF - 11 - - - - - ns
tttransition
time Q7, Q7 output; see Figure 7 [2]
VCC = 2.0 V - 19 75 - 95 - 110 ns
VCC = 4.5 V - 7 15 - 19 - 22 ns
VCC = 6.0 V - 6 13 - 16 - 19 ns
74HC_HCT165 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet Rev. 4 — 28 December 2015 8 of 21
NXP Semiconductors 74HC165; 74HCT165
8-bit parallel-in/serial out shift register
tWpulse width CP input HIGH or LOW;
see Figure 7
VCC = 2.0 V 80 17 - 100 - 120 - ns
VCC = 4.5 V 16 6 - 20 - 24 - ns
VCC = 6.0 V 14 5 - 17 - 20 - ns
PL input LOW; see Figure 8
VCC = 2.0 V 80 14 - 100 - 120 - ns
VCC = 4.5 V 16 5 - 20 - 24 - ns
VCC = 6.0 V 14 4 - 17 - 20 - ns
trec recovery time PL to CP, CE; see Figure 8
VCC = 2.0 V 100 22 - 125 - 150 - ns
VCC = 4.5 V 20 8 - 25 - 30 - ns
VCC = 6.0 V 17 6 - 21 - 26 - ns
tsu set-up time DS to CP, CE; see Figure 10
VCC = 2.0 V 80 11 - 100 - 120 - ns
VCC = 4.5 V 16 4 - 20 - 24 - ns
VCC = 6.0 V 14 3 - 17 - 20 - ns
CE to CP and CP to CE;
see Figure 10
VCC = 2.0 V 80 17 - 100 - 120 - ns
VCC = 4.5 V 16 6 - 20 - 24 - ns
VCC = 6.0 V 14 5 - 17 - 20 - ns
Dn to PL; see Figure 11
VCC = 2.0 V 80 22 - 100 - 120 - ns
VCC = 4.5 V 16 8 - 20 - 24 - ns
VCC = 6.0 V 14 6 - 17 - 20 - ns
thhold time DS to CP, CE and Dn to PL;
see Figure 10
VCC = 2.0 V 5 6 - 5 - 5 - ns
VCC = 4.5 V 5 2 - 5 - 5 - ns
VCC = 6.0 V 5 2 - 5 - 5 - ns
CE to CP and CP to CE;
see Figure 10
VCC = 2.0 V 5 17 - 5 - 5 - ns
VCC = 4.5 V 5 6- 5 - 5 - ns
VCC = 6.0 V 5 5- 5 - 5 - ns
Table 7. Dynamic characteristics …continued
GND (ground = 0 V); CL = 50 pF unless otherwise specified; for test circuit, see Figure 12
Symbol Parameter Conditions 25 C40 C to +85 C40 C to +125 CUnit
Min Typ Max Min Max Min Max
74HC_HCT165 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet Rev. 4 — 28 December 2015 9 of 21
NXP Semiconductors 74HC165; 74HCT165
8-bit parallel-in/serial out shift register
fmax maximum
frequency CP input; see Figure 7
VCC = 2.0 V 6 17 - 5 - 4 - MHz
VCC = 4.5 V 30 51 - 24 - 20 - MHz
VCC = 6.0 V 35 61 - 28 - 24 - MHz
VCC = 5.0 V; CL=15pF - 56 - - - - - MHz
CPD power
dissipation
capacitance
per package;
VI=GNDtoV
CC
[3] -35- - - - - pF
74HCT165
tpd propagation
delay CE, CP to Q7, Q7;
see Figure 7 [1]
VCC = 4.5 V - 17 34 - 43 - 51 ns
VCC = 5.0 V; CL=15pF - 14 - - - - - ns
PL to Q7, Q7; see Figure 8
VCC = 4.5 V - 20 40 - 50 - 60 ns
VCC = 5.0 V; CL=15pF - 17 - - - - - ns
D7 to Q7, Q7; see Figure 9
VCC = 4.5 V - 14 28 - 35 - 42 ns
VCC = 5.0 V; CL=15pF - 11 - - - - - ns
tttransition
time Q7, Q7 output; see Figure 7 [2]
VCC = 4.5 V - 7 15 - 19 - 22 ns
tWpulse width CP input; see Figure 7
VCC = 4.5 V 16 6 - 20 - 24 - ns
PL input; see Figure 8
VCC = 4.5 V 20 9 - 25 - 30 - ns
trec recovery time PL to CP, CE; see Figure 8
VCC = 4.5 V 20 8 - 25 - 30 - ns
tsu set-up time DS to CP, CE ; see Figure 10
VCC = 4.5 V 20 2 - 25 - 30 - ns
CE to CP and CP to CE;
see Figure 10
VCC = 4.5 V 20 7 - 25 - 30 - ns
Dn to PL; see Figure 11
VCC = 4.5 V 20 10 - 25 - 30 - ns
thhold time DS to CP, CE and Dn to PL;
see Figure 10
VCC = 4.5 V 7 1- 9 - 11 - ns
CE to CP and CP to CE;
see Figure 10
VCC = 4.5 V 0 7- 0 - 0 - ns
Table 7. Dynamic characteristics …continued
GND (ground = 0 V); CL = 50 pF unless otherwise specified; for test circuit, see Figure 12
Symbol Parameter Conditions 25 C40 C to +85 C40 C to +125 CUnit
Min Typ Max Min Max Min Max
74HC_HCT165 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet Rev. 4 — 28 December 2015 10 of 21
NXP Semiconductors 74HC165; 74HCT165
8-bit parallel-in/serial out shift register
[1] tpd is the same as tPHL and tPLH.
[2] tt is the same as tTHL and tTLH.
[3] CPD is used to determine the dynamic power dissipation (PD in W).
PD = CPD VCC2 fi + (CL VCC2 fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
(CL VCC2 fo) = sum of outputs;
CL = output load capacitance in pF;
VCC = supply voltage in V.
12. Waveforms
fmax maximum
frequency CP input; see Figure 7
VCC = 4.5 V 26 44 - 21 - 17 - MHz
VCC = 5.0 V; CL=15pF - 48 - - - - - MHz
CPD power
dissipation
capacitance
per package;
VI=GNDtoV
CC 1.5 V [3] -35- - - - - pF
Table 7. Dynamic characteristics …continued
GND (ground = 0 V); CL = 50 pF unless otherwise specified; for test circuit, see Figure 12
Symbol Parameter Conditions 25 C40 C to +85 C40 C to +125 CUnit
Min Typ Max Min Max Min Max
Measurement points are given in Table 8.
VOL and VOH are typical voltage output levels that occur with the output load.
Fig 7. The clock (CP) or clock enable (CE) to output (Q7 or Q7) propagation delays, the clock pulse width, the
maximum clock frequency and the ou tput transition times
PQD
&
3RU&(LQSXW
4RU4RXWSXW
W3+/
W7+/ W7/+
W3/+
W:
I
PD[
90
92+
9,
*1'
92/
90
74HC_HCT165 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet Rev. 4 — 28 December 2015 11 of 21
NXP Semiconductors 74HC165; 74HCT165
8-bit parallel-in/serial out shift register
Measurement points are given in Table 8.
VOL and VOH are typical voltage output levels that occur with the output load.
Fig 8. The p arallel lo ad (P L ) pulse width, the parallel load to output (Q7 or Q7) propagation delays, the parallel
load to clock (CP) and clock enable (CE) recovery time
PQD
3/LQSXW
&(&3LQSXW
4RU4RXWSXW
W3+/
W:WUHF
90
92+
9,
*1'
9,
*1'
92/
90
90
Measurement points are given in Table 8.
VOL and VOH are typical voltage output levels that occur with the output load.
Fig 9. The data input (D7) to output (Q7 or Q7) propagation delays when PL is LOW
PQD
'LQSXW
4RXWSXW
4RXWSXW
W3+/
W3+/
90
92+
9,
*1'
92+
92/
92/
90
W3/+
W3/+
90
74HC_HCT165 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet Rev. 4 — 28 December 2015 12 of 21
NXP Semiconductors 74HC165; 74HCT165
8-bit parallel-in/serial out shift register
The shaded areas indicate when the input is permitted to change for predictable output performance
Measurement points are given in Table 8.
VOL and VOH are typical voltage output levels that occur with the output load.
(1) CE may change only from HIGH-to-LOW while CP is LOW, see Section 1.
Fig 10. The set-up and hold times from the serial data input (DS) to the clock (CP) and clock enable (CE) inputs,
from the clock enable input (CE) to the clock input (CP) and from the clock input (CP) to the
clock enable input (CE)
WK
WVX WVX
WK
W:
90
90
*1'
9,
*1'
9,
'6LQSXW
WVX
90
PQD
*1'
9,
&3&(LQSXW
&3&(LQSXW
Measurement points are given in Table 8.
VOL and VOH are typical voltage output levels that occur with the output load.
Fig 11. The set-up and hold times from the data inputs (Dn) to the parallel load input (PL)
PQD
'QLQSXW
3/LQSXW
W
VX
W
K
9
,
*1'
9
,
*1'
9
0
9
0
W
VX
W
K
9
0
9
0
Table 8. Measurement points
Type Input Output
VIVMVM
74HC165 VCC 0.5VCC 0.5VCC
74HCT165 3 V 1.3 V 1.3 V
74HC_HCT165 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet Rev. 4 — 28 December 2015 13 of 21
NXP Semiconductors 74HC165; 74HCT165
8-bit parallel-in/serial out shift register
Test data is given in Table 9.
Definitions for test circuit:
RT = Termination resistance should be equal to output impedance Zo of the pulse generator.
CL = Load capacitance including jig and probe capacitance.
RL = Load resistance.
S1 = Test selection switch
Fig 12. Test circuit for measuring switching times
9
0
9
0
W
:
W
:
9
9
,
9
,
QHJDWLYH
SXOVH
SRVLWLYH
SXOVH
9
9
0
9
0
W
I
W
U
W
U
W
I
DDG
'87
9
&&
9
&&
9,92
57
5/6
&/
RSHQ
*
Table 9. Test data
Type Input Load S1 position
VItr, tfCLRLtPHL, tPLH
74HC165 VCC 6ns 15pF, 50 pF 1kopen
74HCT165 3V 6ns 15pF, 50 pF 1kopen
74HC_HCT165 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet Rev. 4 — 28 December 2015 14 of 21
NXP Semiconductors 74HC165; 74HCT165
8-bit parallel-in/serial out shift register
13. Package outline
Fig 13. Package outline SOT109-1 (SO16)
;
Z 0
ș
$
$
$
E
S
'
+
(
/
S
4
GHWDLO;
(
=
H
F
/
Y 0 $
$
$
\
SLQLQGH[
81,7 $
PD[ $
$
$
E
S F '
(
H +
( / /
S 4 =\ZY ș
5()(5(1&(6
287/,1(
9(56,21
(8523($1
352-(&7,21 ,668('$7(
,(& -('(& -(,7$
PP
LQFKHV
R
R
',0(16,216LQFKGLPHQVLRQVDUHGHULYHGIURPWKHRULJLQDOPPGLPHQVLRQV
1RWH
3ODVWLFRUPHWDOSURWUXVLRQVRIPPLQFKPD[LPXPSHUVLGHDUHQRWLQFOXGHG
627
( 06
PP
VFDOH
62SODVWLFVPDOORXWOLQHSDFNDJHOHDGVERG\ZLGWKPP 627
74HC_HCT165 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet Rev. 4 — 28 December 2015 15 of 21
NXP Semiconductors 74HC165; 74HCT165
8-bit parallel-in/serial out shift register
Fig 14. Package outline SOT338-1 (SSOP16)
81,7 $
$
$
E
S F '
( H +
( / /
S 4 =\ZY ș
5()(5(1&(6
287/,1(
9(56,21
(8523($1
352-(&7,21 ,668('$7(
,(& -('(& -(,7$
PP
R
R
',0(16,216PPDUHWKHRULJLQDOGLPHQVLRQV
1RWH
3ODVWLFRUPHWDOSURWUXVLRQVRIPPPD[LPXPSHUVLGHDUHQRWLQFOXGHG
627
Z 0
E
S
'
+
(
(
=
H
F
Y 0 $
;
$
\
ș
$
$
$
/
S
4
GHWDLO;
/
$
02
SLQLQGH[
PP
VFDOH
6623SODVWLFVKULQNVPDOORXWOLQHSDFNDJHOHDGVERG\ZLGWKPP 627
$
PD[
74HC_HCT165 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet Rev. 4 — 28 December 2015 16 of 21
NXP Semiconductors 74HC165; 74HCT165
8-bit parallel-in/serial out shift register
Fig 15. Package outline SOT403-1 (TSSOP16)
81,7 $
$
$
E
S F ' (
H +
( / /
S 4 =\ZY ș
5()(5(1&(6
287/,1(
9(56,21
(8523($1
352-(&7,21 ,668('$7(
,(& -('(& -(,7$
PP
R
R
',0(16,216PPDUHWKHRULJLQDOGLPHQVLRQV
1RWHV
3ODVWLFRUPHWDOSURWUXVLRQVRIPPPD[LPXPSHUVLGHDUHQRWLQFOXGHG
3ODVWLFLQWHUOHDGSURWUXVLRQVRIPPPD[LPXPSHUVLGHDUHQRWLQFOXGHG
627 02
Z 0
E
S
'
=
H
ș
$
$
$
/
S
4
GHWDLO;
/
$
+
(
(
F
Y 0 $
;
$
\
PP
VFDOH
76623SODVWLFWKLQVKULQNVPDOORXWOLQHSDFNDJHOHDGVERG\ZLGWKPP 627
$
PD[
SLQLQGH[
74HC_HCT165 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet Rev. 4 — 28 December 2015 17 of 21
NXP Semiconductors 74HC165; 74HCT165
8-bit parallel-in/serial out shift register
Fig 16. Package outline SOT763-1 (DHVQFN16)
WHUPLQDO
LQGH[DUHD
$ (K
E
81,7 \H
F
5()(5(1&(6
287/,1(
9(56,21
(8523($1
352-(&7,21 ,668('$7(
,(& -('(& -(,7$
PP
'K
\
H
',0(16,216PPDUHWKHRULJLQDOGLPHQVLRQV
627 02
/
Y
Z
PP
VFDOH
627
'+94)1SODVWLFGXDOLQOLQHFRPSDWLEOHWKHUPDOHQKDQFHGYHU\WKLQTXDGIODWSDFNDJHQROHDGV
WHUPLQDOVERG\[[PP
$
PD[
$
$
F
GHWDLO;
\
\ &
H
/
(K
'K
H
H
E
;
'
(
&
% $
WHUPLQDO
LQGH[DUHD
$&
&
%
Y 0
Z 0
(
1RWH
3ODVWLFRUPHWDOSURWUXVLRQVRIPPPD[LPXPSHUVLGHDUHQRWLQFOXGHG
'
74HC_HCT165 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet Rev. 4 — 28 December 2015 18 of 21
NXP Semiconductors 74HC165; 74HCT165
8-bit parallel-in/serial out shift register
14. Abbreviations
15. Revision history
Table 10. Ab breviations
Acronym Description
CMOS Complementary Metal-Oxide Semiconductor
DUT Device Under Test
ESD ElectroStatic Discharge
HBM Human Body Model
MM Machine Model
TTL Transistor-Transistor Logic
Table 11. Revision history
Document ID Release date Data sheet status Change notice Supersedes
74HC_HCT165 v.4 20151228 Product data sheet - 74HC_HCT165 v.3
Modifications: •Type numbers 74HC 165N and 74HCT165N (SOT38-4) removed.
74HC_HCT165 v.3 20080314 Product data sheet - 74HC_HCT165_CNV v.2
Modifications: •The format of this data sheet has been redesigned to comply with the new identity
guidelines of NXP Semiconductors.
•Legal texts have been adapted to the new company name where appropriate.
•Package SOT763-1 (DHVQFN16) added to Section 4 “Ordering information” and Section
13 “Package outline ”.
•Family data added, see Section 10 “Static characteristics”
74HC_HCT165_CNV v.2 December 1990 Product specificatio n - -
74HC_HCT165 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet Rev. 4 — 28 December 2015 19 of 21
NXP Semiconductors 74HC165; 74HCT165
8-bit parallel-in/serial out shift register
16. Legal information
16.1 Data sheet status
[1] Please consult the most recently issued document before initiating or completing a design.
[2] The term ‘short data sheet’ is explained in section “Definitions”.
[3] The product status of device (s) descri bed in this d ocument may have change d since this d ocument was p ublished and may dif fer in case of multiple devices. The latest product st atus
information is available on the Internet at URL http://www.nxp.com.
16.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liab ility for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full dat a sheet
with the same product type number(s) and tit le. A short data sh eet is intended
for quick reference only and shou ld not b e relied u pon to cont ain det ailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semicond uctors sales
office. In case of any inconsistency or conflict with the shor t data sheet, the
full data sheet shall pre va il.
Product specificat io n — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to off er functions and qualities beyond those described in the
Product data sheet.
16.3 Disclaimers
Limited warr a nty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warrant ies, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information. NXP Se miconductors takes no
responsibility for the content in this document if provided by an information
source outside of NXP Semiconductors.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequ ential damages (including - wit hout limitation - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggreg ate and cumulative liabil ity towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all informa tion supplied prior
to the publication hereof .
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in app lications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in perso nal injury, death or severe property or environmental
damage. NXP Semiconductors and its suppliers accept no liability for
inclusion and/or use of NXP Semiconducto rs products in such equipment or
applications and ther efore such inclu sion and/or use is at the cu stomer’s own
risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and ope ration of their applications
and products using NXP Semiconductors product s, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suit able and fit for t he customer’s applications and
products planned, as well as fo r the planned application and use of
customer’s third party customer(s). Custo mers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party custo mer(s). Customer is responsible for doing all necessary
testing for the customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings onl y and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individua l agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
No offer to sell or license — Nothing i n this document may be interpreted or
construed as an of fer t o sell product s that is open for accept ance or the gr ant,
conveyance or implication of any license under any copyrights, patents or
other industrial or inte llectual property rights.
Document status[1][2] Product status[3] Definition
Objective [short] data sheet Development This document contains data from the objective specif ication for product development.
Preliminary [short] dat a sheet Qualification This document contains data from the preliminary specification.
Product [short] data sheet Production This document contains the product specification.
74HC_HCT165 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet Rev. 4 — 28 December 2015 20 of 21
NXP Semiconductors 74HC165; 74HCT165
8-bit parallel-in/serial out shift register
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
Non-automotive qualified products — Unless this data sheet expressly
states that this specific NXP Semiconductors product i s automotive qualified,
the product is not suitable for automo tive use. It i s neit her qua lif ied nor test ed
in accordance with automotive testing or application requirements. NXP
Semiconductors accepts no liability for inclusion and/or use of
non-automotive qualified products in automotive equipment or applications.
In the event that customer uses the product for design-in and use in
automotive applications to automot ive specifications and standards, custome r
(a) shall use the product without NXP Semiconductors’ warranty of the
product for such au tomotive applicat ions, use and specifications, and (b)
whenever customer uses the product for automotive applications beyond
NXP Semiconductors’ specifications such use shall be solely at customer’s
own risk, and (c) customer fully indemnifies NXP Semiconduct ors for an y
liability, damages or failed product cl aims resulting from custome r design and
use of the product for automotive applications beyond NXP Semiconductors’
standard warranty and NXP Semiconductors’ product specifications.
Translations — A non-English (translated) version of a document is for
reference only. The English version shall prevail in case of any discrepancy
between the translated and English versions.
16.4 Trademarks
Notice: All referenced b rands, produc t names, service names and trademarks
are the property of their respective ow ners.
17. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
NXP Semiconductors 74HC165; 74HCT165
8-bit parallel-in/serial out shift register
© NXP Semiconductors N.V. 2015. All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 28 December 2015
Document identifier: 74HC_HCT165
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
18. Contents
1 General description. . . . . . . . . . . . . . . . . . . . . . 1
2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1
3 Applications. . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
4 Ordering information. . . . . . . . . . . . . . . . . . . . . 1
5 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2
6 Pinning information. . . . . . . . . . . . . . . . . . . . . . 3
6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3
7 Functional description . . . . . . . . . . . . . . . . . . . 4
8 Limiting values . . . . . . . . . . . . . . . . . . . . . . . . . . 5
9 Recommended operating conditions. . . . . . . . 5
10 Static characteristics. . . . . . . . . . . . . . . . . . . . . 6
11 Dynamic characteristics . . . . . . . . . . . . . . . . . . 7
12 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
13 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 14
14 Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 18
15 Revision history. . . . . . . . . . . . . . . . . . . . . . . . 18
16 Legal information. . . . . . . . . . . . . . . . . . . . . . . 19
16.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 19
16.2 Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
16.3 Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 19
16.4 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 20
17 Contact information. . . . . . . . . . . . . . . . . . . . . 20
18 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
