TC74HC573AP/AF
2014-03-01
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TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic
TC74HC573AP, TC74HC573AF
Octal D-Type Latch with 3-State Output
The TC74HC573A is a high speed CMOS OCTAL LATCH with
3-STATE OUTPUT fabricated with silicon gate C2MOS
technology.
It achieves the high speed operation similar to equivalent
LSTTL while maintaining the CMOS low power dissipation.
Its 8-bit D-type latche is controlled by a latch enable input (LE)
and an output enable input ( OE ).
When the OE input is high, the eight outputs are in a high
impedance state.
All inputs are equipped with protection circuits against static
discharge or transient excess voltage.
Features
• High speed: tpd = 13 ns (typ.) at VCC = 5 V
• Low power dissipation: ICC = 4 μA (max) at Ta = 25°C
• High noise immunity: VNIH = VNIL = 28% VCC (min)
• Output drive capability: 15 LSTTL loads
• Symmetrical output impedance: |IOH| = IOL = 6 mA (min)
• Balanced propagation delays: tpLH ∼
−
tpHL
• Wide operating voltage range: VCC (opr) = 2 to 6 V
• Pin and function compatible with 74LS573
Pin Assignment
TC74HC573AP
TC74HC573AF
Weight
DIP20-P-300-2.54A : 1.30 g (typ.)
SOP20-P-300-1.27A : 0.22 g (typ.)
Start of commercial production
1987-11
TC74HC573AP/AF
2014-03-01
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IEC Logic Symbol
Truth Table
Inputs Output
OE LE D Q
H X X HZ
L L X Qn
L H L L
L H H H
X: Don’t care
HZ: High impedance
Qn: Q outputs are latched at the time when the LE input is taken to a low logic level.
System Diagram
TC74HC573AP/AF
2014-03-01
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Absolute Maximum Ratings (Note 1)
Characteristics Symbol Rating Unit
Supply voltage range VCC −0.5 to 7 V
DC input voltage VIN −0.5 to VCC + 0.5 V
DC output voltage VOUT −0.5 to VCC + 0.5 V
Input diode current IIK ±20 mA
Output diode current IOK ±20 mA
DC output current IOUT ±35 mA
DC VCC/ground current ICC ±75 mA
Power dissipation PD 500 (DIP) (Note 2)/180 (SOP) mW
Storage temperature Tstg −65 to 150 °C
Note 1: Exceeding any of the absolute maximum ratings, even briefly, lead to deterioration in IC performance or
even destruction.
Using continuously under heavy loads (e.g. the application of high temperature/current/voltage and the
significant change in temperature, etc.) may cause this product to decrease in the reliability significantly
even if the operating conditions (i.e. operating temperature/current/voltage, etc.) are within the absolute
maximum ratings and the operating ranges.
Please design the appropriate reliability upon reviewing the Toshiba Semiconductor Reliability Handbook
(“Handling Precautions”/“Derating Concept and Methods”) and individual reliability data (i.e. reliability test
report and estimated failure rate, etc).
Note 2: 500 mW in the range of Ta = −40 to 65°C. From Ta = 65 to 85°C a derating factor of −10 mW/°C shall be
applied until 300 mW.
Operating Ranges (Note)
Characteristics Symbol Rating Unit
Supply voltage VCC 2 to 6 V
Input voltage VIN 0 to VCC V
Output voltage VOUT 0 to VCC V
Operating temperature Topr −40 to 85 °C
Input rise and fall time tr, tf
0 to 1000 (VCC = 2.0 V)
0 to 500 (VCC = 4.5 V)
0 to 400 (VCC = 6.0 V)
ns
Note: The operating ranges must be maintained to ensure the normal operation of the device.
Unused inputs must be tied to either VCC or GND.
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Electrical Characteristics
DC Characteristics
Test Condition Ta = 25°C Ta =
−40 to 85°C
Characteristics Symbol
V
CC (V) Min Typ. Max Min Max
Unit
High-level input
voltage VIH ⎯
2.0
4.5
6.0
1.50
3.15
4.20
⎯
⎯
⎯
⎯
⎯
⎯
1.50
3.15
4.20
⎯
⎯
⎯
V
Low-level input
voltage VIL ⎯
2.0
4.5
6.0
⎯
⎯
⎯
⎯
⎯
⎯
0.50
1.35
1.80
⎯
⎯
⎯
0.50
1.35
1.80
V
IOH = −20 μA
2.0
4.5
6.0
1.9
4.4
5.9
2.0
4.5
6.0
⎯
⎯
⎯
1.9
4.4
5.9
⎯
⎯
⎯
High-level output
voltage VOH VIN
= VIH or VIL
IOH = −6 mA
IOH = −7.8 mA
4.5
6.0
4.18
5.68
4.31
5.80
⎯
⎯
4.13
5.63
⎯
⎯
V
IOL = 20 μA
2.0
4.5
6.0
⎯
⎯
⎯
0.0
0.0
0.0
0.1
0.1
0.1
⎯
⎯
⎯
0.1
0.1
0.1
Low-level output
voltage VOL VIN
= VIH or VIL
IOL = 6 mA
IOL = 7.8 mA
4.5
6.0
⎯
⎯
0.17
0.18
0.26
0.26
⎯
⎯
0.33
0.33
V
3-state output
off-state current IOZ VIN = VIH or VIL
VOUT = VCC or GND 6.0 ⎯ ⎯ ±0.5 ⎯ ±5.0 μA
Input leakage
current IIN VIN = VCC or GND 6.0 ⎯ ⎯ ±0.1 ⎯ ±1.0 μA
Quiescent supply
current ICC VIN = VCC or GND 6.0 ⎯ ⎯ 4.0 ⎯ 40.0 μA
Timing Requirements (input: tr = tf = 6 ns)
Test Condition Ta = 25°C
Ta =
−40 to
85°C
Characteristics Symbol
V
CC (V) Typ. Limit Limit
Unit
Minimum pulse width
(LE)
tW (H) ⎯
2.0
4.5
6.0
⎯
⎯
⎯
75
15
13
95
19
16
ns
Minimum set-up time
(data)
ts ⎯
2.0
4.5
6.0
⎯
⎯
⎯
50
10
9
65
13
11
ns
Minimum hold time
(data)
th ⎯
2.0
4.5
6.0
⎯
⎯
⎯
5
5
5
5
5
5
ns
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AC Characteristics (input: tr = tf = 6 ns)
Test Condition Ta = 25°C Ta =
−40 to 85°C
Characteristics Symbol
CL (pF) VCC (V) Min Typ. Max Min Max
Unit
Output transition time
tTLH
tTHL ⎯ 50
2.0
4.5
6.0
⎯
⎯
⎯
20
6
5
60
12
10
⎯
⎯
⎯
75
15
13
ns
50
2.0
4.5
6.0
⎯
⎯
⎯
50
15
13
115
23
20
⎯
⎯
⎯
145
29
25
Propagation delay
time
(LE-Q)
tpLH
tpHL
⎯
150
2.0
4.5
6.0
⎯
⎯
⎯
60
20
17
155
31
26
⎯
⎯
⎯
195
39
33
ns
50
2.0
4.5
6.0
⎯
⎯
⎯
42
14
12
110
22
19
⎯
⎯
⎯
140
28
24
Propagation delay
time
(D-Q)
tpLH
tpHL
⎯
150
2.0
4.5
6.0
⎯
⎯
⎯
57
19
16
150
30
26
⎯
⎯
⎯
190
38
32
ns
50
2.0
4.5
6.0
⎯
⎯
⎯
55
17
14
140
28
24
⎯
⎯
⎯
175
35
30
Output enable time
tpZL
tpZH
RL = 1 kΩ
150
2.0
4.5
6.0
⎯
⎯
⎯
66
22
19
180
36
31
⎯
⎯
⎯
225
45
38
ns
Output disable time
tpLZ
tpHZ
RL = 1 kΩ 50
2.0
4.5
6.0
⎯
⎯
⎯
40
17
15
125
25
21
⎯
⎯
⎯
155
31
26
ns
Input capacitance CIN ⎯ ⎯ 5 10 ⎯ 10 pF
Output capacitance COUT ⎯ ⎯ 10 ⎯ ⎯ ⎯ pF
Power dissipation
capacitance
CPD
(Note) ⎯ ⎯ 51 ⎯ ⎯ ⎯ pF
Note: CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating
current consumption without load.
Average operating current can be obtained by the equation:
ICC (opr) = CPD･VCC･fIN + ICC/8 (per latch)
And the total CPD when n pcs. of latch operate can be gained by the following equation:
CPD (total) = 33 + 18･n
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Package Dimensions
Weight: 1.30 g (typ.)
TC74HC573AP/AF
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Package Dimensions
Weight: 0.22 g (typ.)
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