v2.0 IGLOO Low-Power Flash FPGAs (R) with Flash*Freeze Technology Features and Benefits * 1.2 V, 1.5 V, 1.8 V, 2.5 V, and 3.3 V Mixed-Voltage Operation * Bank-Selectable I/O Voltages--up to 4 Banks per Chip * Single-Ended I/O Standards: LVTTL, LVCMOS 3.3 V / 2.5 V / 1.8 V / 1.5 V / 1.2 V, 3.3 V PCI / 3.3 V PCI-X, and LVCMOS 2.5 V / 5.0 V Input * Differential I/O Standards: LVPECL, LVDS, B-LVDS, and MLVDS (AGL250 and above) * Wide Range Power Supply Voltage Support per JESD8-B, Allowing I/Os to Operate from 2.7 V to 3.6 V * Wide Range Power Supply Voltage Support per JESD8-12, Allowing I/Os to Operate from 1.14 V to 1.575 V * I/O Registers on Input, Output, and Enable Paths * Hot-Swappable and Cold-Sparing I/Os * Programmable Output Slew Rate and Drive Strength * Weak Pull-Up/-Down * IEEE 1149.1 (JTAG) Boundary Scan Test * Pin-Compatible Packages across the IGLOO Family Low Power * * * * * 1.2 V to 1.5 V Core Voltage Support for Low Power Supports Single-Voltage System Operation 5 W Power Consumption in Flash*Freeze Mode Low-Power Active FPGA Operation Flash*Freeze Technology Enables Ultra-Low Power Consumption while Maintaining FPGA Content * Easy Entry to / Exit from Ultra-Low-Power Flash*Freeze Mode High Capacity * 15 k to 1 Million System Gates * Up to 144 kbits of True Dual-Port SRAM * Up to 300 User I/Os Reprogrammable Flash Technology * * * * * 130-nm, 7-Layer Metal, Flash-Based CMOS Process Live-at-Power-Up (LAPU) Level 0 Support Single-Chip Solution Retains Programmed Design When Powered Off 250 MHz (1.5 V systems) and 160 MHz (1.2 V systems) System Performance In-System Programming (ISP) and Security * Secure ISP Using On-Chip 128-Bit Advanced Encryption Standard (AES) Decryption (except ARM(R)-enabled IGLOO(R) devices) via JTAG (IEEE 1532-compliant) * FlashLock(R) to Secure FPGA Contents High-Performance Routing Hierarchy Clock Conditioning Circuit (CCC) and PLL * Six CCC Blocks, One with an Integrated PLL * Configurable Phase Shift, Multiply/Divide, Delay Capabilities, and External Feedback * Wide Input Frequency Range (1.5 MHz up to 250 MHz) Embedded Memory * 1 kbit of FlashROM User Nonvolatile Memory * SRAMs and FIFOs with Variable-Aspect-Ratio 4,608-Bit RAM Blocks (x1, x2, x4, x9, and x18 organizations) * True Dual-Port SRAM (except x18) ARM Processor Support in IGLOO FPGAs * Segmented, Hierarchical Routing and Clock Structure * M1 IGLOO Devices--CortexTM-M1 Soft Processor Available with or without Debug Advanced I/O * 700 Mbps DDR, LVDS-Capable I/Os (AGL250 and above) IGLOO Product Family IGLOO Devices ARM-Enabled IGLOO Devices System Gates Typical Equivalent Macrocells VersaTiles (D-flip-flops) Flash*Freeze Mode (typical, W) RAM kbits (1,024 bits) 4,608-Bit Blocks FlashROM Bits Secure (AES) ISP 1 Integrated PLL in CCCs 2 VersaNet Globals 3 I/O Banks Maximum User I/Os Package Pins UC/CS QFN VQFP FBGA AGL015 AGL030 AGL060 AGL125 15 k 128 384 5 30 k 256 768 5 60 k 512 1,536 10 125 k 1,024 3,072 16 AGL250 M1AGL250 250 k 2,048 6,144 24 - - 1k - - 6 2 49 - - 1k - - 6 2 81 18 4 1k Yes 1 18 2 96 36 8 1k Yes 1 18 2 133 36 8 1k Yes 1 18 4 143 UC81/CS81 QN48, QN68, QN132 VQ100 CS121 QN132 CS196 QN132 CS196 4 QN132 4,5 VQ100 FG144 5 VQ100 FG144 VQ100 FG144 QN68 AGL400 400 k - 9,216 32 54 12 1k Yes 1 18 4 194 AGL600 AGL1000 M1AGL600 M1AGL1000 600 k 1M - - 13,824 24,576 36 53 108 24 1k Yes 1 18 4 235 144 32 1k Yes 1 18 4 300 CS196 CS281 CS281 FG144, FG256, FG484 FG144, FG256, FG484 FG144, FG256, FG484 Notes: 1. AES is not available for ARM-enabled IGLOO devices. 2. 3. 4. 5. 6. AGL060 in CS121 does not support the PLL. Six chip (main) and twelve quadrant global networks are available for AGL060 and above. The M1AGL250 device does not support this package. Device/package support TBD The IGLOOe handbook provides information on higher densities and additional features. AGL015 and AGL030 devices do not support this feature. November 2009 (c) 2009 Actel Corporation Supported only by AGL015 and AGL030 devices. I IGLOO Low-Power Flash FPGAs I/Os Per Package1 IGLOO Devices AGL015 AGL030 AGL060 AGL125 ARM-Enabled IGLOO Devices AGL250 AGL400 AGL600 AGL1000 M1AGL250 3 M1AGL400 M1AGL600 M1AGL1000 Package Single-Ended I/O Single-Ended I/O Single-Ended I/O Single-Ended I/O Single-Ended I/O 2 Differential I/O Pairs Single-Ended I/O 2 Differential I/O Pairs Single-Ended I/O 2 Differential I/O Pairs Single-Ended I/O 2 Differential I/O Pairs I/O Type QN48 - 34 - - - - - - - - - - QN68 49 49 - - - - - - - - - - UC81 - 66 - - - - - - - - - - CS81 - 66 - - - - - - - - - - CS121 - - 96 - - - - - - - - - VQ100 - 77 71 71 68 - - - - - - - - - - - - QN132 - CS196 - FG144 - FG256 - CS281 FG484 81 13 7 19 7 80 84 87 - - 133 143 35 143 35 - - - - - 96 7 97 97 24 97 25 97 25 97 25 - - - - - 178 38 177 43 177 44 - - - - - - - - 215 53 215 53 - - - - - - 194 38 235 60 300 74 Notes: 1. When considering migrating your design to a lower- or higher-density device, refer to the IGLOO Low-Power Flash FPGAs handbook to ensure compliance with design and board migration requirements. 2. Each used differential I/O pair reduces the number of single-ended I/Os available by two. 3. The M1AGL250 device does not support QN132 or CS196 packages. Refer to the IGLOO Low-Power Flash FPGAs handbook for position assignments of the 15 LVPECL pairs. 4. FG256 and FG484 are footprint-compatible packages. 5. When the Flash*Freeze pin is used to directly enable Flash*Freeze mode and not used as a regular I/O, the number of single-ended user I/Os available is reduced by one. 6. "G" indicates RoHS-compliant packages. Refer to "IGLOO Ordering Information" on page III for the location of the "G" in the part number. 7. Device/package support TBD. IGLOO FPGAs Package Sizes Dimensions Package Length x (mm\mm) UC81 CS81 CS121 QN68 QN132 CS196 CS281 FG144 VQ100 FG256 FG484 Width 4 x 4 5x5 6x6 8x8 8x8 8x8 10 x 10 13 x 13 14 x 14 17 x 17 23 x 23 Nominal Area (mm2) 16 25 36 64 64 64 100 169 196 289 529 Pitch (mm) 0.4 0.5 0.5 0.4 0.5 0.5 0.5 1.0 0.5 1.0 1.0 Height (mm) 0.80 0.80 0.99 0.90 0.75 1.20 1.05 1.45 1.00 1.60 2.23 II v2.0 IGLOO Low-Power Flash FPGAs IGLOO Ordering Information AGL1000 V2 _ G FG 144 I Application (Temperature Range) Blank = Commercial (0C to +70C Ambient Temperature) I = Industrial (-40C to +85C Ambient Temperature) PP = Pre-Production ES = Engineering Sample (Room Temperature Only) Package Lead Count Lead-Free Packaging Blank = Standard Packaging G= RoHS-Compliant Packaging (some packages also halogen-free) Package Type UC = Micro Chip Scale Package (0.4 mm pitch) CS = Chip Scale Package (0.4 mm and 0.5 mm pitches) QN = Quad Flat Pack No Leads (0.4 mm and 0.5 mm pitch) VQ = Very Thin Quad Flat Pack (0.5 mm pitch) FG = Fine Pitch Ball Grid Array (1.0 mm pitch) Supply Voltage 2 = 1.2 V to 1.5 V 5 = 1.5 V only Part Number IGLOO Devices AGL015 = 15,000 System Gates AGL030 = 30,000 System Gates AGL060 = 60,000 System Gates AGL125 = 125,000 System Gates AGL250 = 250,000 System Gates AGL400 = 400,000 System Gates AGL600 = 600,000 System Gates AGL1000 = 1,000,000 System Gates IGLOO Devices with Cortex-M1 M1AGL250 = 250,000 System Gates M1AGL600 = 600,000 System Gates M1AGL1000= 1,000,000 System Gates Note: Marking Information: IGLOO V2 devices do not have V2 marking, but IGLOO V5 devices are marked accordingly. v2.0 III IGLOO Low-Power Flash FPGAs Temperature Grade Offerings AGL015 AGL030 AGL060 AGL125 AGL250 AGL400 M1AGL250 4 Package AGL600 AGL1000 M1AGL600 M1AGL1000 QN48 - C, I - - - - - - QN68 C, I - - - - - - - UC81 - C, I - - - - - - CS81 - C, I - - - - - - CS121 - - C, I - - - - - VQ100 - C, I C, I C, I C, I - - - - - - QN132 - C, I CS196 - - C, I 3 - C, I3 C, I C, I 3 C, I C, I C, I - - C, I C, I C, I C, I C, I FG144 - - FG256 - - - - - C, I C, I C, I CS281 - - - - - - C, I C, I FG484 - - - - - C, I C, I C, I Notes: 1. C = Commercial temperature range: 0C to 70C ambient temperature. 2. I = Industrial temperature range: -40C to 85C ambient temperature. 3. Device/package support TBD. 4. The M1AGL250 device does not support FG256 or QN132 packages. References made to IGLOO devices also apply to ARM-enabled IGLOOe devices. The ARM-enabled part numbers start with M1 (Cortex-M1). Contact your local Actel representative for device availability: http://www.actel.com/contact/default.aspx. AGL015 and AGL030 The AGL015 and AGL030 are architecturally compatible; there are no RAM or PLL features. IV v2.0 1 - IGLOO Device Family Overview General Description The IGLOO family of flash FPGAs, based on a 130-nm flash process, offers the lowest power FPGA, a single-chip solution, small footprint packages, reprogrammability, and an abundance of advanced features. The Flash*Freeze technology used in IGLOO devices enables entering and exiting an ultra-lowpower mode that consumes as little as 5 W while retaining SRAM and register data. Flash*Freeze technology simplifies power management through I/O and clock management with rapid recovery to operation mode. The Low Power Active capability (static idle) allows for ultra-low-power consumption (from 12 W) while the IGLOO device is completely functional in the system. This allows the IGLOO device to control system power management based on external inputs (e.g., scanning for keyboard stimulus) while consuming minimal power. Nonvolatile flash technology gives IGLOO devices the advantage of being a secure, low power, single-chip solution that is live at power-up (LAPU). IGLOO is reprogrammable and offers time-tomarket benefits at an ASIC-level unit cost. These features enable designers to create high-density systems using existing ASIC or FPGA design flows and tools. IGLOO devices offer 1 kbit of on-chip, reprogrammable, nonvolatile FlashROM storage as well as clock conditioning circuitry based on an integrated phase-locked loop (PLL). The AGL015 and AGL030 devices have no PLL or RAM support. IGLOO devices have up to 1 million system gates, supported with up to 144 kbits of true dual-port SRAM and up to 300 user I/Os. M1 IGLOO devices support the high-performance, 32-bit Cortex-M1 processor developed by ARM for implementation in FPGAs. Cortex-M1 is a soft processor that is fully implemented in the FPGA fabric. It has a three-stage pipeline that offers a good balance between low-power consumption and speed when implemented in an M1 IGLOO device. The processor runs the ARMv6-M instruction set, has a configurable nested interrupt controller, and can be implemented with or without the debug block. Cortex-M1 is available for free from Actel for use in M1 IGLOO FPGAs. The ARM-enabled devices have Actel ordering numbers that begin with M1AGL and do not support AES decryption. Flash*Freeze Technology The IGLOO device offers unique Flash*Freeze technology, allowing the device to enter and exit ultra-low-power Flash*Freeze mode. IGLOO devices do not need additional components to turn off I/Os or clocks while retaining the design information, SRAM content, and registers. Flash*Freeze technology is combined with in-system programmability, which enables users to quickly and easily upgrade and update their designs in the final stages of manufacturing or in the field. The ability of IGLOO V2 devices to support a wide range of core voltage (1.2 V to 1.5 V) allows further reduction in power consumption, thus achieving the lowest total system power. When the IGLOO device enters Flash*Freeze mode, the device automatically shuts off the clocks and inputs to the FPGA core; when the device exits Flash*Freeze mode, all activity resumes and data is retained. The availability of low-power modes, combined with reprogrammability, a single-chip and singlevoltage solution, and availability of small-footprint, high pin-count packages, make IGLOO devices the best fit for portable electronics. v2.0 1-1 IGLOO Device Family Overview Flash Advantages Low Power Flash-based IGLOO devices exhibit power characteristics similar to those of an ASIC, making them an ideal choice for power-sensitive applications. IGLOO devices have only a very limited power-on current surge and no high-current transition period, both of which occur on many FPGAs. IGLOO devices also have low dynamic power consumption to further maximize power savings; power is even further reduced by the use of a 1.2 V core voltage. Low dynamic power consumption, combined with low static power consumption and Flash*Freeze technology, gives the IGLOO device the lowest total system power offered by any FPGA. Security The nonvolatile, flash-based IGLOO devices do not require a boot PROM, so there is no vulnerable external bitstream that can be easily copied. IGLOO devices incorporate FlashLock, which provides a unique combination of reprogrammability and design security without external overhead, advantages that only an FPGA with nonvolatile flash programming can offer. IGLOO devices utilize a 128-bit flash-based lock and a separate AES key to secure programmed intellectual property and configuration data. In addition, all FlashROM data in IGLOO devices can be encrypted prior to loading, using the industry-leading AES-128 (FIPS192) bit block cipher encryption standard. AES was adopted by the National Institute of Standards and Technology (NIST) in 2000 and replaces the 1977 DES standard. IGLOO devices have a built-in AES decryption engine and a flash-based AES key that make them the most comprehensive programmable logic device security solution available today. IGLOO devices with AES-based security allow for secure, remote field updates over public networks such as the Internet, and ensure that valuable IP remains out of the hands of system overbuilders, system cloners, and IP thieves. The contents of a programmed IGLOO device cannot be read back, although secure design verification is possible. Security, built into the FPGA fabric, is an inherent component of the IGLOO family. The flash cells are located beneath seven metal layers, and many device design and layout techniques have been used to make invasive attacks extremely difficult. The IGLOO family, with FlashLock and AES security, is unique in being highly resistant to both invasive and noninvasive attacks. Your valuable IP is protected and secure, making remote ISP possible. An IGLOO device provides the most impenetrable security for programmable logic designs. Single Chip Flash-based FPGAs store their configuration information in on-chip flash cells. Once programmed, the configuration data is an inherent part of the FPGA structure, and no external configuration data needs to be loaded at system power-up (unlike SRAM-based FPGAs). Therefore, flash-based IGLOO FPGAs do not require system configuration components such as EEPROMs or microcontrollers to load device configuration data. This reduces bill-of-materials costs and PCB area, and increases security and system reliability. Live at Power-Up The Actel flash-based IGLOO devices support Level 0 of the LAPU classification standard. This feature helps in system component initialization, execution of critical tasks before the processor wakes up, setup and configuration of memory blocks, clock generation, and bus activity management. The LAPU feature of flash-based IGLOO devices greatly simplifies total system design and reduces total system cost, often eliminating the need for CPLDs and clock generation PLLs. In addition, glitches and brownouts in system power will not corrupt the IGLOO device's flash configuration, and unlike SRAM-based FPGAs, the device will not have to be reloaded when system power is restored. This enables the reduction or complete removal of the configuration PROM, expensive voltage monitor, brownout detection, and clock generator devices from the PCB design. Flash-based IGLOO devices simplify total system design and reduce cost and design risk while increasing system reliability and improving system initialization time. IGLOO flash FPGAs allow the user to quickly enter and exit Flash*Freeze mode. This is done almost instantly (within 1 s) and the device retains configuration and data in registers and RAM. Unlike SRAM-based FPGAs the device does not need to reload configuration and design state from 1 -2 v2.0 IGLOO Low-Power Flash FPGAs external memory components; instead it retains all necessary information to resume operation immediately. Reduced Cost of Ownership Advantages to the designer extend beyond low unit cost, performance, and ease of use. Unlike SRAM-based FPGAs, Flash-based IGLOO devices allow all functionality to be live at power-up; no external boot PROM is required. On-board security mechanisms prevent access to all the programming information and enable secure remote updates of the FPGA logic. Designers can perform secure remote in-system reprogramming to support future design iterations and field upgrades with confidence that valuable intellectual property cannot be compromised or copied. Secure ISP can be performed using the industry-standard AES algorithm. The IGLOO family device architecture mitigates the need for ASIC migration at higher user volumes. This makes the IGLOO family a cost-effective ASIC replacement solution, especially for applications in the consumer, networking/communications, computing, and avionics markets. Firm-Error Immunity Firm errors occur most commonly when high-energy neutrons, generated in the upper atmosphere, strike a configuration cell of an SRAM FPGA. The energy of the collision can change the state of the configuration cell and thus change the logic, routing, or I/O behavior in an unpredictable way. These errors are impossible to prevent in SRAM FPGAs. The consequence of this type of error can be a complete system failure. Firm errors do not exist in the configuration memory of IGLOO flashbased FPGAs. Once it is programmed, the flash cell configuration element of IGLOO FPGAs cannot be altered by high-energy neutrons and is therefore immune to them. Recoverable (or soft) errors occur in the user data SRAM of all FPGA devices. These can easily be mitigated by using error detection and correction (EDAC) circuitry built into the FPGA fabric. Advanced Flash Technology The IGLOO family offers many benefits, including nonvolatility and reprogrammability, through an advanced flash-based, 130-nm LVCMOS process with seven layers of metal. Standard CMOS design techniques are used to implement logic and control functions. The combination of fine granularity, enhanced flexible routing resources, and abundant flash switches allows for very high logic utilization without compromising device routability or performance. Logic functions within the device are interconnected through a four-level routing hierarchy. IGLOO family FPGAs utilize design and process techniques to minimize power consumption in all modes of operation. Advanced Architecture The proprietary IGLOO architecture provides granularity comparable to standard-cell ASICs. The IGLOO device consists of five distinct and programmable architectural features (Figure 1-1 on page 1-4 and Figure 1-2 on page 1-4): * Flash*Freeze technology * FPGA VersaTiles * Dedicated FlashROM * Dedicated SRAM/FIFO memory * Extensive CCCs and PLLs * Advanced I/O structure The FPGA core consists of a sea of VersaTiles. Each VersaTile can be configured as a three-input logic function, a D-flip-flop (with or without enable), or a latch by programming the appropriate flash switch interconnections. The versatility of the IGLOO core tile as either a three-input lookup table (LUT) equivalent or a D-flip-flop/latch with enable allows for efficient use of the FPGA fabric. The VersaTile capability is unique to the Actel ProASIC(R) family of third-generation-architecture flash FPGAs. VersaTiles are connected with any of the four levels of routing hierarchy. Flash switches are distributed throughout the device to provide nonvolatile, reconfigurable interconnect programming. Maximum core utilization is possible for virtually any design. The AGL015 and AGL030 do not support PLL or SRAM. v2.0 1-3 IGLOO Device Family Overview In addition, extensive on-chip programming circuitry allows for rapid, single-voltage (3.3 V) programming of IGLOO devices via an IEEE 1532 JTAG interface. Bank 0 Bank 0 Bank 1 CCC RAM Block 4,608-Bit Dual-Port SRAM or FIFO Block* I/Os ISP AES Decryption* User Nonvolatile FlashRom Flash*Freeze Technology Charge Pumps Bank 0 Bank 1 VersaTile Bank 1 * Not supported by AGL015 and AGL030 devices Figure 1-1 * IGLOO Device Architecture Overview with Two I/O Banks (AGL015, AGL030, AGL060, and AGL125) Bank 0 Bank 1 Bank 3 CCC RAM Block 4,608-Bit Dual-Port SRAM or FIFO Block I/Os VersaTile Bank 3 Bank 1 ISP AES Decryption* User Nonvolatile FlashRom Flash*Freeze Technology Charge Pumps RAM Block 4,608-Bit Dual-Port SRAM or FIFO Block (AGL600 and AGL1000) Bank 2 Figure 1-2 * IGLOO Device Architecture Overview with Four I/O Banks (AGL250, AGL600, AGL400, and AGL1000) 1 -4 v2.0 IGLOO Low-Power Flash FPGAs Flash*Freeze Technology The IGLOO device has an ultra-low power static mode, called Flash*Freeze mode, which retains all SRAM and register information and can still quickly return to normal operation. Flash*Freeze technology enables the user to quickly (within 1 s) enter and exit Flash*Freeze mode by activating the Flash*Freeze pin while all power supplies are kept at their original values. In addition, I/Os and global I/Os can still be driven and can be toggling without impact on power consumption, clocks can still be driven or can be toggling without impact on power consumption, and the device retains all core registers, SRAM information, and states. I/O states are tristated during Flash*Freeze mode or can be set to a certain state using weak pull-up or pull-down I/O attribute configuration. No power is consumed by the I/O banks, clocks, JTAG pins, or PLL, and the device consumes as little as 5 W in this mode. Flash*Freeze technology allows the user to switch to active mode on demand, thus simplifying the power management of the device. The Flash*Freeze pin (active low) can be routed internally to the core to allow the user's logic to decide when it is safe to transition to this mode. It is also possible to use the Flash*Freeze pin as a regular I/O if Flash*Freeze mode usage is not planned, which is advantageous because of the inherent low power static (as low as 12 W) and dynamic capabilities of the IGLOO device. Refer to Figure 1-3 for an illustration of entering/exiting Flash*Freeze mode. Actel IGLOO FPGA Flash*Freeze Mode Control Flash*Freeze Pin Figure 1-3 * IGLOO Flash*Freeze Mode VersaTiles The IGLOO core consists of VersaTiles, which have been enhanced beyond the ProASICPLUS(R) core tiles. The IGLOO VersaTile supports the following: * All 3-input logic functions--LUT-3 equivalent * Latch with clear or set * D-flip-flop with clear or set * Enable D-flip-flop with clear or set Refer to Figure 1-4 for VersaTile configurations. LUT-3 Equivalent X1 X2 X3 LUT-3 Y D-Flip-Flop with Clear or Set Data CLK CLR Y Enable D-Flip-Flop with Clear or Set Data CLK D-FF Y D-FF Enable CLR Figure 1-4 * VersaTile Configurations v2.0 1-5 IGLOO Device Family Overview User Nonvolatile FlashROM Actel IGLOO devices have 1 kbit of on-chip, user-accessible, nonvolatile FlashROM. The FlashROM can be used in diverse system applications: * Internet protocol addressing (wireless or fixed) * System calibration settings * Device serialization and/or inventory control * Subscription-based business models (for example, set-top boxes) * Secure key storage for secure communications algorithms * Asset management/tracking * Date stamping * Version management The FlashROM is written using the standard IGLOO IEEE 1532 JTAG programming interface. The core can be individually programmed (erased and written), and on-chip AES decryption can be used selectively to securely load data over public networks (except in the AGL015 and AGL030 devices), as in security keys stored in the FlashROM for a user design. The FlashROM can be programmed via the JTAG programming interface, and its contents can be read back either through the JTAG programming interface or via direct FPGA core addressing. Note that the FlashROM can only be programmed from the JTAG interface and cannot be programmed from the internal logic array. The FlashROM is programmed as 8 banks of 128 bits; however, reading is performed on a byte-bybyte basis using a synchronous interface. A 7-bit address from the FPGA core defines which of the 8 banks and which of the 16 bytes within that bank are being read. The three most significant bits (MSBs) of the FlashROM address determine the bank, and the four least significant bits (LSBs) of the FlashROM address define the byte. The Actel IGLOO development software solutions, Libero(R) Integrated Design Environment (IDE) and Designer, have extensive support for the FlashROM. One such feature is auto-generation of sequential programming files for applications requiring a unique serial number in each part. Another feature allows the inclusion of static data for system version control. Data for the FlashROM can be generated quickly and easily using Actel Libero IDE and Designer software tools. Comprehensive programming file support is also included to allow for easy programming of large numbers of parts with differing FlashROM contents. SRAM and FIFO IGLOO devices (except the AGL015 and AGL030 devices) have embedded SRAM blocks along their north and south sides. Each variable-aspect-ratio SRAM block is 4,608 bits in size. Available memory configurations are 256x18, 512x9, 1kx4, 2kx2, and 4kx1 bits. The individual blocks have independent read and write ports that can be configured with different bit widths on each port. For example, data can be sent through a 4-bit port and read as a single bitstream. The embedded SRAM blocks can be initialized via the device JTAG port (ROM emulation mode) using the UJTAG macro (except in the AGL015 and AGL030 devices). In addition, every SRAM block has an embedded FIFO control unit. The control unit allows the SRAM block to be configured as a synchronous FIFO without using additional core VersaTiles. The FIFO width and depth are programmable. The FIFO also features programmable Almost Empty (AEMPTY) and Almost Full (AFULL) flags in addition to the normal Empty and Full flags. The embedded FIFO control unit contains the counters necessary for generation of the read and write address pointers. The embedded SRAM/FIFO blocks can be cascaded to create larger configurations. PLL and CCC IGLOO devices provide designers with very flexible clock conditioning circuit (CCC) capabilities. Each member of the IGLOO family contains six CCCs. One CCC (center west side) has a PLL. The AGL015 and AGL030 do not have a PLL. The six CCC blocks are located at the four corners and the centers of the east and west sides. One CCC (center west side) has a PLL. 1 -6 v2.0 IGLOO Low-Power Flash FPGAs All six CCC blocks are usable; the four corner CCCs and the east CCC allow simple clock delay operations as well as clock spine access. The inputs of the six CCC blocks are accessible from the FPGA core or from one of several inputs located near the CCC that have dedicated connections to the CCC block. The CCC block has these key features: * Wide input frequency range (fIN_CCC) = 1.5 MHz up to 250 MHz * Output frequency range (fOUT_CCC) = 0.75 MHz up to 250 MHz * 2 programmable delay types for clock skew minimization * Clock frequency synthesis (for PLL only) Additional CCC specifications: * Internal phase shift = 0, 90, 180, and 270. Output phase shift depends on the output divider configuration (for PLL only). * Output duty cycle = 50% 1.5% or better (for PLL only) * Low output jitter: worst case < 2.5% x clock period peak-to-peak period jitter when single global network used (for PLL only) * Maximum acquisition time is 300 s (for PLL only) * Exceptional tolerance to input period jitter--allowable input jitter is up to 1.5 ns (for PLL only) * Four precise phases; maximum misalignment between adjacent phases of 40 ps x 250 MHz / fOUT_CCC (for PLL only) Global Clocking IGLOO devices have extensive support for multiple clocking domains. In addition to the CCC and PLL support described above, there is a comprehensive global clock distribution network. Each VersaTile input and output port has access to nine VersaNets: six chip (main) and three quadrant global networks. The VersaNets can be driven by the CCC or directly accessed from the core via multiplexers (MUXes). The VersaNets can be used to distribute low-skew clock signals or for rapid distribution of high-fanout nets. I/Os with Advanced I/O Standards The IGLOO family of FPGAs features a flexible I/O structure, supporting a range of voltages (1.2 V, 1.5 V, 1.8 V, 2.5 V, 3.0 V wide range, and 3.3 V). IGLOO FPGAs support many different I/O standards--single-ended and differential. The I/Os are organized into banks, with two or four banks per device. The configuration of these banks determines the I/O standards supported (Table 1-1). Table 1-1 * I/O Standards Supported I/O Standards Supported LVTTL/ LVCMOS PCI/PCI-X LVPECL, LVDS, B-LVDS, M-LVDS East and west banks of AGL250 and larger devices Standard Plus North and south banks of AGL250 and larger devices Not supported Not supported Not supported I/O Bank Type Advanced Device and Bank Location All banks of AGL060 and AGL125K Standard All banks of AGL015 and AGL030 v2.0 1-7 IGLOO Device Family Overview Each I/O module contains several input, output, and enable registers. These registers allow the implementation of the following: * Single-Data-Rate applications * Double-Data-Rate applications--DDR LVDS, B-LVDS, and M-LVDS I/Os for point-to-point communications IGLOO banks for the AGL250 device and above support LVPECL, LVDS, B-LVDS, and M-LVDS. B-LVDS and M-LVDS can support up to 20 loads. Hot-swap (also called hot-plug, or hot-insertion) is the operation of hot-insertion or hot-removal of a card in a powered-up system. Cold-sparing (also called cold-swap) refers to the ability of a device to leave system data undisturbed when the system is powered up, while the component itself is powered down, or when power supplies are floating. Wide Range I/O Support Actel IGLOO devices support JEDEC-defined wide range I/O operation. IGLOO devices support both the JESD8-B specification, covering 3 V and 3.3 V supplies, for an effective operating range of 2.7 V to 3.6 V, and JESD8-12 with its 1.2 V nominal, supporting an effective operating range of 1.14 V to 1.575 V. Wider I/O range means designers can eliminate power supplies or power conditioning components from the board or move to less costly components with greater tolerances. Wide range eases I/O bank management and provides enhanced protection from system voltage spikes, while providing the flexibility to easily run custom voltage applications. Part Number and Revision Date Part Number 51700095-001-10 Revised November 2009 List of Changes The following table lists critical changes that were made in the current version of the document. Previous Version Changes in Current Version (v2.0) v1.6 The version changed to v2.0 for IGLOO datasheet chapters, indicating the (September 2009) datasheet contains information based on final characterization. v1.5 (April 2009) The "Reprogrammable Flash Technology" section was modified to add "250 MHz v1.3 (December 2008) 1 -8 N/A I (1.5 V systems) and 160 MHz (1.2 V systems) System Performance." "IGLOO Ordering Information" was revised to note that halogen-free packages are available with RoHS-compliant packaging. v1.4 (February 2009) Page III Table 1-1 * I/O Standards Supported is new. 1-7 The definitions of hot-swap and cold-sparing were added to the "I/Os with Advanced I/O Standards" section. 1-7 M1AGL400 is no longer offered and was removed from the "IGLOO Product Family" table, "IGLOO Ordering Information", and "Temperature Grade Offerings". I, III, IV The -F speed grade is no longer offered for IGLOO devices. The speed grade column and note regarding -F speed grade were removed from "IGLOO Ordering Information". The "Speed Grade and Temperature Grade Matrix" section was removed. III, IV The "Advanced I/O" section was revised to include two bullets regarding wide range power supply voltage support. I v2.0 IGLOO Low-Power Flash FPGAs Previous Version v1.2 (October 2008) Changes in Current Version (v2.0) Page 3.0 V wide range was added to the list of supported voltages in the "I/Os with Advanced I/O Standards" section. The "Wide Range I/O Support" section is new. 1-8 QN48 and QN68 were added to the AGL030 for the following tables: N/A "IGLOO Product Family" "IGLOO Ordering Information" "Temperature Grade Offerings" QN132 is fully supported by AGL125 so footnote 3 was removed. v1.1 (July 2008) This document was updated to include AGL400 device information. The following sections were updated: N/A "IGLOO Product Family" "IGLOO Ordering Information" "Temperature Grade Offerings" "IGLOO Product Family" Figure 1-2 * IGLOO Device Architecture Overview with Four I/O Banks (AGL250, AGL600, AGL400, and AGL1000) v1.0 (March 2008) As a result of the Libero IDE v8.4 release, Actel now offers a wide range of core voltage support. The document was updated to change 1.2 V / 1.5 V to 1.2 V to 1.5 V. N/A 51700095-001-3 (March 2008) This document was divided into two sections and given a version number, starting at v1.0. The first section of the document includes features, benefits, ordering information, and temperature and speed grade offerings. The second section is a device family overview. N/A 51700095-001-2 (February 2008) The "Low Power" section was updated to change "1.2 V and 1.5 V Core Voltage" to "1.2 V and 1.5 V Core and I/O Voltage." The text "(from 12 W)" was removed from "Low-Power Active FPGA Operation." I 1.2_V was added to the list of core and I/O voltages in the "Advanced I/O" and "I/Os with Advanced I/O Standards" sections. The "Embedded Memory" section was updated to remove the footnote reference from the section heading and place it instead after "4,608-Bit" and I, 1-7 I "True Dual-Port SRAM (except x18)." 51700095-001-1 (January 2008) This document was updated to include AGL015 device information. QN68 is a new package that was added because it is offered in the AGL015. The following sections were updated: N/A "Features and Benefits" "IGLOO Ordering Information" "Temperature Grade Offerings" "IGLOO Product Family" "IGLOO FPGAs Package Sizes Dimensions" "AGL015 and AGL030" note "IGLOO Device Family Overview" 51700095-001-0 (January 2008) The "Temperature Grade Offerings" table was updated to include M1AGL600. IV In the "IGLOO Ordering Information" table, the QN package measurements were updated to include both 0.4 mm and 0.5 mm. III In the "General Description" section, the number of I/Os was updated from 288 to 300. 1-5 The "Low Power" section was updated to change the description of low-power I, 1-1, 1-5 active FPGA operation to "from 12 W" from "from 25 W." The same update was made in the "General Description" section and the "Flash*Freeze Technology" section. v2.0 1-9 IGLOO Device Family Overview Previous Version Changes in Current Version (v2.0) Page Advance v0.7 (November 2007) This document was previously in datasheet Advance v0.7. As a result of moving to the handbook format, Actel has restarted the version numbers. The new version number is 51700095-001-0. N/A Advance v0.6 (November 2007) Table 1 * IGLOO Product Family, the "I/Os Per Package1" table, and the Temperature Grade Offerings table were updated to reflect the following: CS196 is now supported for AGL250; device/package support for QN132 is to be determined for AGL250; the CS281 package was added for AGL600 and AGL1000. i, ii, iv Table 2 * IGLOO FPGAs Package Sizes Dimensions is new, and package sizes were removed from the "I/Os Per Package1" table. ii The "I/Os Per Package1"table was updated to reflect 77 instead of 79 singleended I/Os for the VG100 package for AGL030. ii A note was added to "IGLOO Ordering Information" regarding marking information. iii Advance v0.6 (November 2007) Advance v0.5 Table 1 * IGLOO Product Family, the "I/Os Per Package1" table, and the "IGLOO i, ii, iii, iv (September 2007) Ordering Information", and the Temperature Grade Offerings table were updated to add the UC81 package. Advance v0.4 Table 1 * IGLOO Product Family was updated for AGL030 in the Package Pins (September 2007) section to change CS181 to CS81. Advance v0.3 (August 2007) i Cortex-M1 device information was added to Table 1 * IGLOO Product Family, i, ii, iii, iv the "I/Os Per Package1" table, "IGLOO Ordering Information", and Temperature Grade Offerings. The number of single-ended I/Os for the CS81 package for AGL030 was updated to 66 in the "I/Os Per Package1" table. ii In Table 1 * IGLOO Product Family, the CS81 package was added for AGL030. The CS196 was replaced by the CS121 for AGL060. Table note 3 was moved to the specific packages to which it applies for AGL060: QN132 and FG144. i The CS81 and CS121 packages were added to the "I/Os Per Package1" table. The number of single-ended I/Os was removed for the CS196 package in AGL060. Table note 6 was moved to the specific packages to which it applies for AGL060: QN132 and FG144. ii Advance v0.2 (continued) The CS81 and CS121 packages were added to the Temperature Grade Offerings table. The temperature grade offerings were removed for the CS196 package in AGL060. Table note 3 was moved to the specific packages to which it applies for AGL060: QN132 and FG144. iv Advance v0.1 The words "ambient temperature" were added to the temperature range in the "IGLOO Ordering Information", Temperature Grade Offerings, and "Speed Grade and Temperature Grade Matrix" sections. iii, iv Advance v0.2 (July 2007) 1 -1 0 v2.0 IGLOO Low-Power Flash FPGAs Datasheet Categories Categories In order to provide the latest information to designers, some datasheets are published before data has been fully characterized. Datasheets are designated as "Product Brief," "Advance," "Preliminary," and "Production." The definitions of these categories are as follows: Product Brief The product brief is a summarized version of a datasheet (advance or production) and contains general product information. This document gives an overview of specific device and family information. Advance This version contains initial estimated information based on simulation, other products, devices, or speed grades. This information can be used as estimates, but not for production. This label only applies to the DC and Switching Characteristics chapter of the datasheet and will only be used when the data has not been fully characterized. Preliminary The datasheet contains information based on simulation and/or initial characterization. The information is believed to be correct, but changes are possible. Unmarked (production) This version contains information that is considered to be final. Export Administration Regulations (EAR) The products described in this document are subject to the Export Administration Regulations (EAR). They could require an approved export license prior to export from the United States. An export includes release of product or disclosure of technology to a foreign national inside or outside the United States. Actel Safety Critical, Life Support, and High-Reliability Applications Policy The Actel products described in this advance status document may not have completed Actel's qualification process. Actel may amend or enhance products during the product introduction and qualification process, resulting in changes in device functionality or performance. It is the responsibility of each customer to ensure the fitness of any Actel product (but especially a new product) for a particular purpose, including appropriateness for safety-critical, life-support, and other high-reliability applications. Consult Actel's Terms and Conditions for specific liability exclusions relating to life-support applications. A reliability report covering all of Actel's products is available on the Actel website at http://www.actel.com/documents/ORT_Report.pdf. Actel also offers a variety of enhanced qualification and lot acceptance screening procedures. Contact your local Actel sales office for additional reliability information. v2.0 1 - 11 Actel, IGLOO, Actel Fusion, ProASIC, Libero, Pigeon Point and the associated logos are trademarks or registered trademarks of Actel Corporation. All other trademarks and service marks are the property of their respective owners. Actel is the leader in low-power and mixed-signal FPGAs and offers the most comprehensive portfolio of system and power management solutions. Power Matters. Learn more at www.actel.com. Actel Corporation Actel Europe Ltd. Actel Japan Actel Hong Kong 2061 Stierlin Court Mountain View, CA 94043-4655 USA Phone 650.318.4200 Fax 650.318.4600 River Court,Meadows Business Park Station Approach, Blackwater Camberley Surrey GU17 9AB United Kingdom Phone +44 (0) 1276 609 300 Fax +44 (0) 1276 607 540 EXOS Ebisu Buillding 4F 1-24-14 Ebisu Shibuya-ku Tokyo 150 Japan Phone +81.03.3445.7671 Fax +81.03.3445.7668 http://jp.actel.com Room 2107, China Resources Building 26 Harbour Road Wanchai, Hong Kong Phone +852 2185 6460 Fax +852 2185 6488 www.actel.com.cn 51700095-001-10/11.09