www.irf.com 16/29/99
IRFBC40AS
SMPS MOSFET
HEXFET® Power MOSFET
lSwitch Mode Power Supply ( SMPS )
lUninterruptable Power Supply
lHigh speed power switching
Benefits
Applications
lLow Gate Charge Qg results in Simple
Drive Requirement
lImproved Gate, Avalanche and dynamic
dv/dt Ruggedness
lFully Characterized Capacitance and
Avalanche Voltage and Current
l Effective Coss Specified ( See AN 1001)
VDSS Rds(on) max ID
600V 1.2Ω6.2A
Typical SMPS Topology:
l Single transistor Forward
Parameter Max. Units
ID @ TC = 25°C Continuous Drain Current, VGS @ 10V6.2
ID @ TC = 100°C Continuous Drain Current, VGS @ 10V3.9 A
IDM Pulsed Drain Current 25
PD @TC = 25°C Power Dissipation 125 W
Linear Derating Factor 1.0 W/°C
VGS Gate-to-Source Voltage ± 30 V
dv/dt Peak Diode Recovery dv/dt 6.0 V/ns
TJOperating Junction and -55 to + 150
TSTG Storage Temperature Range
Soldering Temperature, for 10 seconds 300 (1.6mm from case ) °C
Absolute Maximum Ratings
PD- 91897A
Notes through are on page 9
2
D Pak
IRFBC40AS
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Parameter Min. Typ. Max. Units Conditions
V(BR)DSS Drain-to-Source Breakdown Voltage 600 ––– ––– V VGS = 0V, ID = 250µA
∆V(BR)DSS/∆TJ Breakdown Voltage Temp. Coefficient ––– 0.66 ––– V/°C Reference to 25°C, ID = 1mA
RDS(on) Static Drain-to-Source On-Resistance ––– ––– 1.2 ΩVGS = 10V, ID = 3.7A
VGS(th) Gate Threshold Voltage 2.0 ––– 4.0 V VDS = VGS, ID = 250µA
––– ––– 25 µA VDS = 600V, VGS = 0V
––– ––– 250 VDS = 480V, VGS = 0V, TJ = 125°C
Gate-to-Source Forward Leakage ––– ––– 100 VGS = 30V
Gate-to-Source Reverse Leakage ––– ––– -100 nA VGS = -30V
Parameter Min. Typ. Max. Units Conditions
gfs Forward Transconductance 3.4 ––– ––– S VDS = 50V, ID = 3.7A
QgTotal Gate Charge –– – –– – 42 ID = 6.2A
Qgs Gate-to-Source Charge ––– ––– 10 nC VDS = 480V
Qgd Gate-to-Drain ("Miller") Charge ––– ––– 20 VGS = 10V, See Fig. 6 and 13
td(on) Turn-On Delay Time ––– 13 ––– VDD = 300V
trRise Time ––– 23 ––– ID = 6.2A
td(off) Turn-Off Delay Time ––– 31 ––– RG = 9.1Ω
tfFall Time ––– 18 ––– RD = 47Ω,See Fig. 10
Ciss Input Capacitance ––– 1036 ––– VGS = 0V
Coss Output Capacitance ––– 136 ––– VDS = 25V
Crss Reverse Transfer Capacitance ––– 7.0 ––– pF ƒ = 1.0MHz, See Fig. 5
Coss Output Capacitance ––– 1487 ––– VGS = 0V, VDS = 1.0V, ƒ = 1.0MHz
Coss Output Capacitance ––– 36 ––– VGS = 0V, VDS = 480V, ƒ = 1.0MHz
Coss eff. Effective Output Capacitance ––– 48 ––– VGS = 0V, VDS = 0V to 480V
Dynamic @ TJ = 25°C (unless otherwise specified)
ns
Parameter Typ. Max. Units
EAS Single Pulse Avalanche Energy––– 570 mJ
IAR Avalanche Current––– 6.2 A
EAR Repetitive Avalanche Energy––– 13 mJ
Avalanche Characteristics
S
D
G
Parameter Min. Typ. Max. Units Conditions
ISContinuous Source Current MOSFET symbol
(Body Diode) ––– ––– showing the
ISM Pulsed Source Current integral reverse
(Body Diode) ––– ––– p-n junction diode.
VSD Diode Forward Voltage ––– ––– 1.5 V TJ = 25°C, IS = 6.2A, VGS = 0V
trr Reverse Recovery Time ––– 431 647 ns TJ = 25°C, IF = 6.2A
Qrr Reverse RecoveryCharge ––– 1.8 2.8 µC di/dt = 100A/µs
ton Forward Turn-On Time Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)
Diode Characteristics
6.2
25 A
Parameter Typ. Max. Units
RθJC Junction-to-Case ––– 1.0 °C/W
RθJA Junction-to-Ambient ( PCB Mounted, steady-state)* ––– 40
Thermal Resistance
Static @ TJ = 25°C (unless otherwise specified)
IGSS
IDSS Drain-to-Source Leakage Current
IRFBC40AS
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Fig 4. Normalized On-Resistance
Vs. Temperature
Fig 2. Typical Output Characteristics,
Fig 1. Typical Output Characteristics,
Fig 3. Typical Transfer Characteristics
JJ
0.01
0.1
1
10
100
0.1 1 10 100
20
µ
s PULSE WIDTH
T = 25 C
J°
TOP
BOTTOM
VGS
15V
10V
8.0V
7.0V
6.0V
5.5V
5.0V
4.5V
V , Drain-to-Source Voltage (V)
I , Drain-to-Source Current (A)
DS
D
4.5V
0.1
1
10
100
1 10 100
20
µ
s PULSE WIDTH
T = 150 C
J°
TOP
BOTTOM
VGS
15V
10V
8.0V
7.0V
6.0V
5.5V
5.0V
4.5V
V , Drain-to-Source Volta
g
e (V)
I , Drain-to-Source Current (A)
DS
D
4.5V
0.1
1
10
100
4.0 5.0 6.0 7.0 8.0 9.0 10.0
V = 50V
20µs PULSE WIDTH
DS
V , Gate-to-Source Volta
g
e (V)
I , Drain-to-Source Current (A)
GS
D
T = 25 C
J°
T = 150 C
J°
-60 -40 -20 0 20 40 60 80 100 120 140 160
0.0
0.5
1.0
1.5
2.0
2.5
3.0
T , Junction Temperature ( C)
R , Drain-to-Source On Resistance
(Normalized)
J
DS(on)
°
V =
I =
GS
D
10V
5.9A
IRFBC40AS
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Fig 8. Maximum Safe Operating Area
Fig 6. Typical Gate Charge Vs.
Gate-to-Source Voltage
Fig 5. Typical Capacitance Vs.
Drain-to-Source Voltage
Fig 7. Typical Source-Drain Diode
Forward Voltage
0 8 16 24 32 40
0
4
8
12
16
20
Q , Total Gate Charge (nC)
V , Gate-to-Source Voltage (V)
G
GS
FOR TEST CIRCUIT
SEE FIGURE
I =
D
13
5.9A
V = 120V
DS
V = 300V
DS
V = 480V
DS
0.1
1
10
100
0.4 0.6 0.8 1.0 1.2
V ,Source-to-Drain Voltage (V)
I , Reverse Drain Current (A)
SD
SD
V = 0 V
GS
T = 25 C
J°
T = 150 C
J°
110 100 1000
VDS, Drain-to-Source Voltage (V)
1
10
100
1000
10000
100000
C, Capacitance(pF)
Coss
Crss
Ciss
VGS = 0V, f = 1 MHZ
Ciss = C
gs + Cgd, C
ds SHORTED
Crss
= C
gd
Coss
= C
ds + C
gd
0.1
1
10
100
10 100 1000 10000
OPERATION IN THIS AREA LIMITED
BY RDS(on)
Sin
g
le Pulse
T
T = 150 C
= 25 C
°°
J
C
V , Drain-to-Source Voltage (V)
I , Drain Current (A)I , Drain Current (A)
DS
D
10us
100us
1ms
10ms
IRFBC40AS
www.irf.com 5
Fig 10a. Switching Time Test Circuit
Fig 10b. Switching Time Waveforms
Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case
Fig 9. Maximum Drain Current Vs.
Case Temperature
VDS
Pulse Width ≤ 1 µs
Duty Factor ≤ 0.1 %
RD
VGS
RGD.U.T.
10V
+
-
VDD
V
DS
90%
10%
V
GS t
d(on)
t
r
t
d(off)
t
f
25 50 75 100 125 150
0.0
1.0
2.0
3.0
4.0
5.0
6.0
7.0
T , Case Temperature ( C)
I , Drain Current (A)
°
C
D
0.01
0.1
1
10
0.00001 0.0001 0.001 0.01 0.1 1
Notes:
1. Duty factor D = t / t
2. Peak T = P x Z + T
1 2
JDM thJC C
P
t
t
DM
1
2
t , Rectangular Pulse Duration (sec)
Thermal Response (Z )
1
thJC
0.01
0.02
0.05
0.10
0.20
D = 0.50
SINGLE PULSE
(THERMAL RESPONSE)
IRFBC40AS
6www.irf.com
Q
G
Q
GS
Q
GD
V
G
Charge
D.U.T. V
DS
I
D
I
G
3mA
V
GS
.3µF
50KΩ
.2µF
12V
Current Regulator
Same Type as D.U.T.
Current Sampling Resistors
+
-
10 V
Fig 13b. Gate Charge Test Circuit
Fig 13a. Basic Gate Charge Waveform
Fig 12c. Maximum Avalanche Energy
Vs. Drain Current
Fig 12b. Unclamped Inductive Waveforms
Fig 12a. Unclamped Inductive Test Circuit
tp
V
(BR)DSS
I
AS
R
G
I
AS
0.01
Ω
t
p
D.U.T
L
VDS
+
-V
DD
DRIVER
A
15V
20V
Fig 12d. Typical Drain-to-Source Voltage
Vs. Avalanche Current
0.0 1.0 2.0 3.0 4.0 5.0 6.0 7.0
IAV , Avalanche Current ( A)
720
740
760
780
800
820
V DSav , Avalanche Voltage ( V )
25 50 75 100 125 150
0
200
400
600
800
1000
1200
1400
Starting T , Junction Temperature ( C)
E , Single Pulse Avalanche Energy (mJ)
J
AS
°
ID
TOP
BOTTOM
2.8A
3.9A
6.2A
IRFBC40AS
www.irf.com 7
P.W. Period
di/dt
Diode Recovery
dv/dt
Ripple ≤5%
Body Diode Forward Drop
Re-Applied
Voltage
Reverse
Recovery
Current Body Diode Forward
Current
V
GS
=10V
V
DD
I
SD
Driver Gate Drive
D.U.T. I
SD
Waveform
D.U.T. V
DS
Waveform
Inductor Curent
D = P.W.
Period
+
-
+
+
+
-
-
-
Fig 14. For N-Channel HEXFETS
* VGS = 5V for Logic Level Devices
Peak Diode Recovery dv/dt Test Circuit
RGVDD
• dv/dt controlled by RG
• Driver same type as D.U.T.
• ISD controlled by Duty Factor "D"
• D.U.T. - Device Under Test
D.U.T Circuit Layout Considerations
• Low Stray Inductance
• Ground Plane
• Low Leakage Inductance
Current Transformer
*
IRFBC40AS
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D2Pak Package Outline
D2Pak
Part Marking Information
10.16 (.400)
REF.
6.47 (.255 )
6.18 (.243 )
2.61 (.103)
2.32 (.091)
8.89 (.350)
REF.
- B -
1.32 (.052)
1.22 (.048)
2.79 (.110)
2.29 (.090)
1.39 (.055)
1.14 (.045)
5.28 (.208)
4.78 (.188)
4.69 (.185)
4.20 (.165)
10.54 (.415)
10.29 (.405)
- A -
2
1 3 15.49 (.610)
14.73 (.580)
3X 0.93 (.037)
0.69 (.027)
5 .08 (.20 0)
3X 1.40 (.055)
1.14 (.045)
1.78 (.070)
1.27 (.050)
1.40 (.055)
MAX .
NOTES:
1 DIMENSIONS AFTER SOLDER DIP.
2 DIMENSIONING & TOLE RANCING PER ANSI Y14.5M, 1982.
3 CONTROLLING DIMENSION : INCH.
4 HEATSINK & LEAD DIM ENSIONS DO NOT INCLUDE BURRS.
0.55 (.022)
0.46 (.018)
0.2 5 (.0 1 0) M B A M MINIMUM RECOMMENDED FOOTPRINT
11.43 (.450)
8 .89 (.35 0)
17 .78 (.70 0)
3.81 (.15 0)
2.08 (.082)
2X
LEAD AS SIG N ME N TS
1 - GATE
2 - DR AIN
3 - SOURCE
2.54 (.100)
2X
PAR T NUM B ER
INTERNATIONAL
RE CTIFIE R
L O G O DATE CODE
(YYW W )
YY = YEAR
WW = WEEK
A S SEMBLY
LO T CO D E
F530S
9B 1 M
9246
A
IRFBC40AS
www.irf.com 9
WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, Tel: (310) 322 3331
IR GREAT BRITAIN: Hurst Green, Oxted, Surrey RH8 9BB, UK Tel: ++ 44 1883 732020
IR CANADA: 15 Lincoln Court, Brampton, Ontario L6T3Z2, Tel: (905) 453 2200
IR GERMANY: Saalburgstrasse 157, 61350 Bad Homburg Tel: ++ 49 6172 96590
IR ITALY: Via Liguria 49, 10071 Borgaro, Torino Tel: ++ 39 11 451 0111
IR FAR EAST: K&H Bldg., 2F, 30-4 Nishi-Ikebukuro 3-Chome, Toshima-Ku, Tokyo Japan 171 Tel: 81 3 3983 0086
IR SOUTHEAST ASIA: 1 Kim Seng Promenade, Great World City West Tower, 13-11, Singapore 237994 Tel: ++ 65 838 4630
IR TAIWAN:16 Fl. Suite D. 207, Sec. 2, Tun Haw South Road, Taipei, 10673, Taiwan Tel: 886-2-2377-9936
http://www.irf.com/ Data and specifications subject to change without notice. 6/99
Tape & Reel Information
D2Pak
3
4
4
TRR
FEED D IRE CTION
1 .85 (.0 73)
1 .65 (.0 65)
1 .60 (.0 63)
1 .50 (.0 59)
4.10 (.161)
3.90 (.153)
TRL
FEED DIRECTION
10.90 (.429)
10.70 (.421) 16.10 (.634)
15.90 (.626)
1.75 (.069)
1.25 (.049)
11.60 (.457)
11.40 (.449) 15.42 (.609)
15.22 (.601)
4.72 (.136)
4.52 (.178)
24.30 (.957)
23.90 (.941)
0.368 (.0145)
0.342 (.0135)
1.60 (.063)
1.50 (.059)
13.50 (.532 )
12.80 (.504 )
330.00
(14.173)
MAX.
2 7.40 (1.079 )
2 3.90 (.941)
60.00 (2.362)
M IN .
30.40 (1.197)
M A X.
26 .40 (1.03 9)
24 .40 (.9 61 )
NO TES :
1. COMFORM S TO EIA-418.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION MEASURED @ HUB.
4. INCLUDES FLANGE DISTORTION @ O UTER EDGE.
Repetitive rating; pulse width limited by
max. junction temperature. ( See fig. 11 )
ISD ≤ 6.2A, di/dt ≤ 88A/µs, VDD ≤ V(BR)DSS,
TJ ≤ 150°C
Notes:
Starting TJ = 25°C, L = 29.6mH
RG = 25Ω, IAS = 6.2A. (See Figure 12)
Pulse width ≤ 300µs; duty cycle ≤ 2%.
Coss eff. is a fixed capacitance that gives the same charging time
as Coss while VDS is rising from 0 to 80% VDSS
Uses IRFBC40A data and test conditions
* When mounted on FR-4 board using minimum recommended footprint.
For recommended footprint and soldering techniques refer to application note #AN-994.
