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features
D10-Bit Voltage Output DAC
DProgrammable Settling Time vs Power
Consumption
3 µs in Fast Mode
9 µs in Slow Mode
DUltra Low Power Consumption:
900 µW Typ in Slow Mode at 3 V
2.1 mW Typ in Fast Mode at 3 V
DDifferential Nonlinearity...<0.2 LSB Typ
DCompatible With TMS320 and SPI Serial
Ports
DPower-Down Mode (10 nA)
DBuffered High-Impedance Reference Input
DVoltage Output Range ... 2 Times the
Reference Input Voltage
DMonotonic Over Temperature
DAvailable in MSOP Package
applications
DDigital Servo Control Loops
DDigital Offset and Gain Adjustment
DIndustrial Process Control
DMachine and Motion Control Devices
DMass Storage Devices
description
The TLV5606 is a 10-bit voltage output digital-to-
analog converter (DAC) with a flexible 4-wire
serial interface. The 4-wire serial interface allows
glueless interface to TMS320, SPI, QSPI, and
Microwire serial ports. The TLV5606 is pro-
grammed with a 16-bit serial string containing 4
control and 10 data bits. Developed for a wide
range of supply voltages, the TLV5606 can
operate from 2.7 V to 5.5 V.
The resistor string output voltage is buffered by a x2 gain rail-to-rail output buffer. The buffer features a Class AB
output stage to improve stability and reduce settling time. The settling time of the DAC is programmable to allow
the designer to optimize speed versus power dissipation. The settling time is chosen by the control bits within
the 16-bit serial input string. A high-impedance buffer is integrated on the REFIN terminal to reduce the need
for a low source impedance drive to the terminal.
Implemented with a CMOS process, the TLV5606 is designed for single supply operation from 2.7 V to 5.5 V.
The device is available in an 8-terminal SOIC package. The TLV5606C is characterized for operation from 0°C
to 70°C. The TLV5606I is characterized for operation from −40°C to 85°C.
AVAILABLE OPTIONS
PACKAGE
TASMALL OUTLINE†
(D) MSOP†
(DGK)
0°C to 70°C TLV5606CD TLV5606CDGK
−40°C to 85°C TLV5606ID TLV5606IDGK
†Available i n tape and reel as the TLV5606CDR, TLV5606IDR,
TLV5606CDGKR, and the TLV5606IDGKR
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications o
f
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 2002−2004, Texas Instruments Incorporated
!"# $ %&'# "$ (&)*%"# +"#'
+&%#$ %! # $('%%"#$ (' #,' #'!$ '-"$ $#&!'#$
$#"+"+ .""#/ +&%# (%'$$0 +'$ # '%'$$"*/ %*&+'
#'$#0 "** (""!'#'$
1
2
3
4
8
7
6
5
DIN
SCLK
CS
FS
VDD
OUT
REFIN
AGND
D OR DGK PACKAGE
(TOP VIEW)
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functional block diagram
Serial Input
Register
16 Cycle
Timer
REFIN
CS
SCLK
FS
OUT
_
+
Power-On
Reset
DIN 10-Bit
Data
Latch
Speed/Power-Down
Logic
2
10
Update
6
1
2
3
4
7
x2
12
10
Terminal Functions
TERMINAL
I/O
DESCRIPTION
NAME NO.
I/O
DESCRIPTION
AGND 5 Analog ground
CS 3 I Chip select. Digital input used to enable and disable inputs, active low.
DIN 1 I Serial digital data input
FS 4 I Frame sync. Digital input used for 4-wire serial interfaces such as the TMS320 DSP interface.
OUT 7 O DAC analog output
REFIN 6 I Reference analog input voltage
SCLK 2 I Serial digital clock input
VDD 8Positive power supply
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absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage (VDD to AGND) 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Reference input voltage range − 0.3 V to VDD + 0.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Digital input voltage range − 0.3 V to VDD + 0.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating free-air temperature range, TA: TLV5606C 0°C to 70°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TLV5606I −40°C to 85°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, Tstg −65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 260°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
recommended operating conditions
MIN NOM MAX UNIT
Supply voltage, VDD
VDD = 5 V 4.5 5 5.5 V
Supply voltage, V
DD VDD = 3 V 2.7 3 3.3 V
High-level digital input voltage, VIH
DVDD = 2.7 V 2 V
High-level digital input voltage, V
IH DVDD = 5.5 V 2.4 V
Low-level digital input voltage, VIL
DVDD = 2.7 V 0.6 V
Low-level digital input voltage, V
IL DVDD = 5.5 V 1 V
Reference voltage, Vref to REFIN terminal VDD = 5 V (see Note 1) AGND 2.048 VDD−1.5 V
Reference voltage, Vref to REFIN terminal VDD = 3 V (see Note 1) AGND 1.024 VDD−1.5 V
Load resistance, RL2 10 kΩ
Load capacitance, CL100 pF
Clock frequency, fCLK 20 MHz
Operating free-air temperature, TA
TLV5606C 0 70 °C
Operating free-air temperature, T
ATLV5606I −40 85 °C
NOTE 1: Due to the x2 output buffer, a reference input voltage ≥ VDD/2 causes clipping of the transfer function.
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
power supply
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VDD = 5 V, VREF = 2.048 V,
No load, Fast 0.9 1.35 mA
IDD
Power supply current
No load,
All inputs = AGND or VDD,
DAC latch = 0x800 Slow 0.4 0.6 mA
I
DD
Power supply current
VDD = 3 V, VREF = 1.024 V
No load, Fast 0.7 1.1 mA
No load,
All inputs = AGND or VDD,
DAC latch = 0x800 Slow 0.3 0.45 mA
Power down supply current (see Figure 12) 10 nA
PSRR
Power supply rejection ratio
Zero scale See Note 2 −80
dB
PSRR
Power supply rejection ratio
Full scale See Note 3 −80
dB
Power on threshold voltage, POR 2 V
NOTES: 2. Power supply rejection ratio at zero scale is measured by varying VDD and is given by:
PSRR = 20 log [(EZS(VDDmax) − EZS(VDDmin))/VDDmax]
3. Power supply rejection ratio at full scale is measured by varying VDD and is given by:
PSRR = 20 log [(EG(VDDmax) − EG(VDDmin))/VDDmax]
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electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted) (continued)
static DAC specifications RL = 10 kΩ, CL = 100 pF
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Resolution 10 10 bits
INL Integral nonlinearity See Note 4 ±0.5 ±1.5 LSB
DNL Differential nonlinearity See Note 5 ±0.2 ±1 LSB
EZS Zero-scale error (offset error at zero scale) See Note 6 ±10 mV
Zero-scale-error temperature coefficient See Note 7 10 ppm/°C
EGGain error See Note 8 ±0.6 % of
FS
voltage
Gain-error temperature coefficient See Note 9 10 ppm/°C
NOTES: 4. The relative accuracy or integral nonlinearity (INL) sometimes referred to as linearity error, is the maximum deviation of the output
from the line between zero and full scale excluding the effects of zero code and full-scale errors. Tested from code 10 to code 1023.
5. The differential nonlinearity (DNL) sometimes referred to as differential error, is the difference between the measured and ideal 1
LSB amplitude change of any two adjacent codes. Monotonic means the output voltage changes in the same direction (or remains
constant) as a change in the digital input code. Tested from code 10 to code 1023.
6. Zero-scale error is the deviation from zero voltage output when the digital input code is zero.
7. Zero-scale-error temperature coefficient is given by: EZS TC = [EZS (Tmax) − E ZS (Tmin)]/Vref × 106/(Tmax − Tmin).
8. Gain error is the deviation from the ideal output (2V ref − 1 LSB) with an output load of 10 kΩ excluding the effects of the zero-error.
9. Gain temperature coefficient is given by: EGTC = [EG(Tmax) − EG (Tmin)]/Vref × 106/(Tmax − Tmin).
output specifications
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VOVoltage output range RL = 10 kΩ0AVDD−0.1 V
Output load regulation accuracy RL = 2 kΩ, vs 10 kΩ0.1 ±0.25 % of FS
voltage
reference input (REF)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VIInput voltage range 0 VDD−1.5 V
RIInput resistance 10 MΩ
CIInput capacitance 5 pF
Reference input bandwidth
REFIN = 0.2 Vpp + 1.024 V dc
Slow 525 kHz
Reference input bandwidth REFIN = 0.2 Vpp + 1.024 V dc Fast 1.3 MHz
Reference feed through REFIN = 1 Vpp at 1 kHz + 1.024 V dc (see Note 10) −75 dB
NOTE 10: Reference feedthrough is measured at the DAC output with an input code = 0x000.
digital inputs
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
IIH High-level digital input current VI = VDD ±1µA
IIL Low-level digital input current VI = 0 V ±1µA
CIInput capacitance 3 pF
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operating characteristics over recommended operating free-air temperature range (unless
otherwise noted)
analog output dynamic performance
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
ts(FS)
Output settling time, full scale
RL = 10 k
Ω
,
C
L
= 100 pF, Fast 3 5.5
s
ts(FS) Output settling time, full scale
RL = 10 kΩ,
See Note 11
CL = 100 pF,
Slow 9 20 µs
ts(CC)
Output settling time, code to code
RL = 10 k
Ω
,
C
L
= 100 pF, Fast 1 µs
ts(CC) Output settling time, code to code
RL = 10 kΩ,
See Note 12
CL = 100 pF,
Slow 2 µs
SR
Slew rate
RL = 10 k
Ω
,
CL = 100 pF,
Fast 3.6
V/ s
SR Slew rate
RL = 10 kΩ,
See Note 13
CL = 100 pF,
Slow 0.9 V/µs
Glitch energy Code transition from 0x7FF to 0x800 10 nV−s
S/N Signal to noise
fs = 400 KSPS fout = 1.1 kHz,
62 dB
S/(N+D) Signal to noise + distortion fs = 400 KSPS fout = 1.1 kHz,
RL = 10 kΩCL = 100 pF,
60 dB
THD Total harmonic distortion
R
L
= 10 k
Ω,
C
L
= 100 pF,
BW = 20 kHz
−61 dB
Spurious free dynamic range
BW = 20 kHz
68 dB
NOTES: 11. Settling time is the time for the output signal to remain within ±0.5 LSB of the final measured value for a digital input code change
of 0x080 to 0x3FF or 0x3FF to 0x080. Not tested, ensured by design.
12. Settling time is the time for the output signal to remain within ± 0.5 LSB of the final measured value for a digital input code change
of one count. Code change from 0x1FF to 0x200. Not tested, ensured by design.
13. Slew rate determines the time it takes for a change of the DAC output from 10% to 90% full-scale voltage.
digital input timing requirements
MIN NOM MAX UNIT
tsu(CS−FS) Setup time, CS low before FS↓10 ns
tsu(FS−CK) Setup time, FS low before first negative SCLK edge 8 ns
tsu(C16−FS) Setup time, sixteenth negative edge after FS low on which bit D0 is sampled before rising
edge of FS 10 ns
tsu(C16−CS) Setup time, sixteenth positive SCLK edge (first positive after D0 is sampled) before CS rising
edge. If F S i s used instead of the sixteenth positive edge to update the DAC, then the setup
time is between the FS rising edge and CS rising edge. 10 ns
twH Pulse duration, SCLK high 25 ns
twL Pulse duration, SCLK low 25 ns
tsu(D) Setup time, data ready before SCLK falling edge 8 ns
th(D) Hold time, data held valid after SCLK falling edge 5 ns
twH(FS) Pulse duration, FS high 20 ns
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PARAMETER MEASUREMENT INFORMATION
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
123451516
D15 D14 D13 D12 D1 D0
tsu(FS-CK)
tsu(CS-FS)
twH(FS)
th(D)
tsu(D)
twH
twL
tsu(C16-CS)
tsu(C16-FS)
SCLK
DIN
CS
FS
Figure 1. Timing Diagram
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TYPICAL CHARACTERISTICS
Figure 2
1.998
1.996
1.994
1.990 0 0.01 0.02 0.05 0.1 0.2 0.5
− Output Voltage − V
2
2.002
Load Current − mA
OUTPUT VOLTAGE
vs
LOAD CURRENT
2.004
12
3 V Slow Mode, SOURCE
3 V Fast Mode, SOURCE
1.992
VO
VDD = 3 V,
Vref = 1 V,
Full Scale
Figure 3
3.995
3.99
3.985
3.975 0 0.02 0.04 0.1 0.2 0.4 1
4
4.005
OUTPUT VOLTAGE
vs
LOAD CURRENT
4.01
24
3.98
− Output Voltage − V
Load Current − mA
5 V Slow Mode, SOURCE
5 V Fast Mode, SOURCE
VO
VDD = 5 V,
Vref = 2 V,
Full Scale
Figure 4
0.1
0.08
0.04
00 0.01 0.02 0.05 0.1 0.2 0.5
0.16
0.18
OUTPUT VOLTAGE
vs
LOAD CURRENT
0.2
12
0.14
0.12
0.06
0.02
− Output Voltage − V
Load Current − mA
3 V Slow Mode, SINK
3 V Fast Mode, SINK
VO
VDD = 3 V,
Vref = 1 V,
Zero Code
Figure 5
0.2
0.15
0.1
00 0.02 0.04 0.1 0.2 0.4 1
0.25
0.3
OUTPUT VOLTAGE
vs
LOAD CURRENT
0.35
24
0.05
− Output Voltage − V
Load Current − mA
5 V Slow Mode, SINK
5 V Fast Mode, SINK
VO
VDD = 5 V,
Vref = 2 V,
Zero Code
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TYPICAL CHARACTERISTICS
Figure 6
0.6
0.4
0.2
−55 −40 −25 0 25 40 70
− Supply Current − mA
0.8
SUPPLY CURRENT
vs
FREE-AIR TEMPERATURE
1
85 125
IDD
VDD = 3 V,
Vref = 1 V,
Full Scale
TA − Free-Air Temperature − C°
Fast Mode
Slow Mode
Figure 7
SUPPLY CURRENT
vs
FREE-AIR TEMPERATURE
0.6
0.4
0.2
−55 −40 −25 0 25 40 70
− Supply Current − mA
0.8
1
85 125
IDD
VDD = 5 V,
Vref = 2 V,
Full Scale
TA − Free-Air Temperature − C°
Fast Mode
Slow Mode
Figure 8
−−40
−50
−70
−80 0 5 10 20
THD − Total Harmonic Distortion − dB
−30
−10
f − Frequency − kHz
TOTAL HARMONIC DISTORTION
vs
FREQUENCY
0
30 50 100
−20
−60
Vref = 1 V dc + 1 V p/p Sinewave,
Output Full Scale
Fast Mode
Figure 9
−−40
−50
−70
−80 0 5 10 20
THD − Total Harmonic Distortion − dB
−30
−10
f − Frequency − kHz
TOTAL HARMONIC DISTORTION
vs
FREQUENCY
0
30 50 100
−20
−60
Vref = 1 V dc + 1 V p/p Sinewave,
Output Full Scale
Slow Mode
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TYPICAL CHARACTERISTICS
Figure 10
−−40
−50
−70
−80 0 5 10 20
THD − Total Harmonic Distortion And Noise − dB
−30
−10
f − Frequency − kHz
TOTAL HARMONIC DISTORTION AND NOISE
vs
FREQUENCY
0
30 50 100
−20
−60
Vref = 1 V dc + 1 V p/p Sinewave,
Output Full Scale
Fast Mode
Figure 11
−−40
−50
−70
−80 0 5 10 20
−30
−10
f − Frequency − kHz
TOTAL HARMONIC DISTORTION AND NOISE
vs
FREQUENCY
0
30 50 100
−20
−60
Vref = 1 V dc + 1 V p/p Sinewave,
Output Full Scale
THD − Total Harmonic Distortion And Noise − dB
Slow Mode
Figure 12
400
300
100
00 100 200 300 400 500 600
− Supply Current −
600
800
T − Time − ns
SUPPLY CURRENT
vs
TIME (WHEN ENTERING POWER-DOWN MODE)
900
700 800 900 1000
700
500
200
IDD µA
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TYPICAL CHARACTERISTICS
−1.0
−0.5
0.0
0.5
1.0
0 512 1024
INL − Integral Nonlinearity − LSB
Digital Code
INTEGRAL NONLINEARITY ERROR
Figure 13
−0.20
−0.16
−0.12
−0.08
−0.04
0.00
0.04
0.08
0.12
0.16
0.20
0 512 1024
DNL − Differential Nonlinearity − LSB
Digital Code
DIFFERENTIAL NONLINEARITY ERROR
Figure 14
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APPLICATION INFORMATION
general function
The T LV5606 is a 10-bit single supply DAC based on a resistor string architecture. The device consists of a serial
interface, speed and power-down control logic, a reference input buf fer , a resistor string, and a rail-to-rail output
buffer.
The output voltage (full scale determined by external reference) is given by:
2REFCODE
2n[V]
where REF is the reference voltage and CODE is the digital input value within the range of 010 to 2n−1, where
n = 10 (bits). The 16-bit data word, consisting of control bits and the new DAC value, is illustrated in the data
format section. A power-on reset initially resets the internal latches to a defined state (all bits zero).
serial interface
Explanation of data transfer: First, the device has to be enabled with CS set to low. Then, a falling edge of FS
starts shifting the data bit-per-bit (starting with the MSB) to the internal register on the falling edges of SCLK.
After 16 bits have been transferred or FS rises, the content of the shift register is moved to the DAC latch which
updates the voltage output to the new level.
The serial interface of the TLV5606 can be used in two basic modes:
DFour wire (with chip select)
DThree wire (without chip select)
Using chip select (four wire mode), it is possible to have more than one device connected to the serial port of
the data source (DSP or microcontroller). The interface is compatible with the TMS320 family. Figure 15 shows
an example with two TLV5606s connected directly to a TMS320 DSP.
TMS320
DSPXF0
XF1
FSX
DX
CLKX
TLV5606
CS FS DIN SCLK
TLV5606
CS FS DIN SCLK
Figure 15. TMS320 Interface
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APPLICATION INFORMATION
serial interface (continued)
If there is no need to have more than one device on the serial bus, then CS can be tied low. Figure 16 shows
an example of how to connect the TLV5606 to a TMS320, SPI, or Microwire port using only three pins.
TMS320
DSPFSX
DX
CLKX
TLV5606
FS
DIN
SCLK
CS
SPI
SS
MOSI
SCLK
TLV5606
FS
DIN
SCLK
CS
Microwire
I/O
SO
SK
TLV5606
FS
DIN
SCLK
CS
Figure 16. Three-Wire Interface
Notes on SPI and Microwire: Before the controller starts the data transfer, the software has to generate a falling
edge on the I/O pin connected to FS. If the word width is 8 bits (SPI and Microwire), two write operations must
be performed to program the TLV5606. After the write operation(s), the DAC output is updated automatically
on the next positive clock edge following the sixteenth falling clock edge.
serial clock frequency and update rate
The maximum serial clock frequency is given by:
fSCLKmax +1
twH(min) )twL(min) +20 MHz
The maximum update rate is:
fUPDATEmax +1
16 ǒtwH(min))twL(min)Ǔ+1.25 MHz
The maximum update rate is a theoretical value for the serial interface, since the settling time of the TLV5606
has to be considered also.
data format
The 16-bit data word for the TLV5606 consists of two parts:
DControl bits (D15 . . . D12)
DNew DAC value (D11 ...D2)
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
X SPD PWR X New DAC value (10 bits) 0 0
X: don’t care
SPD: Speed control bit. 1 → fast mode 0 → slow mode
PWR: Power control bit. 1 → power down 0 → normal operation
In power-down mode, all amplifiers within the TLV5606 are disabled.
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APPLICATION INFORMATION
TLV5606 interfaced to TMS320C203 DSP
hardware interfacing
Figure 17 shows an example how to connect the TLV5606 to a TMS320C203 DSP. The serial interface of the
TLV5606 is ideally suited to this configuration, using a maximum of four wires to make the necessary
connections. In applications where only one synchronous serial peripheral is used, the interface can be
simplified even further by pulling CS low all the time as shown in the figure.
FS
DIN
SCLKOUT
REFIN
CS AGND
VDD
REF
FS
DX
CLKX
TMS320C203 TLV5606
RLOAD
Figure 17. TLV5606 to DSP Interface
software
No setup procedure is needed to access the TLV5606. The output voltage can be set using just a single
command.
out data_addr, SDTR
where data_addr points to an address location holding the control bits and the 12 data bits providing the output
voltage data. SDTR is the address of the transmit FIFO of the synchronous serial port.
The following code shows how to use the timer of the TMS320C203 as a time base to generate a voltage ramp
with the TLV5606.
A timer interrupt is generated every 205 µs. The corresponding interrupt service routine increments the output
code (stored at 0x0064) for the DAC, adds the DAC control bits to the four most significant bits, and writes the
new code to the TLV5606. The resulting period of the saw waveform is:
π = 4096 × 205 E-6 s = 0.84 s
;***************************************************************************************
;* Title : Ramp generation with TLV5606 *
;* Version : 1.0 *
;* DSP : TI TMS320C203 *
;* (1998) Texas Instruments Incorporated *
;***************************************************************************************
;−−−−−−−−−−− I/O and memory mapped regs −−−−−−−−−−−−
.include ”regs.asm”
;−−−−−−−−−−− vectors −−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−
.ps 0h
b start
b INT1
b INT23
b TIM_ISR
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APPLICATION INFORMATION
;***************************************************************************************
;* Main Program
;***************************************************************************************
.ps 1000h
.entry
start:
; disable interrupts
setc INTM ; disable maskable interrupts
splk #0ffffh, IFR
splk #0004h, IMR
; set up the timer to interrupt ever 205uS
splk #0000h, 60h
splk #00FFh, 61h
out 61h, PRD
out 60h, TIM
splk #0c2fh, 62h
out 62h, TCR
; Configure SSP to use internal clock, internal frame sync and burst mode
splk #0CC0Eh, 63h
out 63h, SSPCR
splk #0CC3Eh, 63h
out 63h, SSPCR
splk #0000h, 64h ; set initial DAC value
; enable interrupts
clrc INTM ; enable maskable interrupts
; loop forever!
next: idle ;wait for interrupt
b next
; all else fails stop here
done: b done ;hang there
;***************************************************************************************
;* Interrupt Service Routines
;***************************************************************************************
INT1: ret ;do nothing and return
INT23: ret ;do nothing and return
TIM_ISR:
lacl 64h ; restore counter value to ACC
add #4h ; increment DAC value
and #0FFCh ; mask 4 MSBs
sacl 64h ; store 12 bit counter value
or #4000h ; set DAC control bits
sacl 65h ; store DAC value
out 65h, SDTR ; send data
clrc intm ; re-enable interrupts
ret
.END
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APPLICATION INFORMATION
TLV5606 interfaced to MCS51 microcontroller
hardware interfacing
Figure 18 shows an example of how to connect the TLV5606 to an MCS51 compatible microcontroller. The
serial DAC input data and external control signals are sent via I/O port 3 of the controller. The serial data is sent
on the RxD line, with the serial clock output on the TxD line. P3.4 and P3.5 are configured as outputs to provide
the chip select and frame sync signals for the TLV5606.
SDIN
SCLK
CS
OUT
REFIN
AGND
REF
RxD
TxD
P3.4
MCS51 Controller TLV5606
FS
P3.5
VDD
RLOAD
Figure 18. TLV5606 to MCS51 Controller Interface
software
The example program puts out a sine wave on the OUT pin.
The on-chip timer is used to generate interrupts at a fixed frequency. The related interrupt service routine fetches
and writes the next sample to the DAC. The samples are stored in a lookup table, which describes one full period
of a sine wave.
The serial port of the controller is used in mode 0, which transmits 8 bits of data on RxD, accompanied by a
synchronous clock on TxD. Two writes concatenated together are required to write a complete word to the
TLV5606. The CS and FS signals are provided in the required fashion through control of I/O port 3, which has
bit addressable outputs.
;***************************************************************************************
;* Title : Ramp generation with TLV5606 *
;* Version : 1.0 *
;* MCU : INTEL MCS51 *
;* (1998) Texas Instruments Incorporated *
;***************************************************************************************
;−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−
; Program function declaration
;−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−
NAME GENSINE
MAIN SEGMENT CODE
ISR SEGMENT CODE
SINTBL SEGMENT CODE
VAR1 SEGMENT DATA
STACK SEGMENT IDATA
;−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−
; Code start at address 0, jump to start
;−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−
CSEG AT 0
MCS is a registered trademark of Intel Corporation
SLAS259B − DECEMBER 1999 − REVISED APRIL 2004
16 WWW.TI.COM
APPLICATION INFORMATION
LJMP start ; Execution starts at address 0 on power−up.
;−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−
; Code in the timer0 interrupt vector
;−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−
CSEG AT 0BH
LJMP timer0isr ; Jump vector for timer 0 interrupt is 000Bh
;−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−
; Define program variables
;−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−
RSEG VAR1
rolling_ptr: DS 1
;−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−
; Interrupt service routine for timer 0 interrupts
;−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−
RSEG ISR
timer0isr:
PUSH PSW
PUSH ACC
CLR T0 ; set CSB low
CLR T1 ; set FS low
; The signal to be output on the dac is a sine function. One cycle of a sine wave is
; held in a table @ sinevals as 32 samples of msb, lsb pairs (64 bytes). The pointer,
; rolling_ptr, rolls round the table of samples incrementing by 2 bytes (1 sample) on
; each interrupt (at the end of this routine).
MOV DPTR,#sinevals ; set DPTR to the start of the table of sine signal values
MOV A,rolling_ptr ; ACC loaded with the pointer into the sine table
MOVC A,@A+DPTR ; get msb from the table
ORL A, #00H ; set control bits
MOV SBUF,A ; send out msb of data word
MOV A,rolling_ptr ; move rolling pointer in to ACC
INC A ; increment ACC holding the rolling pointer
MOVC A,@A+DPTR ; which is the lsb of this sample, now in ACC
MSB_TX:
JNB TI, MSB_TX ; wait for transmit to complete
CLR TI ; clear for new transmit
MOV SBUF,A ; and send out the lsb
LSB_TX:
JNB TI, LSB_TX ; wait for lsb transmit to complete
SETB T1 ; set FS = 1
CLR TI ; clear for new transmit
MOV A,rolling_ptr ; load ACC with rolling pointer
INC A ; increment the ACC twice, to get next sample
INC A
ANL A,#03FH ; wrap back round to 0 if >64
MOV rolling_ptr,A ; move value held in ACC back to the rolling pointer
SETB T0 ; CSB high
POP ACC
POP PSW
RETI
;−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−
; Set up stack
;−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−
SLAS259B − DECEMBER 1999 − REVISED APRIL 2004
17
WWW.TI.COM
APPLICATION INFORMATION
RSEG STACK
DS 10h ; 16 Byte Stack!
;−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−
; Main Program
;−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−
RSEG MAIN
start:
MOV SP,#STACK−1 ; first set Stack Pointer
CLR A
MOV SCON,A ; set serial port 0 to mode 0
MOV TMOD,#02H ; set timer 0 to mode 2 − auto−reload
MOV TH0,#0C8H ; set TH0 for 16.67 kHs interrupts
SETB T1 ; set FS = 1
SETB T0 ; set CSB = 1
SETB ET0 ; enable timer 0 interrupts
SETB EA ; enable all interrupts
MOV rolling_ptr,A ; set rolling pointer to 0
SETB TR0 ; start timer 0
always:
SJMP always ; while(1) !
RET
;−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−
; Table of 32 sine wave samples used as DAC data
;−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−
RSEG SINTBL
sinevals:
DW 01000H
DW 0903CH
DW 05094H
DW 0305CH
DW 0B084H
DW 070C8H
DW 0F0E0H
DW 0F066H
DW 0F038H
DW 0F06CH
DW 0F0E0H
DW 070C8H
DW 0B084H
DW 0305CH
DW 05094H
DW 0903CH
DW 01000H
DW 06020H
DW 0A0E8H
DW 0C060H
DW 040F8H
DW 080B4H
DW 0009CH
DW 00050H
DW 00024H
DW 00050H
DW 0009CH
DW 080B4H
DW 040F8H
DW 0C060H
DW 0A0E8H
DW 06020H
END
SLAS259B − DECEMBER 1999 − REVISED APRIL 2004
18 WWW.TI.COM
APPLICATION INFORMATION
linearity, offset, and gain error using single ended supplies
When an amplifier is operated from a single supply, the voltage offset can still be either positive or negative. With
a positive offset, the output voltage changes on the first code change. With a negative offset, the output voltage
may not change with the first code, depending on the magnitude of the offset voltage.
The output amplifier attempts to drive the output to a negative voltage. However, because the most negative
supply rail is ground, the output cannot drive below ground and clamps the output at 0 V.
The output voltage then remains at zero until the input code value produces a sufficient positive output voltage
to overcome the negative offset voltage, resulting in the transfer function shown in Figure 19.
DAC Code
Output
Voltage
0 V
Negative
Offset
Figure 19. Effect of Negative Offset (Single Supply)
This offset error, not the linearity error, produces this breakpoint. The transfer function would have followed the
dotted line if the output buffer could drive below the ground rail.
For a DAC, linearity is measured between zero-input code (all inputs 0) and full-scale code (all inputs 1) after
offset and full scale are adjusted out or accounted for in some way. However, single supply operation does not
allow for adjustment when the offset is negative due to the breakpoint in the transfer function. So the linearity
is measured between full-scale code and the lowest code that produces a positive output voltage.
power-supply bypassing and ground management
Printed-circuit boards that use separate analog and digital ground planes of fer the best system performance.
Wire-wrap boards do not perform well and should not be used. The two ground planes should be connected
together at the low-impedance power-supply source. The best ground connection may be achieved by
connecting the DAC AGND terminal to the system analog ground plane, making sure that analog ground
currents are well managed and there are negligible voltage drops across the ground plane.
A 0.1-µF ceramic-capacitor bypass should be connected between VDD and AGND and mounted with short leads
as close as possible to the device. Use of ferrite beads may further isolate the system analog supply from the
digital power supply.
Figure 20 shows the ground plane layout and bypassing technique.
0.1 µF
Analog Ground Plane
1
2
3
4
8
7
6
5
Figure 20. Power-Supply Bypassing
SLAS259B − DECEMBER 1999 − REVISED APRIL 2004
19
WWW.TI.COM
APPLICATION INFORMATION
definitions of specifications and terminology
integral nonlinearity (INL)
The relative accuracy or integral nonlinearity (INL), sometimes referred to as linearity error, is the maximum
deviation of the output from the line between zero and full scale excluding the ef fects of zero code and full-scale
errors.
differential nonlinearity (DNL)
The differential nonlinearity (DNL), sometimes referred to as differential error, is the difference between the
measured and ideal 1 LSB amplitude change of any two adjacent codes. Monotonic means the output voltage
changes in the same direction (or remains constant) as a change in the digital input code.
zero-scale error (EZS)
Zero-scale error is defined as the deviation of the output from 0 V at a digital input value of 0.
gain error (EG)
Gain error is the error in slope of the DAC transfer function.
signal-to-noise ratio + distortion (S/N+D)
S/N+D is the ratio of the rms value of the output signal to the rms sum of all other spectral components below
the Nyquist frequency, including harmonics but excluding dc. The value for S/N+D is expressed in decibels.
spurious free dynamic range (SFDR)
SFDR is the difference between the rms value of the output signal and the rms value of the largest spurious
signal within a specified bandwidth. The value for SFDR is expressed in decibels.
total harmonic distortion (THD)
THD is the ratio of the rms sum of the first six harmonic components to the rms value of the fundamental signal
and is expressed in decibels.
PACKAGE OPTION ADDENDUM
www.ti.com 16-Aug-2012
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
TLV5606CD ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV5606CDG4 ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV5606CDGK ACTIVE VSSOP DGK 8 80 Green (RoHS
& no Sb/Br) CU NIPDAUAGLevel-1-260C-UNLIM
TLV5606CDGKG4 ACTIVE VSSOP DGK 8 80 Green (RoHS
& no Sb/Br) CU NIPDAUAGLevel-1-260C-UNLIM
TLV5606CDGKR ACTIVE VSSOP DGK 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAUAGLevel-1-260C-UNLIM
TLV5606CDGKRG4 ACTIVE VSSOP DGK 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAUAGLevel-1-260C-UNLIM
TLV5606CDR ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV5606CDRG4 ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV5606ID ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV5606IDG4 ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV5606IDGK ACTIVE VSSOP DGK 8 80 Green (RoHS
& no Sb/Br) CU NIPDAUAGLevel-1-260C-UNLIM
TLV5606IDGKG4 ACTIVE VSSOP DGK 8 80 Green (RoHS
& no Sb/Br) CU NIPDAUAGLevel-1-260C-UNLIM
TLV5606IDGKR ACTIVE VSSOP DGK 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAUAGLevel-1-260C-UNLIM
TLV5606IDGKRG4 ACTIVE VSSOP DGK 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAUAGLevel-1-260C-UNLIM
TLV5606IDR ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV5606IDRG4 ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
(1) The marketing status values are defined as follows:
PACKAGE OPTION ADDENDUM
www.ti.com 16-Aug-2012
Addendum-Page 2
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
TLV5606CDGKR VSSOP DGK 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1
TLV5606CDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
TLV5606IDGKR VSSOP DGK 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1
TLV5606IDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 16-Aug-2012
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TLV5606CDGKR VSSOP DGK 8 2500 367.0 367.0 35.0
TLV5606CDR SOIC D 8 2500 367.0 367.0 35.0
TLV5606IDGKR VSSOP DGK 8 2500 367.0 367.0 35.0
TLV5606IDR SOIC D 8 2500 367.0 367.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 16-Aug-2012
Pack Materials-Page 2
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