SLAS259B - DECEMBER 1999 - REVISED APRIL 2004 D Buffered High-Impedance Reference Input D Voltage Output Range . . . 2 Times the features D 10-Bit Voltage Output DAC D Programmable Settling Time vs Power D D D D Reference Input Voltage D Monotonic Over Temperature D Available in MSOP Package Consumption 3 s in Fast Mode 9 s in Slow Mode Ultra Low Power Consumption: 900 W Typ in Slow Mode at 3 V 2.1 mW Typ in Fast Mode at 3 V Differential Nonlinearity . . . <0.2 LSB Typ Compatible With TMS320 and SPI Serial Ports Power-Down Mode (10 nA) applications D D D D D Digital Servo Control Loops Digital Offset and Gain Adjustment Industrial Process Control Machine and Motion Control Devices Mass Storage Devices D OR DGK PACKAGE (TOP VIEW) description The TLV5606 is a 10-bit voltage output digital-toanalog converter (DAC) with a flexible 4-wire serial interface. The 4-wire serial interface allows glueless interface to TMS320, SPI, QSPI, and Microwire serial ports. The TLV5606 is programmed with a 16-bit serial string containing 4 control and 10 data bits. Developed for a wide range of supply voltages, the TLV5606 can operate from 2.7 V to 5.5 V. DIN SCLK CS FS 1 8 2 7 3 6 4 5 VDD OUT REFIN AGND The resistor string output voltage is buffered by a x2 gain rail-to-rail output buffer. The buffer features a Class AB output stage to improve stability and reduce settling time. The settling time of the DAC is programmable to allow the designer to optimize speed versus power dissipation. The settling time is chosen by the control bits within the 16-bit serial input string. A high-impedance buffer is integrated on the REFIN terminal to reduce the need for a low source impedance drive to the terminal. Implemented with a CMOS process, the TLV5606 is designed for single supply operation from 2.7 V to 5.5 V. The device is available in an 8-terminal SOIC package. The TLV5606C is characterized for operation from 0C to 70C. The TLV5606I is characterized for operation from - 40C to 85C. AVAILABLE OPTIONS PACKAGE TA SMALL OUTLINE (D) 0C to 70C TLV5606CD -40C to 85C TLV5606ID MSOP (DGK) TLV5606CDGK TLV5606IDGK Available in tape and reel as the TLV5606CDR, TLV5606IDR, TLV5606CDGKR, and the TLV5606IDGKR Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright 2002-2004, Texas Instruments Incorporated !"# $ %&'# "$ (&)*%"# +"#' +&%#$ %! # $('%%"#$ (' #,' #'!$ '-"$ $#&!'#$ $#"+"+ .""#/ +&%# (%'$$0 +'$ # '%'$$"*/ %*&+' #'$#0 "** (""!'#'$ WWW.TI.COM 1 SLAS259B - DECEMBER 1999 - REVISED APRIL 2004 functional block diagram _ 6 + REFIN 12 Serial Input Register 1 DIN 10 10-Bit Data Latch 2 SCLK 16 Cycle Timer 3 CS 4 FS 10 x2 7 OUT Update 2 Power-On Reset Speed/Power-Down Logic Terminal Functions TERMINAL NAME 2 NO. I/O DESCRIPTION AGND 5 Analog ground CS 3 I Chip select. Digital input used to enable and disable inputs, active low. DIN 1 I Serial digital data input FS 4 I Frame sync. Digital input used for 4-wire serial interfaces such as the TMS320 DSP interface. OUT 7 O DAC analog output REFIN 6 I Reference analog input voltage SCLK 2 I Serial digital clock input VDD 8 Positive power supply WWW.TI.COM SLAS259B - DECEMBER 1999 - REVISED APRIL 2004 absolute maximum ratings over operating free-air temperature range (unless otherwise noted) Supply voltage (VDD to AGND) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V Reference input voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.3 V to VDD + 0.3 V Digital input voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.3 V to VDD + 0.3 V Operating free-air temperature range, TA: TLV5606C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0C to 70C TLV5606I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40C to 85C Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65C to 150C Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260C Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. recommended operating conditions Supply voltage, VDD VDD = 5 V VDD = 3 V High-level digital input voltage, VIH DVDD = 2.7 V DVDD = 5.5 V Low-level digital input voltage, VIL DVDD = 2.7 V DVDD = 5.5 V Reference voltage, Vref to REFIN terminal Reference voltage, Vref to REFIN terminal MIN NOM MAX 4.5 5 5.5 V 2.7 3 3.3 V 2 V 2.4 VDD = 5 V (see Note 1) VDD = 3 V (see Note 1) V AGND 2.048 AGND 1.024 2 10 Load resistance, RL UNIT 0.6 V 1 V VDD -1.5 VDD -1.5 V V k Load capacitance, CL 100 pF Clock frequency, fCLK 20 MHz 0 70 C -40 85 C Operating free-air temperature, TA TLV5606C TLV5606I NOTE 1: Due to the x2 output buffer, a reference input voltage VDD/2 causes clipping of the transfer function. electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) power supply PARAMETER IDD TEST CONDITIONS VDD = 5 V, VREF = 2.048 V, No load, All inputs = AGND or VDD, DAC latch = 0x800 Power supply current VDD = 3 V, VREF = 1.024 V No load, All inputs = AGND or VDD, DAC latch = 0x800 MIN TYP MAX UNIT Fast 0.9 1.35 mA Slow 0.4 0.6 mA Fast 0.7 1.1 mA Slow 0.3 0.45 mA Power down supply current (see Figure 12) PSRR Power supply rejection ratio 10 Zero scale See Note 2 -80 Full scale See Note 3 -80 Power on threshold voltage, POR 2 nA dB V NOTES: 2. Power supply rejection ratio at zero scale is measured by varying VDD and is given by: PSRR = 20 log [(EZS(VDDmax) - EZS(VDDmin))/VDDmax] 3. Power supply rejection ratio at full scale is measured by varying VDD and is given by: PSRR = 20 log [(EG(VDDmax) - EG(VDDmin))/VDDmax] WWW.TI.COM 3 SLAS259B - DECEMBER 1999 - REVISED APRIL 2004 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) (continued) static DAC specifications RL = 10 k, CL = 100 pF PARAMETER TEST CONDITIONS MIN TYP Resolution MAX UNIT 10 10 bits INL Integral nonlinearity See Note 4 0.5 1.5 LSB DNL Differential nonlinearity See Note 5 0.2 1 LSB EZS Zero-scale error (offset error at zero scale) See Note 6 Zero-scale-error temperature coefficient See Note 7 Gain error See Note 8 Gain-error temperature coefficient See Note 9 EG 10 10 mV ppm/C 0.6 10 % of FS voltage ppm/C NOTES: 4. The relative accuracy or integral nonlinearity (INL) sometimes referred to as linearity error, is the maximum deviation of the output from the line between zero and full scale excluding the effects of zero code and full-scale errors. Tested from code 10 to code 1023. 5. The differential nonlinearity (DNL) sometimes referred to as differential error, is the difference between the measured and ideal 1 LSB amplitude change of any two adjacent codes. Monotonic means the output voltage changes in the same direction (or remains constant) as a change in the digital input code. Tested from code 10 to code 1023. 6. Zero-scale error is the deviation from zero voltage output when the digital input code is zero. 7. Zero-scale-error temperature coefficient is given by: EZS TC = [EZS (Tmax) - EZS (Tmin)]/Vref x 106/(Tmax - Tmin). 8. Gain error is the deviation from the ideal output (2Vref - 1 LSB) with an output load of 10 k excluding the effects of the zero-error. 9. Gain temperature coefficient is given by: EG TC = [EG(Tmax) - EG (Tmin)]/Vref x 106/(Tmax - Tmin). output specifications PARAMETER VO Voltage output range Output load regulation accuracy TEST CONDITIONS MIN RL = 10 k TYP 0 RL = 2 k, vs 10 k MAX AVDD-0.1 0.25 0.1 UNIT V % of FS voltage reference input (REF) PARAMETER VI RI Input voltage range CI Input capacitance TEST CONDITIONS MIN TYP 0 MAX VDD-1.5 Input resistance 10 Slow Reference input bandwidth REFIN = 0.2 Vpp + 1.024 V dc Reference feed through REFIN = 1 Vpp at 1 kHz + 1.024 V dc (see Note 10) UNIT V M 5 pF 525 kHz 1.3 MHz -75 dB Fast NOTE 10: Reference feedthrough is measured at the DAC output with an input code = 0x000. digital inputs PARAMETER IIH IIL High-level digital input current CI Input capacitance 4 Low-level digital input current TEST CONDITIONS MIN TYP VI = VDD VI = 0 V 3 WWW.TI.COM MAX UNIT 1 A 1 A pF SLAS259B - DECEMBER 1999 - REVISED APRIL 2004 operating characteristics over recommended operating free-air temperature range (unless otherwise noted) analog output dynamic performance PARAMETER TEST CONDITIONS ts(FS) Output settling time, full scale RL = 10 k, See Note 11 CL = 100 pF, ts(CC) Output settling time, code to code RL = 10 k, See Note 12 CL = 100 pF, SR S/N Slew rate RL = 10 k, See Note 13 CL = 100 pF, Glitch energy Code transition from 0x7FF to 0x800 MIN TYP MAX Fast 3 5.5 Slow 9 20 Fast 1 s Slow 2 s Fast 3.6 Slow 0.9 Signal to noise S/(N+D) Signal to noise + distortion THD Total harmonic distortion fs = 400 KSPS fout = 1.1 kHz, RL = 10 k, CL = 100 pF, k BW = 20 kHz Spurious free dynamic range UNIT ss V/ s V/s 10 nV-s 62 dB 60 dB -61 dB 68 dB NOTES: 11. Settling time is the time for the output signal to remain within 0.5 LSB of the final measured value for a digital input code change of 0x080 to 0x3FF or 0x3FF to 0x080. Not tested, ensured by design. 12. Settling time is the time for the output signal to remain within 0.5 LSB of the final measured value for a digital input code change of one count. Code change from 0x1FF to 0x200. Not tested, ensured by design. 13. Slew rate determines the time it takes for a change of the DAC output from 10% to 90% full-scale voltage. digital input timing requirements MIN tsu(CS-FS) tsu(FS-CK) Setup time, CS low before FS Setup time, FS low before first negative SCLK edge NOM MAX UNIT 10 ns 8 ns tsu(C16-FS) Setup time, sixteenth negative edge after FS low on which bit D0 is sampled before rising edge of FS 10 ns tsu(C16-CS) Setup time, sixteenth positive SCLK edge (first positive after D0 is sampled) before CS rising edge. If FS is used instead of the sixteenth positive edge to update the DAC, then the setup time is between the FS rising edge and CS rising edge. 10 ns twH twL Pulse duration, SCLK high 25 ns Pulse duration, SCLK low 25 ns tsu(D) Setup time, data ready before SCLK falling edge 8 ns th(D) twH(FS) Hold time, data held valid after SCLK falling edge 5 ns 20 ns Pulse duration, FS high WWW.TI.COM 5 SLAS259B - DECEMBER 1999 - REVISED APRIL 2004 PARAMETER MEASUREMENT INFORMATION IIIII IIIII IIII IIII SCLK 1 2 tsu(D) DIN twH twL 3 4 5 15 16 th(D) D15 D14 D13 D12 tsu(FS-CK) D1 D0 tsu(C16-CS) tsu(CS-FS) CS twH(FS) tsu(C16-FS) FS Figure 1. Timing Diagram 6 III III IIII IIII WWW.TI.COM SLAS259B - DECEMBER 1999 - REVISED APRIL 2004 TYPICAL CHARACTERISTICS OUTPUT VOLTAGE vs LOAD CURRENT OUTPUT VOLTAGE vs LOAD CURRENT 2.004 3 V Fast Mode, SOURCE 1.998 1.996 1.994 5 V Slow Mode, SOURCE 4.005 VO - Output Voltage - V VO - Output Voltage - V 2.002 2 4.01 VDD = 3 V, Vref = 1 V, Full Scale 3 V Slow Mode, SOURCE 1.992 4 5 V Fast Mode, SOURCE 3.995 3.99 3.985 3.98 1.990 3.975 0 0.01 0.02 0.05 0.1 0.2 0.5 1 2 0 Load Current - mA 0.02 0.04 0.1 0.2 0.4 1 Load Current - mA Figure 2 2 4 Figure 3 OUTPUT VOLTAGE vs LOAD CURRENT OUTPUT VOLTAGE vs LOAD CURRENT 0.2 0.35 VDD = 3 V, Vref = 1 V, Zero Code 0.18 VDD = 5 V, Vref = 2 V, Zero Code 0.3 0.16 0.14 VO - Output Voltage - V VO - Output Voltage - V VDD = 5 V, Vref = 2 V, Full Scale 3 V Slow Mode, SINK 0.12 0.1 0.08 3 V Fast Mode, SINK 0.06 0.25 5 V Slow Mode, SINK 0.2 0.15 5 V Fast Mode, SINK 0.1 0.04 0.05 0.02 0 0 0 0.01 0.02 0.05 0.1 0.2 0.5 Load Current - mA 1 2 0 Figure 4 0.02 0.04 0.1 0.2 0.4 1 Load Current - mA 2 4 Figure 5 WWW.TI.COM 7 SLAS259B - DECEMBER 1999 - REVISED APRIL 2004 TYPICAL CHARACTERISTICS SUPPLY CURRENT vs FREE-AIR TEMPERATURE SUPPLY CURRENT vs FREE-AIR TEMPERATURE 1 1 VDD = 5 V, Vref = 2 V, Full Scale I DD - Supply Current - mA I DD - Supply Current - mA VDD = 3 V, Vref = 1 V, Full Scale 0.8 Fast Mode 0.6 0.4 Fast Mode 0.8 0.6 0.4 Slow Mode Slow Mode 0.2 -55 -40 85 -25 0 25 40 70 TA - Free-Air Temperature - C 0.2 -55 -40 125 Figure 6 TOTAL HARMONIC DISTORTION vs FREQUENCY 0 0 Vref = 1 V dc + 1 V p/p Sinewave, Output Full Scale -10 THD - Total Harmonic Distortion - dB THD - Total Harmonic Distortion - dB 125 Figure 7 TOTAL HARMONIC DISTORTION vs FREQUENCY -20 -30 --40 -50 -60 Fast Mode -70 -80 0 5 10 20 30 50 100 f - Frequency - kHz Vref = 1 V dc + 1 V p/p Sinewave, Output Full Scale -10 -20 -30 --40 -50 -60 Slow Mode -70 -80 0 5 10 20 30 f - Frequency - kHz Figure 8 8 85 -25 0 25 40 70 TA - Free-Air Temperature - C Figure 9 WWW.TI.COM 50 100 SLAS259B - DECEMBER 1999 - REVISED APRIL 2004 TYPICAL CHARACTERISTICS Vref = 1 V dc + 1 V p/p Sinewave, Output Full Scale -10 TOTAL HARMONIC DISTORTION AND NOISE vs FREQUENCY THD - Total Harmonic Distortion And Noise - dB 0 -20 -30 --40 -50 Fast Mode -60 -70 -80 0 Vref = 1 V dc + 1 V p/p Sinewave, Output Full Scale -10 -20 -30 --40 -50 Slow Mode -60 -70 -80 0 5 10 30 20 50 100 0 5 f - Frequency - kHz 10 20 30 50 100 f - Frequency - kHz Figure 10 Figure 11 SUPPLY CURRENT vs TIME (WHEN ENTERING POWER-DOWN MODE) 900 800 I DD - Supply Current - A THD - Total Harmonic Distortion And Noise - dB TOTAL HARMONIC DISTORTION AND NOISE vs FREQUENCY 700 600 500 400 300 200 100 0 0 100 200 300 400 500 600 700 800 900 1000 T - Time - ns Figure 12 WWW.TI.COM 9 SLAS259B - DECEMBER 1999 - REVISED APRIL 2004 TYPICAL CHARACTERISTICS INL - Integral Nonlinearity - LSB INTEGRAL NONLINEARITY ERROR 1.0 0.5 0.0 -0.5 -1.0 0 512 1024 Digital Code Figure 13 DNL - Differential Nonlinearity - LSB DIFFERENTIAL NONLINEARITY ERROR 0.20 0.16 0.12 0.08 0.04 0.00 -0.04 -0.08 -0.12 -0.16 -0.20 0 512 Digital Code Figure 14 10 WWW.TI.COM 1024 SLAS259B - DECEMBER 1999 - REVISED APRIL 2004 APPLICATION INFORMATION general function The TLV5606 is a 10-bit single supply DAC based on a resistor string architecture. The device consists of a serial interface, speed and power-down control logic, a reference input buffer, a resistor string, and a rail-to-rail output buffer. The output voltage (full scale determined by external reference) is given by: 2 REF CODE [V] 2n where REF is the reference voltage and CODE is the digital input value within the range of 010 to 2n-1, where n = 10 (bits). The 16-bit data word, consisting of control bits and the new DAC value, is illustrated in the data format section. A power-on reset initially resets the internal latches to a defined state (all bits zero). serial interface Explanation of data transfer: First, the device has to be enabled with CS set to low. Then, a falling edge of FS starts shifting the data bit-per-bit (starting with the MSB) to the internal register on the falling edges of SCLK. After 16 bits have been transferred or FS rises, the content of the shift register is moved to the DAC latch which updates the voltage output to the new level. The serial interface of the TLV5606 can be used in two basic modes: D Four wire (with chip select) D Three wire (without chip select) Using chip select (four wire mode), it is possible to have more than one device connected to the serial port of the data source (DSP or microcontroller). The interface is compatible with the TMS320 family. Figure 15 shows an example with two TLV5606s connected directly to a TMS320 DSP. TLV5606 CS FS DIN SCLK TLV5606 CS FS DIN SCLK TMS320 DSP XF0 XF1 FSX DX CLKX Figure 15. TMS320 Interface WWW.TI.COM 11 SLAS259B - DECEMBER 1999 - REVISED APRIL 2004 APPLICATION INFORMATION serial interface (continued) If there is no need to have more than one device on the serial bus, then CS can be tied low. Figure 16 shows an example of how to connect the TLV5606 to a TMS320, SPI, or Microwire port using only three pins. TMS320 DSP TLV5606 FSX SPI FS DIN DX CLKX TLV5606 FS DIN SS MOSI SCLK SCLK Microwire FS DIN I/O SO SK SCLK CS TLV5606 SCLK CS CS Figure 16. Three-Wire Interface Notes on SPI and Microwire: Before the controller starts the data transfer, the software has to generate a falling edge on the I/O pin connected to FS. If the word width is 8 bits (SPI and Microwire), two write operations must be performed to program the TLV5606. After the write operation(s), the DAC output is updated automatically on the next positive clock edge following the sixteenth falling clock edge. serial clock frequency and update rate The maximum serial clock frequency is given by: f SCLKmax + t wH(min) 1 )t + 20 MHz wL(min) The maximum update rate is: f UPDATEmax + 1 wH(min) ) twL(min) + 1.25 MHz 16 t The maximum update rate is a theoretical value for the serial interface, since the settling time of the TLV5606 has to be considered also. data format The 16-bit data word for the TLV5606 consists of two parts: D Control bits D New DAC value D15 D14 D13 D12 X SPD PWR X X: don't care SPD: Speed control bit. PWR: Power control bit. (D15 . . . D12) (D11 . . . D2) D11 1 fast mode 1 power down D10 D9 D8 D7 D6 D5 New DAC value (10 bits) 0 slow mode 0 normal operation In power-down mode, all amplifiers within the TLV5606 are disabled. 12 WWW.TI.COM D4 D3 D2 D1 D0 0 0 SLAS259B - DECEMBER 1999 - REVISED APRIL 2004 APPLICATION INFORMATION TLV5606 interfaced to TMS320C203 DSP hardware interfacing Figure 17 shows an example how to connect the TLV5606 to a TMS320C203 DSP. The serial interface of the TLV5606 is ideally suited to this configuration, using a maximum of four wires to make the necessary connections. In applications where only one synchronous serial peripheral is used, the interface can be simplified even further by pulling CS low all the time as shown in the figure. TMS320C203 TLV5606 FS FS DX DIN VDD SCLK CLKX REF OUT REFIN CS AGND RLOAD Figure 17. TLV5606 to DSP Interface software No setup procedure is needed to access the TLV5606. The output voltage can be set using just a single command. out data_addr, SDTR where data_addr points to an address location holding the control bits and the 12 data bits providing the output voltage data. SDTR is the address of the transmit FIFO of the synchronous serial port. The following code shows how to use the timer of the TMS320C203 as a time base to generate a voltage ramp with the TLV5606. A timer interrupt is generated every 205 s. The corresponding interrupt service routine increments the output code (stored at 0x0064) for the DAC, adds the DAC control bits to the four most significant bits, and writes the new code to the TLV5606. The resulting period of the saw waveform is: = 4096 x 205 E-6 s = 0.84 s ;*************************************************************************************** ;* Title : Ramp generation with TLV5606 * ;* Version : 1.0 * ;* DSP : TI TMS320C203 * ;* (1998) Texas Instruments Incorporated * ;*************************************************************************************** ;----------- I/O and memory mapped regs ------------ .include "regs.asm" ;----------- vectors ------------------------------- .ps 0h b start b INT1 b INT23 b TIM_ISR WWW.TI.COM 13 SLAS259B - DECEMBER 1999 - REVISED APRIL 2004 APPLICATION INFORMATION ;*************************************************************************************** ;* Main Program ;*************************************************************************************** .ps 1000h .entry start: ; disable interrupts setc INTM ; disable maskable interrupts splk #0ffffh, IFR splk #0004h, IMR ; set up the timer to interrupt ever 205uS splk #0000h, 60h splk #00FFh, 61h out 61h, PRD out 60h, TIM splk #0c2fh, 62h out 62h, TCR ; Configure SSP to use internal clock, internal frame sync and burst mode splk #0CC0Eh, 63h out 63h, SSPCR splk #0CC3Eh, 63h out 63h, SSPCR splk #0000h, 64h ; set initial DAC value ; enable interrupts clrc INTM ; enable maskable interrupts ; loop forever! next: idle b next ;wait for interrupt ; all else fails stop here done: b done ;hang there ;*************************************************************************************** ;* Interrupt Service Routines ;*************************************************************************************** INT1: ret ;do nothing and return INT23: ret ;do nothing and return TIM_ISR: lacl add and sacl or sacl out 64h #4h #0FFCh 64h #4000h 65h 65h, SDTR ; ; ; ; ; ; ; restore counter value to ACC increment DAC value mask 4 MSBs store 12 bit counter value set DAC control bits store DAC value send data clrc ret intm ; re-enable interrupts .END 14 WWW.TI.COM SLAS259B - DECEMBER 1999 - REVISED APRIL 2004 APPLICATION INFORMATION TLV5606 interfaced to MCS51 microcontroller hardware interfacing Figure 18 shows an example of how to connect the TLV5606 to an MCS51 compatible microcontroller. The serial DAC input data and external control signals are sent via I/O port 3 of the controller. The serial data is sent on the RxD line, with the serial clock output on the TxD line. P3.4 and P3.5 are configured as outputs to provide the chip select and frame sync signals for the TLV5606. MCS51 Controller TLV5606 RxD SDIN TxD SCLK P3.4 P3.5 CS FS VDD OUT REF REFIN RLOAD AGND Figure 18. TLV5606 to MCS51 Controller Interface software The example program puts out a sine wave on the OUT pin. The on-chip timer is used to generate interrupts at a fixed frequency. The related interrupt service routine fetches and writes the next sample to the DAC. The samples are stored in a lookup table, which describes one full period of a sine wave. The serial port of the controller is used in mode 0, which transmits 8 bits of data on RxD, accompanied by a synchronous clock on TxD. Two writes concatenated together are required to write a complete word to the TLV5606. The CS and FS signals are provided in the required fashion through control of I/O port 3, which has bit addressable outputs. ;*************************************************************************************** ;* Title : Ramp generation with TLV5606 * ;* Version : 1.0 * * ;* MCU : INTEL MCS51 ;* (1998) Texas Instruments Incorporated * ;*************************************************************************************** ;--------------------------------------------------------------------------------------- ; Program function declaration ;--------------------------------------------------------------------------------------- NAME GENSINE MAIN ISR SINTBL VAR1 STACK SEGMENT SEGMENT SEGMENT SEGMENT SEGMENT CODE CODE CODE DATA IDATA ;--------------------------------------------------------------------------------------- ; Code start at address 0, jump to start ;--------------------------------------------------------------------------------------- CSEG AT 0 MCS is a registered trademark of Intel Corporation WWW.TI.COM 15 SLAS259B - DECEMBER 1999 - REVISED APRIL 2004 APPLICATION INFORMATION LJMP start ; Execution starts at address 0 on power-up. ;--------------------------------------------------------------------------------------- ; Code in the timer0 interrupt vector ;--------------------------------------------------------------------------------------- CSEG AT 0BH LJMP timer0isr ; Jump vector for timer 0 interrupt is 000Bh ;--------------------------------------------------------------------------------------- ; Define program variables ;--------------------------------------------------------------------------------------- RSEG VAR1 rolling_ptr: DS 1 ;--------------------------------------------------------------------------------------- ; Interrupt service routine for timer 0 interrupts ;--------------------------------------------------------------------------------------- RSEG ISR timer0isr: PUSH PUSH PSW ACC CLR CLR T0 ; ; ; ; T1 ; set CSB low ; set FS low The signal to be output on the dac is a sine function. One cycle of a sine wave is held in a table @ sinevals as 32 samples of msb, lsb pairs (64 bytes). The pointer, rolling_ptr, rolls round the table of samples incrementing by 2 bytes (1 sample) on each interrupt (at the end of this routine). MOV MOV DPTR,#sinevals ; set DPTR to the start of the table of sine signal values A,rolling_ptr ; ACC loaded with the pointer into the sine table MOVC ORL MOV A,@A+DPTR A, #00H SBUF,A ; get msb from the table ; set control bits ; send out msb of data word MOV A,rolling_ptr ; move rolling pointer in to ACC INC A ; increment ACC holding the rolling pointer MOVC A,@A+DPTR ; which is the lsb of this sample, now in ACC MSB_TX: JNB CLR MOV TI, MSB_TX TI SBUF,A ; wait for transmit to complete ; clear for new transmit ; and send out the lsb LSB_TX: JNB SETB CLR TI, LSB_TX T1 TI ; wait for lsb transmit to complete ; set FS = 1 ; clear for new transmit MOV INC INC ANL MOV A,rolling_ptr A A A,#03FH rolling_ptr,A ; load ACC with rolling pointer ; increment the ACC twice, to get next sample SETB T0 ; CSB high POP POP ACC PSW ; wrap back round to 0 if >64 ; move value held in ACC back to the rolling pointer RETI ;------------------------------------------------------------------------------- ; Set up stack ;------------------------------------------------------------------------------- 16 WWW.TI.COM SLAS259B - DECEMBER 1999 - REVISED APRIL 2004 APPLICATION INFORMATION RSEG STACK DS 10h ; 16 Byte Stack! ;------------------------------------------------------------------------------- ; Main Program ;------------------------------------------------------------------------------- RSEG start: MOV MAIN SP,#STACK-1 ; first set Stack Pointer CLR MOV MOV MOV SETB SETB A SCON,A TMOD,#02H TH0,#0C8H T1 T0 ; ; ; ; ; SETB SETB ET0 EA ; enable timer 0 interrupts ; enable all interrupts MOV SETB rolling_ptr,A TR0 set set set set set serial port 0 to mode 0 timer 0 to mode 2 - auto-reload TH0 for 16.67 kHs interrupts FS = 1 CSB = 1 ; set rolling pointer to 0 ; start timer 0 always: SJMP always ; while(1) ! RET ;------------------------------------------------------------------------------- ; Table of 32 sine wave samples used as DAC data ;------------------------------------------------------------------------------- RSEG SINTBL sinevals: DW 01000H DW 0903CH DW 05094H DW 0305CH DW 0B084H DW 070C8H DW 0F0E0H DW 0F066H DW 0F038H DW 0F06CH DW 0F0E0H DW 070C8H DW 0B084H DW 0305CH DW 05094H DW 0903CH DW 01000H DW 06020H DW 0A0E8H DW 0C060H DW 040F8H DW 080B4H DW 0009CH DW 00050H DW 00024H DW 00050H DW 0009CH DW 080B4H DW 040F8H DW 0C060H DW 0A0E8H DW 06020H END WWW.TI.COM 17 SLAS259B - DECEMBER 1999 - REVISED APRIL 2004 APPLICATION INFORMATION linearity, offset, and gain error using single ended supplies When an amplifier is operated from a single supply, the voltage offset can still be either positive or negative. With a positive offset, the output voltage changes on the first code change. With a negative offset, the output voltage may not change with the first code, depending on the magnitude of the offset voltage. The output amplifier attempts to drive the output to a negative voltage. However, because the most negative supply rail is ground, the output cannot drive below ground and clamps the output at 0 V. The output voltage then remains at zero until the input code value produces a sufficient positive output voltage to overcome the negative offset voltage, resulting in the transfer function shown in Figure 19. Output Voltage 0V DAC Code Negative Offset Figure 19. Effect of Negative Offset (Single Supply) This offset error, not the linearity error, produces this breakpoint. The transfer function would have followed the dotted line if the output buffer could drive below the ground rail. For a DAC, linearity is measured between zero-input code (all inputs 0) and full-scale code (all inputs 1) after offset and full scale are adjusted out or accounted for in some way. However, single supply operation does not allow for adjustment when the offset is negative due to the breakpoint in the transfer function. So the linearity is measured between full-scale code and the lowest code that produces a positive output voltage. power-supply bypassing and ground management Printed-circuit boards that use separate analog and digital ground planes offer the best system performance. Wire-wrap boards do not perform well and should not be used. The two ground planes should be connected together at the low-impedance power-supply source. The best ground connection may be achieved by connecting the DAC AGND terminal to the system analog ground plane, making sure that analog ground currents are well managed and there are negligible voltage drops across the ground plane. A 0.1-F ceramic-capacitor bypass should be connected between VDD and AGND and mounted with short leads as close as possible to the device. Use of ferrite beads may further isolate the system analog supply from the digital power supply. Figure 20 shows the ground plane layout and bypassing technique. Analog Ground Plane 1 8 2 7 3 6 4 5 0.1 F Figure 20. Power-Supply Bypassing 18 WWW.TI.COM SLAS259B - DECEMBER 1999 - REVISED APRIL 2004 APPLICATION INFORMATION definitions of specifications and terminology integral nonlinearity (INL) The relative accuracy or integral nonlinearity (INL), sometimes referred to as linearity error, is the maximum deviation of the output from the line between zero and full scale excluding the effects of zero code and full-scale errors. differential nonlinearity (DNL) The differential nonlinearity (DNL), sometimes referred to as differential error, is the difference between the measured and ideal 1 LSB amplitude change of any two adjacent codes. Monotonic means the output voltage changes in the same direction (or remains constant) as a change in the digital input code. zero-scale error (EZS) Zero-scale error is defined as the deviation of the output from 0 V at a digital input value of 0. gain error (EG) Gain error is the error in slope of the DAC transfer function. signal-to-noise ratio + distortion (S/N+D) S/N+D is the ratio of the rms value of the output signal to the rms sum of all other spectral components below the Nyquist frequency, including harmonics but excluding dc. The value for S/N+D is expressed in decibels. spurious free dynamic range (SFDR) SFDR is the difference between the rms value of the output signal and the rms value of the largest spurious signal within a specified bandwidth. The value for SFDR is expressed in decibels. total harmonic distortion (THD) THD is the ratio of the rms sum of the first six harmonic components to the rms value of the fundamental signal and is expressed in decibels. WWW.TI.COM 19 PACKAGE OPTION ADDENDUM www.ti.com 16-Aug-2012 PACKAGING INFORMATION Orderable Device (1) Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/ Ball Finish MSL Peak Temp TLV5606CD ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLV5606CDG4 ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLV5606CDGK ACTIVE VSSOP DGK 8 80 Green (RoHS & no Sb/Br) CU NIPDAUAGLevel-1-260C-UNLIM TLV5606CDGKG4 ACTIVE VSSOP DGK 8 80 Green (RoHS & no Sb/Br) CU NIPDAUAGLevel-1-260C-UNLIM TLV5606CDGKR ACTIVE VSSOP DGK 8 2500 Green (RoHS & no Sb/Br) CU NIPDAUAGLevel-1-260C-UNLIM TLV5606CDGKRG4 ACTIVE VSSOP DGK 8 2500 Green (RoHS & no Sb/Br) CU NIPDAUAGLevel-1-260C-UNLIM TLV5606CDR ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLV5606CDRG4 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLV5606ID ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLV5606IDG4 ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLV5606IDGK ACTIVE VSSOP DGK 8 80 Green (RoHS & no Sb/Br) CU NIPDAUAGLevel-1-260C-UNLIM TLV5606IDGKG4 ACTIVE VSSOP DGK 8 80 Green (RoHS & no Sb/Br) CU NIPDAUAGLevel-1-260C-UNLIM TLV5606IDGKR ACTIVE VSSOP DGK 8 2500 Green (RoHS & no Sb/Br) CU NIPDAUAGLevel-1-260C-UNLIM TLV5606IDGKRG4 ACTIVE VSSOP DGK 8 2500 Green (RoHS & no Sb/Br) CU NIPDAUAGLevel-1-260C-UNLIM TLV5606IDR ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLV5606IDRG4 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM The marketing status values are defined as follows: Addendum-Page 1 (3) Samples (Requires Login) PACKAGE OPTION ADDENDUM www.ti.com 16-Aug-2012 ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 16-Aug-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device TLV5606CDGKR Package Package Pins Type Drawing VSSOP SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant DGK 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 TLV5606CDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 TLV5606IDGKR VSSOP DGK 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 TLV5606IDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 16-Aug-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TLV5606CDGKR VSSOP DGK 8 2500 367.0 367.0 35.0 TLV5606CDR SOIC D 8 2500 367.0 367.0 35.0 TLV5606IDGKR VSSOP DGK 8 2500 367.0 367.0 35.0 TLV5606IDR SOIC D 8 2500 367.0 367.0 35.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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