SEMICONDUCTOR
1
Features
• Advanced 0.6 micron CMOS Technology
• These Devices are High-speed, Low Power Devices
with High Current Drive
•V
CC = 5V ±10%
• Hysteresis on All Inputs
• CD74FCT16501T
- High Output Drive: IOH = -32mA; IOL = 64mA
- Power Off Disable Outputs Permit "Live Insertion"
- Typical VOLP (Output Ground Bounce) < 1.0V at
VCC = 5V, TA = 25oC
• CD74FCT162501T
- Balanced Output Drivers: ±24mA
- Reduced System Switching Noise
- Typical VOLP (Output Ground Bounce) < 0.6V at
VCC = 5V, TA = 25oC
Description
These devices are 18-bit are registered bus transceivers
designed with D-type latches and flip-flops to allow data flow
in transparent, latched, and clocked modes. The Output
Enable (OEAB and OEBA, Latch Enable (LEAB and LEBA)
and Clock (CLKAB and CLKBA) inputs control the data flow
in each direction. When LEAB is HIGH, the device operates
in transparent mode for A-to-B data flow. When LEAB is
LOW, the A data is latched if CLKAB is held at a HIGH or
LOW logic level. The A bus data is stored in the latch/flip-
flop on the HIGH-to-LOW transition of CLKAB, if LEAB is
LOW. OEAB performs the output enable function on the B
por t. Data flow from B por t to A por t is similar using OEBA,
LEBA and CLKBA. These high-speed, low power devices
offer a flow-through organization for ease of board layout.
The CD74FCT16501T output buffers are designed with a
Power-Off disable allowing "live insertion" of boards when
used as backplane drivers.
The CD74FCT162501T has 24 mA balanced output drivers.
It is designed with current limiting resistors at its outputs to
control the output edge rate resulting in low er ground bounce
and undershoot. This eliminates the need for external termi-
nating resistors for most interface applications.
Ordering Information
PART NUMBER
TEMP.
RANGE
(oC) PACKAGE PKG.
NO.
CD74FCT16501ATMT -40 to 85 56 Ld TSSOP M56.240-P
CD74FCT16501ATSM -40 to 85 56 Ld SSOP M56.300-P
CD74FCT16501CTMT -40 to 85 56 Ld TSSOP M56.240-P
CD74FCT16501CTSM -40 to 85 56 Ld SSOP M56.300-P
CD74FCT16501DTMT -40 to 85 56 Ld TSSOP M56.240-P
CD74FCT16501DTSM -40 to 85 56 Ld SSOP M56.300-P
CD74FCT16501ETMT -40 to 85 56 Ld TSSOP M56.240-P
CD74FCT16501ETSM -40 to 85 56 Ld SSOP M56.300-P
CD74FCT162501ATMT -40 to 85 56 Ld TSSOP M56.240-P
CD74FCT162501ATSM -40 to 85 56 Ld SSOP M56.300-P
CD74FCT162501CTMT -40 to 85 56 Ld TSSOP M56.240-P
CD74FCT162501CTSM -40 to 85 56 Ld SSOP M56.300-P
CD74FCT162501DTMT -40 to 85 56 Ld TSSOP M56.240-P
CD74FCT162501DTSM -40 to 85 56 Ld SSOP M56.300-P
CD74FCT162501ETMT -40 to 85 56 Ld TSSOP M56.240-P
CD74FCT162501ETSM -40 to 85 56 Ld SSOP M56.300-P
December 1996
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright © Harris Corporation 1996
CD74FCT16501T,
CD74FCT162501T
Fast CMOS 18-Bit Registered Transceiver
File Number 4184.1
2
Pinout
CD74FCT16501T, CD74FCT162501T
(SSOP, TSSOP)
TOP VIEW
56
55
54
53
52
51
50
49
21
9
10
11
12
13
14
15
16
17
18
19
20
22
23
24
25
26
27
28
A4
A5
GND
A6
A7
A8
A9
A10
A11
GND
A12
A13
A14
VCC
A15
A16
GND
A17
OEBA
LEBA
36
48
47
46
45
44
43
42
41
40
39
38
37
35
34
33
32
31
30
29
5
6
7
8
A1
A2
VCC
A3
1
2
3
4
OEAB
LEAB
A0
GND
B4
B5
GND
B6
B7
B8
B9
B10
B11
GND
B12
B13
B14
VCC
B15
B16
GND
B17
CLKBA
GND
B1
B2
VCC
B3
GND
CLKAB
B0
GND
CD74FCT16501T, CD74FCT162501T
3
Functional Block Diagram
TRUTH TABLE (NOTES 1 AND 4)
B0
OEAB
D
C
A0
CLKBA
LEBA
OEBA
LEAB
CLKAB
TO 17 OTHER CHANNELS
D
C
D
C
D
C
INPUTS OUTPUTS
OEAB LEAB CLKAB AXBX
LXXXZ
HHXLL
HHXHH
HL↑LL
HL↑HH
H L L X B (Note 2)
H L H X B (Note 3)
NOTES:
19. A-to-B data flow is shown. B-to-A data flow is similar but uses OEBA, LEBA, and CLKBA.
20. Output level before the indicated steady-state input conditions were established.
21. Output level before the indicated steady-state input conditions wer established, provided that
CLKAB was LOW before LEAB went LOW.
22. H = High Voltage Level
L = Low Voltage Level
Z = High Impedance
↑ = LOW-to-HIGH Transition
CD74FCT16501T, CD74FCT162501T
4
Pin Descriptions
PIN NAME DESCRIPTION
OEAB A-to-B Output Enable Input
OEBA B-to-A Output Enable Input (Active LOW)
LEAB A-to-B Latch Enable Input
LEBA B-to-A Latch Enable Input
CLKAB A-to-B Clock Input
CLKBA B-to-A Clock Input
AXA-to-B Data Inputs or B-to-A
Three-State Outputs (Note 5)
BXB-to-A Data Inputs or A-to-B
Three-State Outputs (Note 5)
GND Ground
VCC Power
CD74FCT16501T, CD74FCT162501T
5
Absolute Maximum Ratings Thermal Information
DC Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7.0V
DC Output Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .120mA
Operating Conditions
Operating Temperature Range. . . . . . . . . . . . . . . . . . -40oC to 85oC
Supply Voltage to Ground Potential
Inputs and VCC Only. . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7.0V
Supply Voltage to Ground Potential
Outputs and D/O Only. . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7.0V
Thermal Resistance (Typical, Note 5) θJA (oC/W)
SOIC Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . ___
SSOP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . ___
Maximum Junction Temperature. . . . . . . . . . . . . . . . . . . . . . . 150oC
Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC
Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . . 300oC
(Lead Tips Only)
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
23. θJA is measured with the component mounted on an evaluation PC board in free air.
Electrical Specifications
PARAMETERS SYMBOL (NOTE 6)
TEST CONDITIONS MIN (NOTE 7)
TYP MAX UNITS
DC ELECTRICAL SPECIFICATIONS Over the Operating Range, TA = -40oC to 85oC, VCC = 5.0V ±10%
Input HIGH Voltage VIH Guaranteed Logic HIGH Level 2.0 - - V
Input LOW Voltage VIL Guaranteed Logic LOW Level - - 0.8 V
Input HIGH Current IIH Standard Input,VCC = Max VIN = VCC --1µA
Input HIGH Current IIH Standard I/O, VCC = Max VIN = VCC --1µA
Input LOW Current IIL Standard Input, VCC = Min VIN = GND - - -1 µA
Input LOW Current IIL Standard I/O, VCC = Min VIN = GND - - -1 µA
High Impedance
Output Current
(Three-State)
(Note 9)
IOZH VCC = Max VOUT = 2.7V - - 1 µA
IOZL VCC = Max VOUT = 0.5V - - -1 µA
Clamp Diode Voltage VIK VCC = Min, IIN = -18mA - -0.7 -1.2 V
Short Circuit Current IOS VCC = Max (Note 8), VOUT = GND -80 -140 -200 mA
Output Drive Current IOVCC = Max (Note 8), VOUT = GND -50 - -180 mA
Input Hysteresis VH- 100 - mV
CD74FCT16501T OUTPUT DRIVE SPECIFICATIONS Over the Operating Range
Output HIGH Voltage VOH VCC = Min, VIN = VIH or VIL IOH = -3.0mA 2.5 3.5 - V
IOH = -15.0mA 2.4 3.5 - V
IOH = -32.0mA 2.0 3.0 - V
Output LOW Voltage VOL VCC = Min, VIN = VIH or VIL IOL = 64mA - 0.2 0.55 V
Power Down Disable IOFF VCC = 0V, VIN or VOUT ≤4.5V - - ±100 µA
CD74FCT162501T OUTPUT DRIVE SPECIFICATIONS Over the Operating Range
Output HIGH Voltage VOH VCC = Min, VIN = VIH or VIL IOH = -24.0mA 2.4 3.3 - V
Output LOW Voltage VOL VCC = Min, VIN = VIH or VIL IOL = 24mA - 0.3 0.55 V
Output LOW Current IODL VCC = 5V, VIN = VIH or VIL, VOUT = 1.5V (Note 10) 60 115 150 mA
Output HIGH Current IODH VCC = 5V, VIN = VIH or VIL, VOUT = 1.5V (Note 10) -60 -115 -150 mA
CAPACITANCE TA = 25oC, f = 1MHz
Input Capacitance
(Note 10) CIN VIN = 0V - 4.5 6 pF
Output Capacitance
(Note 10) COUT VOUT = 0V - 5.5 8 pF
CD74FCT16501T, CD74FCT162501T
6
POWER SUPPLY SPECIFICATIONS
Quiescent Power
Supply Current ICC VCC = Max VIN = GND
or VCC - 0.1 500 µA
Supply Current per
Input at TTL HIGH ∆ICC VCC = Max VIN = 3.4V
(Note 11) - 0.5 1.5 mA
Supply Current per
Input per MHz
(Note 12)
ICCD VCC = Max, Outputs Open
OEAB = OEBA = VCC or GND
One Bit Toggling
50% Duty Cycle
VIN = VCC
VIN = GND - 75 120 µA/
MHz
Total Power Supply
Current (Note 14) ICVCC = Max, Outputs Open
fCP = 10MHz (CLKAB)
50% Duty Cycle
OEAB = OEBA = VCC
LEAB = GND
One Bit Toggling
fI = 5MHz
50% Duty Cycle
VIN = VCC
VIN = GND - 0.8 1.7
(Note 13) mA
VIN = 3.4V
VIN = GND - 1.3 4.2
(Note 13) mA
VCC = Max, Outputs Open
fCP = 10MHz (CLKAB)
50% Duty Cycle
OEAB = OEBA = VCC
LEAB = GND
18 Bits Toggling
fI = 2.5MHz
50% Duty Cycle
VIN = VCC
VIN = GND - 3.8 6.5
(Note 13) mA
VIN = 3.4V
VIN = GND - 8.5 20.8
(Note 13) mA
Switching Specifications Over Operating Range
PARAMETER SYMBOL
(NOTE 15)
TEST
CONDITIONS
AT CT DT ET
UNITS
(NOTE 16)
MIN MAX (NOTE 16)
MIN MAX (NOTE 16)
MIN MAX (NOTE 16)
MIN MAX
CLKAB or CLKBA
Frequency fMAX CL = 50pF
RL = 500Ω- 150 - 150 - 150 - 150 MHz
Propagation Delay
AX to BX or BXto AXtPLH,
tPHL CL = 50pF
RL = 500Ω1.5 5.1 1.5 4.6 1.5 4.1 1.5 3.8 ns
Propagation Delay
LEBA to AX, LEAB to BXtPLH,
tPHL CL = 50pF
RL = 500Ω1.5 5.6 1.5 5.3 1.5 4.6 1.5 4.2 ns
Propagation Delay
CLKBA to AX,
CLKAB to BX
tPLH,
tPHL CL = 50pF
RL = 500Ω1.5 5.6 1.5 5.3 1.5 4.6 1.5 4.2 ns
Output Enable Time
OEBA to AX,
OEAB to Bx
tPZH,
tPZL CL = 50pF
RL = 500Ω1.5 6.0 1.5 5.6 1.5 5.2 1.5 4.8 ns
Output Disable Time
(Note 14)
OEBA to AX, OEAB to BX
tPHZ
tPLZ CL = 50pF
RL = 500Ω1.5 5.6 1.5 5.2 1.5 5.2 1.5 5.2 ns
Setup Time HIGH or LOW
AX to CLKAB,
BX to CLKBA
tSU CL = 50pF
RL = 500Ω3.0 - 3.0 - 3.0 - 2.4 - ns
Hold Time HIGH or LOW
AX to CLKAB,
BX to CLKBA
tHCL = 50pF
RL = 500Ω0-0-0-0-ns
Electrical Specifications (Continued)
PARAMETERS SYMBOL (NOTE 6)
TEST CONDITIONS MIN (NOTE 7)
TYP MAX UNITS
CD74FCT16501T, CD74FCT162501T
7
Setup Time HIGH or
LOW, AX to LEAB,
BX to LEBA, Clock HIGH
tSU CL = 50pF
RL = 500Ω3.0 - 3.0 - 3.0 - 2.0 - ns
Setup Time HIGH or
LOW, AX to LEAB,
BX to LEBA, Clock LOW
tSU CL = 50pF
RL = 500Ω1.5 - 1.5 - 1.5 - 1.5 - ns
Hold Time HIGH or LOW,
Ax to LEAB, Bx to LEBA tHCL = 50pF
RL = 500Ω1.5 - 1.5 - 1.5 - 0.5 - ns
LEAB or LEBA Pulse
Width HIGH (Note 17) tWCL = 50pF
RL = 500Ω3.0 - 3.0 - 3.0 - 3.0 - ns
CLKAB or CLKBA Pulse
Width HIGH or LOW
(Note 17)
tWCL = 50pF
RL = 500Ω3.0 - 3.0 - 3.0 - 3.0 - ns
Output Skew (Note 18) tSK(O) CL = 50pF
RL = 500Ω- 0.5 - 0.5 - 0.5 - 0.5 ns
NOTES:
24. For conditions shown as Max or Min, use appropriate value specified under Electrical Characteristics for the applicable device type.
25. Typical values are at VCC = 5.0V, 25oC ambient and maximum loading.
26. Not more than one output should be shorted at one time. Duration of the test should not exceed one second.
27. This specification does not apply to bi-directional functionalities with Bus Hold.
28. This parameter is determined by device characterization but is not production tested.
29. Per TTL driven input (VIN = 3.4V); all other inputs at VCC or GND.
30. This parameter is not directly testable, but is derived for use in Total Power Supply Calculations.
31. Values for these conditions are examples of the ICC formula. These limits are guaranteed but not tested.
32. IC = IQUIESCENT + IINPUTS + IDYNAMIC
IC = ICC + ∆ICC DHNT + ICCD (fCP/2 + fINI)
ICC = Quiescent Current
∆ICC = Power Supply Current for a TTL High Input (VIN = 3.4V)
DH = Duty Cycle for TTL Inputs High
NT = Number of TTL Inputs at DH
ICCD = Dynamic Current Caused by an Input Transition Pair (HLH or LHL)
fCP = Clock Frequency for Register Devices (Zero for Non-Register Devices)
fI = Input Frequency
NI = Number of Inputs at fI
All currents are in milliamps and all frequencies are in megahertz.
33. See test circuit and wave forms.
34. Minimum limits are guaranteed but not tested on Propagation Delays.
35. This parameter is guaranteed but not production tested.
36. Skew between any two outputs, of the same package, switching in the same direction. This parameter is guaranteed by design.
Switching Specifications Over Operating Range (Continued)
PARAMETER SYMBOL
(NOTE 15)
TEST
CONDITIONS
AT CT DT ET
UNITS
(NOTE 16)
MIN MAX (NOTE 16)
MIN MAX (NOTE 16)
MIN MAX (NOTE 16)
MIN MAX
CD74FCT16501T, CD74FCT162501T
8
CD74FCT16501T, CD74FCT162501T
Test Circuits and Waveforms
NOTE:
37. Pulse Generator for All Pulses: Rate ≤1.0MHz; ZOUT ≤50Ω;
tf, tr≤ 2.5ns. FIGURE 4. TEST CIRCUIT
FIGURE 5. SETUP, HOLD, AND RELEASE TIMING FIGURE 6. PULSE WIDTH
FIGURE 7. ENABLE AND DISABLE TIMING FIGURE 8. PROPAGATION DELAY
DUT
PULSE
GENERATOR
RTCL
50pF
VCC
VOUT
7.0V
500Ω
VIN
500Ω
SWITCH POSITION
TEST SWITCH
tPLZ, tPZL Closed
tPHZ, tPZH, tPLH, tPHL Open
DEFINITIONS:
CL = Load capacitance, includes jig and probe capacitance.
RT = Termination resistance, should be equal to ZOUT of the
Pulse Generator.
3V
1.5V
0V
DATA INPUT
TIMING INPUT
ASYNCHRONOUS
CONTROL, PRESET,
SYNCHRONOUS CONTROL
PRESET, CLEAR,
CLOCK ENABLE, ETC.
3V
1.5V
0V
3V
1.5V
0V
3V
1.5V
0V
tSU
tREM
tH
tSU tH
CLEAR, ETC. tW
LOW-HIGH-LOW
PULSE
HIGH-LOW-HIGH
PULSE
1.5V
1.5V
3V
1.5V
0V
CONTROL INPUT
OUTPUT
NORMALLY LOW
OUTPUT
NORMALLY HIGH SWITCH
OPEN
tPZL 3.5V
1.5V
1.5V
0V
tPLZ
tPHZ
tPZH
0V
3.5V
0.3V
0.3V
VOL
VOH
SWITCH
CLOSED
ENABLE DISABLE
1.5V
3V
0V
1.5V
3V
0V
tPLH
SAME PHASE
INPUT TRANSITION
tPHL
tPLH tPHL
OPPOSITE PHASE
INPUT TRANSITION
OUTPUT 1.5V
VOH
VOL
9
CD74FCT16501T, CD74FCT162501T
NOTES:
1. Dimension “D” does not include mold flash, protrusions or gate
burrs.
2. Dimension “E” does not include interlead flash or protrusions.
3. “L” is the length of terminal for soldering to a substrate.
4. “N” is the number of terminal positions.
5. Terminal numbers are shown for reference only.
6. Controlling dimension: INCHES. Converted millimeter dimen-
sions are not necessarily exact.
INDEX
AREA E
D
N
123
e
L
B
A1
A
SEATING PLANE
0.10(0.004) C
H
α
0.08(0.003) M
Thin Shrink Small Outline Plastic Packages (TSSOP)
M56.240-P
56 LEAD THIN SHRINK SMALL OUTLINE PLASTIC PACKAGE
SYMBOL
INCHES MILLIMETERS
NOTESMIN MAX MIN MAX
A 0.041 0.047 1.05 1.20 -
A1 0.002 0.006 0.05 0.15 -
B 0.007 0.010 0.178 0.254 -
C 0.004 0.008 0.102 0.203 -
D 0.547 0.555 13.90 14.09 1
E 0.236 0.244 6.00 6.19 2
e 0.0197 BSC 0.50 BSC -
H 0.307 0.330 7.80 8.38 -
L 0.020 0.030 0.51 0.76 3
N56 564
α
0
o
8
o
0
o
8
o
-
Rev. 0 6/96
10
All Harris Semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Harris Semiconductor products are sold by description only. Harr is Semiconductor reserves the right to make changes in circuit design and/or specifications at
any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Harris is
believed to be accurate and reliable. However, no responsibility is assumed by Harris or its subsidiaries for its use; nor for any infringements of patents or other
rights of third parties which ma y result from its use . No license is g r anted b y implication or otherwise under any patent or patent rights of Harris or its subsidiaries.
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FAX: (65) 748-0400
SEMICONDUCTOR
CD74FCT16501T, CD74FCT162501T
NOTES:
1. These package dimensions are within allow ab le dimensions of
JECEC MO-118-AB, Issue B.
2. Dimension “D” does not include mold flash, protrusions or gate
burrs.
3. Dimension “E” does not include interlead flash or protrusions.
4. “L” is the length of terminal for soldering to a substrate.
5. “N” is the number of terminal positions.
6. Terminal numbers are shown for reference only.
7. Controlling dimension: INCHES. Converted millimeter dimen-
sions are not necessarily exact.
INDEX
AREA E
D
N
123
e
B
A1
A
SEATING PLANE
0.10(0.004)
H
0.17(0.007) M
L
0.25
0.010
GAUGE
PLANE
C
αA2
h x 45o
Shrink Small Outline Plastic Packages (SSOP)
M56.300-P
56 LEAD SHRINK SMALL OUTLINE PLASTIC PACKAGE
SYMBOL
INCHES MILLIMETERS
NOTESMIN MAX MIN MAX
A 0.096 0.108 2.44 2.74 -
A1 0.008 0.016 0.20 0.41 -
A2 0.088 0.092 2.24 2.34 -
B 0.008 0.0135 0.20 0.34 -
C 0.005 0.010 0.13 0.25 -
D 0.720 0.730 18.29 18.54 2
E 0.291 0.299 7.39 7.59 3
e 0.025 BSC 0.635 BSC -
H 0.395 0.415 10.03 10.54 -
h 0.015 0.025 0.381 0.635 -
L 0.020 0.040 0.51 1.01 4
N56 565
α
0
o
8
o
0
o
8
o
-
Rev. 0 5/96
