SCAS521F − AUGUST 1995 − REVISED OCT OBER 2003
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
D2-V to 6-V VCC Operation
DInputs Accept Voltages to 6 V
DMax tpd of 10 ns at 5 V
description/ordering information
The ’AC74 devices are dual positive-edge-
triggered D-type flip-flops.
A low level at the preset (PRE) or clear (CLR) input
sets or resets the outputs, regardless of the levels
of the other inputs. When PRE and CLR are
inactive (high), data at the data (D) input meeting
the setup-time requirements is transferred to the
outputs on the positive-going edge of the clock
pulse. Clock triggering occurs at a voltage level
and is not directly related to the rise time of the
clock pulse. Following the hold-time interval, data
at D can be changed without affecting the levels
at the outputs.
ORDERING INFORMATION
TAPACKAGE†ORDERABLE
PART NUMBER TOP-SIDE
MARKING
PDIP − N Tube SN74AC74N SN74AC74N
SOIC − D
Tube SN74AC74D
AC74
SOIC − D Tape and reel SN74AC74DR AC74
−40°C to 85°CSOP − NS Tape and reel SN74AC74NSR AC74
−40 C to 85 C
SSOP − DB Tape and reel SN74AC74DBR AC74
TSSOP − PW
Tube SN74AC74PW
AC74
TSSOP − PW Tape and reel SN74AC74PWR AC74
CDIP − J Tube SNJ54AC74J SNJ54AC74J
−55°C to 125°CCFP − W Tube SNJ54AC74W SNJ54AC74W
−55 C to 125 C
LCCC − FK Tube SNJ54AC74FK SNJ54AC74FK
†Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.
Copyright 2003, Texas Instruments Incorporated
! " #$%! " &$'(#! )!%*
)$#!" # ! "&%##!" &% !+% !%" %," "!$%!"
"!)) -!.* )$#! &#%""/ )%" ! %#%""(. #($)%
!%"!/ (( &%!%"*
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications o
f
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
1
2
3
4
5
6
7
14
13
12
11
10
9
8
1CLR
1D
1CLK
1PRE
1Q
1Q
GND
VCC
2CLR
2D
2CLK
2PRE
2Q
2Q
SN54AC74 . . . FK PACKAGE
(TOP VIEW)
SN54AC74 ...J OR W PACKAGE
SN74AC74 . . . D, DB, N, NS, OR PW PACKAGE
(TOP VIEW)
3 2 1 20 19
910111213
4
5
6
7
8
18
17
16
15
14
2D
NC
2CLK
NC
2PRE
1CLK
NC
1PRE
NC
1Q
1D
1CLR
NC
2Q
2Q V
2CLR
1Q
GND
NC
NC − No internal connection
CC
&)$#!" #&(! ! 0121 (( &%!%" % !%"!%)
$(%"" !+%-"% !%)* (( !+% &)$#!" &)$#!
&#%""/ )%" ! %#%""(. #($)% !%"!/ (( &%!%"*
SCAS521F − AUGUST 1995 − REVISED OCT OBER 2003
2POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
FUNCTION TABLE
INPUTS OUTPUTS
PRE CLR CLK D Q Q
L H X X H L
HLXXLH
LLXXH
†H†
H H ↑HHL
H H ↑LLH
H H L X Q0Q0
†This configuration is unstable; that is, it does not
persist when either PRE or CLR returns to its
inactive (high) level.
logic diagram, each flip-flop (positive logic)
TG
C
C
TG
C
C
TG
C
C
C
C
TG
C
C
PRE
CLK
D
CLR
Q
Q
SCAS521F − AUGUST 1995 − REVISED OCT OBER 2003
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC −0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, VI (see Note 1) −0.5 V to VCC + 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output voltage range, VO (see Note 1) −0.5 V to VCC + 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input clamp current, IIK (VI < 0 or VI > VCC) ±20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output clamp current, IOK (VO < 0 or VO > VCC) ±20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous output current, IO (VO = 0 to VCC) ±50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous current through VCC or GND ±200 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package thermal impedance, θJA (see Note 2): D package 86°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DB package 96°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
N package 80°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
NS package 76°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PW package 113°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, Tstg −65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
recommended operating conditions (see Note 3)
SN54AC74 SN74AC74
UNIT
MIN MAX MIN MAX
UNIT
VCC Supply voltage 2 6 2 6 V
VCC = 3 V 2.1 2.1
V
IH
High-level input voltage VCC = 4.5 V 3.15 3.15 V
VIH
High-level input voltage
VCC = 5.5 V 3.85 3.85
V
VCC = 3 V 0.9 0.9
V
IL
Low-level input voltage VCC = 4.5 V 1.35 1.35 V
VIL
Low-level input voltage
VCC = 5.5 V 1.65 1.65
V
VIInput voltage 0 VCC 0 VCC V
VOOutput voltage 0 VCC 0 VCC V
VCC = 3 V −12 −12
I
OH
High-level output current VCC = 4.5 V −24 −24 mA
IOH
High-level output current
VCC = 5.5 V −24 −24
mA
VCC = 3 V 12 12
I
OL
Low-level output current VCC = 4.5 V 24 24 mA
IOL
Low-level output current
VCC = 5.5 V 24 24
mA
∆t/∆vInput transition rise or fall rate 8 8 ns/V
TAOperating free-air temperature −55 125 −40 85 °C
NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
SCAS521F − AUGUST 1995 − REVISED OCT OBER 2003
4POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
TA = 25°C SN54AC74 SN74AC74
UNIT
PARAMETER
TEST CONDITIONS
VCC MIN TYP MAX MIN MAX MIN MAX
UNIT
3 V 2.9 4.49 2.9 2.9
I
OH
= −50 µA4.5 V 4.4 5.49 4.4 4.4
IOH = −50 µA
5.5 V 5.4 5.49 5.4 5.4
VOH
IOH = −12 mA 3 V 2.56 2.4 2.46
V
VOH
IOH = −24 mA
4.5 V 3.86 3.7 3.76 V
IOH = −24 mA 5.5 V 4.86 4.7 4.76
IOH = −50 mA†5.5 V 3.85
IOH = −75 mA†5.5 V 3.85
3 V 0.002 0.1 0.1 0.1
I
OL
= 50 µA4.5 V 0.001 0.1 0.1 0.1
IOL = 50 µA
5.5 V 0.001 0.1 0.1 0.1
VOL
IOL = 12 mA 3 V 0.36 0.5 0.44
V
VOL
IOL = 24 mA
4.5 V 0.36 0.5 0.44 V
IOL = 24 mA 5.5 V 0.36 0.5 0.44
IOL = 50 mA†5.5 V 1.65
IOL = 75 mA†5.5 V 1.65
II
Data pins
VI = VCC or GND
5.5 V
±0.1 ±1±1
A
IIControl pins VI = VCC or GND 5.5 V ±0.1 ±1±1µA
ICC VI = VCC or GND, IO = 0 5.5 V 2 40 20 µA
CiVI = VCC or GND 5 V 3 pF
†Not more than one output should be tested at a time, and the duration of the test should not exceed 2 ms.
timing requirements over recommended operating free-air temperature range,
VCC = 3.3 V " 0.3 V (unless otherwise noted) (see Figure 1)
TA = 25°C SN54AC74 SN74AC74
UNIT
MIN MAX MIN MAX MIN MAX
UNIT
fclock Clock frequency 100 70 95 MHz
tw
Pulse duration
PRE or CLR low 5.5 8 7
ns
twPulse duration CLK 5.5 8 7 ns
tsu
Setup time, data before CLK↑
Data 4 5 4.5
ns
tsu Setup time, data before CLK↑PRE or CLR inactive 0 0.5 0 ns
thHold time, data after CLK↑0.5 0.5 0.5 ns
SCAS521F − AUGUST 1995 − REVISED OCT OBER 2003
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
timing requirements over recommended operating free-air temperature range,
VCC = 5 V"0.5 V (unless otherwise noted) (see Figure 1)
TA = 25°C SN54AC74 SN74AC74
UNIT
MIN MAX MIN MAX MIN MAX
UNIT
fclock Clock frequency 140 95 125 MHz
tw
Pulse duration
PRE or CLR low 4.5 5.5 5
ns
twPulse duration CLK 4.5 5.5 5 ns
tsu
Setup time, data before CLK↑
Data 3 4 3
ns
tsu Setup time, data before CLK↑PRE or CLR inactive 0 0.5 0 ns
thHold time, data after CLK↑0.5 0.5 0.5 ns
switching characteristics over recommended operating free-air temperature range,
VCC = 3.3 V " 0.3 V (unless otherwise noted) (see Figure 1)
PARAMETER
FROM
TO
TA = 25°C SN54AC74 SN74AC74
UNIT
PARAMETER
FROM
(INPUT)
TO
(OUTPUT) MIN TYP MAX MIN MAX MIN MAX
UNIT
fmax 100 125 70 95 MHz
tPLH
PRE or CLR
Q or Q
3.5 8 12 1 13 2.5 13
ns
tPHL PRE or CLR Q or Q 4 10.5 12 1 14 3.5 13.5 ns
tPLH
CLK
Q or Q
4.5 8 13.5 1 17.5 4 16
ns
tPHL CLK Q or Q 3.5 8 14 1 13.5 3.5 14.5 ns
switching characteristics over recommended operating free-air temperature range,
VCC = 5 V " 0.5 V (unless otherwise noted) (see Figure 1)
PARAMETER
FROM
TO
TA = 25°C SN54AC74 SN74AC74
UNIT
PARAMETER
FROM
(INPUT)
TO
(OUTPUT) MIN TYP MAX MIN MAX MIN MAX
UNIT
fmax 140 160 95 125 MHz
tPLH
PRE or CLR
Q or Q
2.5 6 9 1 9.5 2 10
ns
tPHL PRE or CLR Q or Q 3 8 9.5 1 10.5 2.5 10.5 ns
tPLH
CLK
Q or Q
3.5 6 10 1 12 3 10.5
ns
tPHL CLK Q or Q 2.5 6 10 1 10 2.5 10.5 ns
operating characteristics, VCC = 3.3 V, TA = 25°C
PARAMETER TEST CONDITIONS TYP UNIT
Cpd Power dissipation capacitance CL = 50 pF, f = 1 MHz 45 pF
SCAS521F − AUGUST 1995 − REVISED OCT OBER 2003
6POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
50% VCC 50% VCC
50% VCC
50% VCC
VCC
VCC
0 V
0 V
th
tsu
VOLTAGE WAVEFORMS
Data Input
tPLH
tPHL
tPHL
tPLH
VOH
VOH
VOL
VOL
50% VCC 50% VCC
VCC
0 V
50% VCC
50% VCC
Input
Out-of-Phase
Output
In-Phase
Output Timing Input
50% VCC
VOLTAGE WAVEFORMS
From Output
Under Test
CL = 50 pF
(see Note A)
LOAD CIRCUIT
S1
2
×
V
CC
500 Ω
500 Ω Open tPLH/tPHL Open
TEST S1
VCC
0 V
50% VCC 50% VCC
tw
VOLTAGE WAVEFORMS
Input
NOTES: A. CL includes probe and jig capacitance.
B. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr v2.5 ns, tf v 2.5 ns
.
C. The outputs are measured one at a time with one input transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
PACKAGE OPTION ADDENDUM
www.ti.com 4-Feb-2021
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead finish/
Ball material
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
5962-88520012A ACTIVE LCCC FK 20 1 Non-RoHS
& Green POST-PLATE N / A for Pkg Type -55 to 125 5962-
88520012A
SNJ54AC
74FK
5962-8852001CA ACTIVE CDIP J 14 1 Non-RoHS
& Green SNPB N / A for Pkg Type -55 to 125 5962-8852001CA
SNJ54AC74J
5962-8852001DA ACTIVE CFP W 14 1 Non-RoHS
& Green SNPB N / A for Pkg Type -55 to 125 5962-8852001DA
SNJ54AC74W
5962-8852001VDA ACTIVE CFP W 14 1 Non-RoHS
& Green SNPB N / A for Pkg Type -55 to 125 5962-8852001VD
A
SNV54AC74W
SN74AC74D ACTIVE SOIC D 14 50 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 AC74
SN74AC74DBR ACTIVE SSOP DB 14 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 AC74
SN74AC74DR ACTIVE SOIC D 14 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 AC74
SN74AC74N ACTIVE PDIP N 14 25 RoHS & Green NIPDAU N / A for Pkg Type -40 to 85 SN74AC74N
SN74AC74NE4 ACTIVE PDIP N 14 25 RoHS & Green NIPDAU N / A for Pkg Type -40 to 85 SN74AC74N
SN74AC74NSR ACTIVE SO NS 14 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 AC74
SN74AC74PW ACTIVE TSSOP PW 14 90 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 AC74
SN74AC74PWR ACTIVE TSSOP PW 14 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 AC74
SN74AC74PWRE4 ACTIVE TSSOP PW 14 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 AC74
SN74AC74PWRG4 ACTIVE TSSOP PW 14 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 AC74
SNJ54AC74FK ACTIVE LCCC FK 20 1 Non-RoHS
& Green POST-PLATE N / A for Pkg Type -55 to 125 5962-
88520012A
SNJ54AC
74FK
SNJ54AC74J ACTIVE CDIP J 14 1 Non-RoHS
& Green SNPB N / A for Pkg Type -55 to 125 5962-8852001CA
SNJ54AC74J
PACKAGE OPTION ADDENDUM
www.ti.com 4-Feb-2021
Addendum-Page 2
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead finish/
Ball material
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
SNJ54AC74W ACTIVE CFP W 14 1 Non-RoHS
& Green SNPB N / A for Pkg Type -55 to 125 5962-8852001DA
SNJ54AC74W
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF SN54AC74, SN54AC74-SP, SN74AC74 :
PACKAGE OPTION ADDENDUM
www.ti.com 4-Feb-2021
Addendum-Page 3
•Catalog: SN74AC74, SN54AC74
•Enhanced Product: SN74AC74-EP, SN74AC74-EP
•Military: SN54AC74
•Space: SN54AC74-SP
NOTE: Qualified Version Definitions:
•Catalog - TI's standard catalog product
•Enhanced Product - Supports Defense, Aerospace and Medical Applications
•Military - QML certified for Military and Defense Applications
•Space - Radiation tolerant, ceramic packaging and qualified for use in Space-based application
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
SN74AC74DR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1
SN74AC74DR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1
SN74AC74NSR SO NS 14 2000 330.0 16.4 8.2 10.5 2.5 12.0 16.0 Q1
SN74AC74PWR TSSOP PW 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 30-Dec-2020
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
SN74AC74DR SOIC D 14 2500 853.0 449.0 35.0
SN74AC74DR SOIC D 14 2500 333.2 345.9 28.6
SN74AC74NSR SO NS 14 2000 853.0 449.0 35.0
SN74AC74PWR TSSOP PW 14 2000 853.0 449.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 30-Dec-2020
Pack Materials-Page 2
www.ti.com
PACKAGE OUTLINE
C
14X .008-.014
[0.2-0.36]
TYP
-15
0
AT GAGE PLANE
-.314.308 -7.977.83[ ]
14X -.026.014 -0.660.36[ ]
14X -.065.045 -1.651.15[ ]
.2 MAX TYP
[5.08] .13 MIN TYP
[3.3]
TYP-.060.015 -1.520.38[ ]
4X .005 MIN
[0.13]
12X .100
[2.54]
.015 GAGE PLANE
[0.38]
A
-.785.754 -19.9419.15[ ]
B -.283.245 -7.196.22[ ]
CDIP - 5.08 mm max heightJ0014A
CERAMIC DUAL IN LINE PACKAGE
4214771/A 05/2017
NOTES:
1. All controlling linear dimensions are in inches. Dimensions in brackets are in millimeters. Any dimension in brackets or parenthesis are for
reference only. Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This package is hermitically sealed with a ceramic lid using glass frit.
4. Index point is provided on cap for terminal identification only and on press ceramic glass frit seal only.
5. Falls within MIL-STD-1835 and GDIP1-T14.
78
14
1
PIN 1 ID
(OPTIONAL)
SCALE 0.900
SEATING PLANE
.010 [0.25] C A B
www.ti.com
EXAMPLE BOARD LAYOUT
ALL AROUND
[0.05] MAX.002
.002 MAX
[0.05]
ALL AROUND
SOLDER MASK
OPENING
METAL
(.063)
[1.6]
(R.002 ) TYP
[0.05]
14X ( .039)
[1]
( .063)
[1.6]
12X (.100 )
[2.54]
(.300 ) TYP
[7.62]
CDIP - 5.08 mm max heightJ0014A
CERAMIC DUAL IN LINE PACKAGE
4214771/A 05/2017
LAND PATTERN EXAMPLE
NON-SOLDER MASK DEFINED
SCALE: 5X
SEE DETAIL A SEE DETAIL B
SYMM
SYMM
1
78
14
DETAIL A
SCALE: 15X
SOLDER MASK
OPENING
METAL
DETAIL B
13X, SCALE: 15X
MECHANICAL DATA
MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE
4040065 /E 12/01
28 PINS SHOWN
Gage Plane
8,20
7,40
0,55
0,95
0,25
38
12,90
12,30
28
10,50
24
8,50
Seating Plane
9,907,90
30
10,50
9,90
0,38
5,60
5,00
15
0,22
14
A
28
1
2016
6,50
6,50
14
0,05 MIN
5,905,90
DIM
A MAX
A MIN
PINS **
2,00 MAX
6,90
7,50
0,65 M
0,15
0°–ā8°
0,10
0,09
0,25
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-150
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