2011-2018 Microchip Technology Inc. DS80000531J-page 1
PIC32MX1XX/2XX 28/36/44-PIN
The PIC32MX1XX/2XX 28/36/44-pin family devices that
you have received conform functionally to the current
Device Data Sheet (DS60001168K), except for the
anomalies describe d in this doc ument.
The errata described in this document w ill be addressed
in future revisions of the PIC32MX1XX/2XX 28/36/44-
pin silicon.
Data Sheet clarifications and corrections start on page
12, following the disc ussion of silico n issues.
The silicon revision level can be identified using the
current version of MPLAB
®
X IDE and Microchip’s
programmers, debuggers and emulation tools, which
are available at the Microchip corporate web site
(www.microchip.com).
For example, to identify the silicon revision level
using MPLAB X IDE in conjunction with a hardware
debugger:
1. Using the appropriate interface, connect the
device to the hardware deb ugg er.
2. Open an MPLAB X IDE project.
3. Configure the MPLAB X IDE project for the
appropriate device and hardware debugger.
4. Select Wind ow > Dashboa rd, and then click
the Refresh Debug Tool Status icon
().
5. The part number and the Device and
Revision ID values appear in the Output
window.
The Device and Revision ID values for the various
silicon revisions are provided in Table 1 through
Table 4.
Note: The silicon issues discussed in the
following pages are for silicon revisions
with the Device and Revision IDs liste d in
Table 1 through Table 4. The last column
of ea ch tab le re presen ts th e late st si licon
revision for the devices listed. The silicon
issues are summarized in Table 5.
Note: If you are unable to extract the silicon
revision level, please contact your local
Microchip sales office for assistance.
TABLE 1: SILICON DEVREV VALUES FOR DEVICES WITH 16/32 KB FLASH
Part Number Device ID
(1)
Revision ID for Silicon Revision
(1)
A0 A1
PIC32MX110F016B 0x4A07053
0x0 0x1
PIC32MX110F016C 0x4A09053
PIC32MX110F016D 0x4A0B053
PIC32MX210F016B 0x4A01053
PIC32MX210F016C 0x4A03053
PIC32MX210F016D 0x4A05053
PIC32MX120F032B 0x4A06053
PIC32MX120F032C 0x4A08053
PIC32MX120F032D 0x4A0A053
PIC32MX220F032B 0x4A00053
PIC32MX220F032C 0x4A02053
PIC32MX220F032D 0x4A04053
Note 1: Refer to the “Memory Organization” and “Special Fea tures ” chapters in the current Device Data Sheet
(DS60001168J) for detailed information on Device and Revisi on IDs for your specific device.
PIC32MX1XX/2XX 28/36/44-pin Family
Silicon Errata and Data Sheet Clarification
PIC32MX1XX/2XX 28/36/44-PIN
DS80000531J-page 2 2011-2018 Mic rochip Technology Inc.
TABLE 2: SILICON DEVREV VALUES FOR DEVICES WITH 64/128 KB FLASH
Part Number Device ID
(1)
Revision ID for Silicon Revision
(1)
A0 A1 A3
PIC32MX130F064B 0x4D07053
0x0 0x1
0x3
PIC32MX130F064C 0x4D09053
PIC32MX130F064D 0x4D0B053
PIC32MX230F064B 0x4D01053
PIC32MX230F064C 0x4D03053
PIC32MX230F064D 0x4D05053
PIC32MX150F128B 0x4D060 53
—
PIC32MX150F128C 0x4D08053
PIC32MX150F128D 0x4D0A053
PIC32MX250F128B 0x4D00053
PIC32MX250F128C 0x4D02053
PIC32MX250F128D 0x4D04053
Note 1: Refer to the “Memor y Organi zati on” and “Sp eci al Feature s” chapters in the current Device Data Sheet
(DS60001168J) for detailed information on Device and Revisi on IDs for your specific device.
TABLE 3: SILICON DEVREV VALUES FOR DEVICES WITH 256 KB FLASH AND 64 KB RAM
Part Number Device ID
(1)
Revision ID for Silicon Revision
(1)
A1 A2
PIC32MX170F256B 0x6610053
0x1 0x2
PIC32MX170F256D 0x661A053
PIC32MX270F256B 0x6600053
PIC32MX270F256D 0x660A053
PIC32MX270F256DB 0x660C053
Note 1: Refer to the “Memory Organization” and “Special Fea tures ” chapters in the current Device Data Sheet
(DS60001168J) for detailed information on Device and Revisi on IDs for your specific device.
TABLE 4: SILICON DEVREV VALUES FOR DEVICES WITH 256 KB FLASH AND 16 KB RAM
Part Number Device ID
(1)
Revision ID for Silicon Revision
(1)
A0
PIC32MX130F256B 0x6703053
0x0
PIC32MX130F256D 0x6705053
PIC32MX230F256B 0x6700053
PIC32MX230F256D 0x6702053
Note 1: Refer to the “Mem ory Or ga niz ation ” and “Special Fea tures ” chapters in the current Device Data Sheet
(DS60001168J) for detailed information on Device and Revisi on IDs for your specific device.
2011-2018 Microchip Technology Inc. DS80000531J-page 3
PIC32MX1XX/2XX 28/36/44-PIN
s
TABLE 5: SILICON ISSUE SUMMARY
Module Feature Item Issue Summary
Affected Device
Flash
Memory
(KB)
Data
Memory
(KB)
Silicon
Revision
A0 A1 A2 A3
Voltage
Regulator BOR 1. Device may not exit Brown-out Reset (BOR)
state if a BO R event occurs.
16/32 4/8 X — —
64 16 X —
128 32 X — —
256 16 — — —
256 64 — —
Oscillator Clock Switch 2.
If a Fail-Safe Clock Monitor (FSCM) event
occur s when Primary Oscill ator (P
OSC
) mode
is used, firmware clock swi tch requests to
switch from FRC mode will fail.
16/32 4/8 X X — —
64 16 X X —X
128 32 X X — —
256 16 X — — —
256 64 —XX—
I
2
CSlave Mode 3. The I
2
C module does not respond to address
0x78 when the STRICT and A10M bits are
cleared in the I2CxCON register.
16/32 4/8 X X — —
64 16 X X —X
128 32 X X — —
256 16 X — — —
256 64 —XX—
USB UIDLE Interrupt 4. UIDLE interrupts cease if the UIDLE interrupt
flag is cleared.
16/32 4/8 X X — —
64 16 X X —X
128 32 X X — —
256 16 X — — —
256 64 —XX—
ADC N/A 5
The DNL param et er of the ADC m odule is
not within the published data sheet
specifications when the ADC module is
operating at maximum conversion rate.
16/32 4/8 X X — —
64 16 X X —X
128 32 X X — —
256 16 X — — —
256 64 —XX—
ADC CTMU
Calibration 6. Op en select i on for Chan nel 0 positi ve input
is not functional.
16/32 4/8 X X — —
64 16 —
128 32 — —
256 16 — — —
256 64 — —
Legend: An ‘X’ indicates the issue is present in th is revision of silicon;
shaded cells with an Em dash (‘—’) indicate that this silicon revision does not exist for this issue;
blank cells indicate an issue has been corrected in this revision of silicon.
PIC32MX1XX/2XX 28/36/44-PIN
DS80000531J-page 4 2011-2018 Mic rochip Technology Inc.
ADC Conversion
Tr i gger from
INT0 Interrupt 7.
The ADC module conversion triggers occur
on the ris in g ed ge of t he I N T0 signal even
when INT0 is configured to generate an
interrupt on the falling edge.
16/32 4/8 X X — —
64 16 X X —X
128 32 X X — —
256 16 X — — —
256 64 —XX—
Parallel
Master Port
(PMP) Address Pins 8. Wh e n t h e Parallel Mas ter Port (PMP)
module is enable d, address pin s cannot be
used as G P I O ou tp ut pi ns.
16/32 4/8 X X — —
64 16 X X —X
128 32 X X — —
256 16 X — — —
256 64 —XX—
I/O Ports RA0 a nd R A1
Pins 9. When I2C1 is enabled, all dig ital output-onl y
functions and all analog functions on pins
RA0 an d R A 1 d o not fu nction corre ct l y.
16/32 4/8 X X — —
64 16 X X —
128 32 X X — —
256 16 — — —
256 64 — —
CPU Data Wr ite to a
Peripheral 10. A data wr ite o peration by th e C PU t o a
peripheral ma y be rep eated if an i nt errupt
occur s dur i ng initial write operation.
16/32 4/8 X X — —
64 16 X X —
128 32 X X — —
256 16 — — —
256 64 — —
Oscillator Clock Out 11.
A clock signal is present on the CLKO pi n,
regardless of the clock source and setting of
the CL K O Enable Configuration bit, during a
Power-on Reset (POR) cond i tion.
16/32 4/8 X X — —
64 16 X X —X
128 32 X X — —
256 16 X — — —
256 64 —XX—
Input Ca pt ur e Idle Mode and
Sleep Mode 12.
All inpu t ca pt ur e modes s el ec ta bl e by
ICM<2:0>, with the exception o f Interrupt-
only mode, will not work when the CPU
enters Idle mode or Sleep mode.
16/32 4/8 X X — —
64 16 X X —X
128 32 X X — —
256 16 X — — —
256 64 —XX—
TABLE 5: SILICON ISSUE SUMMARY (CONTINUED)
Module Feature Item Issue Summary
Affected Device
Flash
Memory
(KB)
Data
Memory
(KB)
Silicon
Revision
A0 A1 A2 A3
Legend: An ‘X’ indicates the issue is present in th is revision of silicon;
shaded cells with an Em dash (‘—’) indicate that this silicon revision does not exis t for this issue;
blank cells indicate an issue has been corrected in this revision of silicon.
2011-2018 Microchip Technology Inc. DS80000531J-page 5
PIC32MX1XX/2XX 28/36/44-PIN
Watchdog
T i me r (WDT ) Windowed
Mode 13. The Watchdog T imer may issue a reset even
if the user tries to clear the module within the
all ow ed window.
16/32 4/8 X X — —
64 16 X X —X
128 32 X X — —
256 16 X — — —
256 64 —XX—
Non-5V
Tolerant Pins Pull-ups 14. Internal pu ll-up res i stors may not guarantee
a logical ‘1’ on non-5 V t olerant pins when
they ar e co nf i gur ed as digital input s.
16/32 4/8 X X — —
64 16 X X —
128 32 X X — —
256 16 — — —
256 64 — —
5V Tolerant
Pins Pull-ups 15. Internal pu ll-up res istors ma y not guaran t ee
a logical ‘1’ on 5V tolera nt pi ns when they
are co nfigured as di gital inputs.
16/32 4/8 X X — —
64 16 X X —X
128 32 X X — —
256 16 X — — —
256 64 —XX—
I/O Ports Open D r ai n 16.
The Open Drain selection (ODCx) on I/O port
pins is not available w hen the pin is
configured for anything other than a standard
port output.
16/32 4/8 X X — —
64 16 X X —
128 32 X X — —
256 16 — — —
256 64 — —
I/O Ports RB5 a nd R B6
Pins 17.
When the I2C2 module is enabled, all digital
output-only functions and all analog
functi ons on pins RB 5 an d R B 6 do not
function correctly.
16/32 4/8 X X — —
64 16 X X —
128 32 X X — —
256 16 — — —
256 64 — —
I/O Ports Analog Inputs 18. Certa in fun ct ions are not av ai la ble w hen
using PGED3/PGEC3 or PGED4/PGEC4
while in Debug mode.
16/32 4/8 X X — —
64 16 X X —X
128 32 X X — —
256 16 X — — —
256 64 —XX—
TABLE 5: SILICON ISSUE SUMMARY (CONTINUED)
Module Feature Item Issue Summary
Affected Device
Flash
Memory
(KB)
Data
Memory
(KB)
Silicon
Revision
A0 A1 A2 A3
Legend: An ‘X’ indicates the issue is present in th is revision of silicon;
shaded cells with an Em dash (‘—’) indicate that this silicon revision does not exist for this issue;
blank cells indicate an issue has been corrected in this revision of silicon.
PIC32MX1XX/2XX 28/36/44-PIN
DS80000531J-page 6 2011-2018 Mic rochip Technology Inc.
UART Synchronization 19. O n a R X FI FO overflow, shift regi st er s st op
receiving data, which causes the UART to
lose sy nchroniza t io n.
16/32 4/8 X X — —
64 16 X X —X
128 32 X X — —
256 16 X — — —
256 64 —XX—
Timer1 Interrupts 20. Timer1 w ill not generate interrupt s wi t h an
exter nal asynchr onous clock input an d
pres caler other than 1:1.
16/32 4/8 X X — —
64 16 X X —X
128 32 X X — —
256 16 X — — —
256 64 —XX—
Flash
Memory Write Protection 21. The Pr ogram W rite Pr otecti on (PWP) bit s are
not ena bl ed unless the Boot Write Protec t
(BWP) bit is also enabled.
16/32 4/8 X X — —
64 16 X X —X
128 32 X X — —
256 16 X — — —
256 64 —XX—
Flash
Memory Write Protection 22.
When enabled, the Boot Write Protect
(BWP) bit also protects and overlaps the first
page of user prog ram space bel ow 0x0400 in
additi on t o t he boot segm ent.
16/32 4/8 X X — —
64 16 X X —
128 32 X X — —
256 16 — — —
256 64 — —
Flash
Memory Write Protection 23. The Program Write Protection (PWP) bit field
is off by one pag e r el at ive t o th e definition in
the data sheet.
16/32 4/8 X X — —
64 16 X X —
128 32 X X — —
256 16 — — —
256 64 — —
Flash
Memory Write Protection 24. Attempts to protect the entire Flash memory
using the follo wing valu e s , will res ult in no
pages being protected.
16/32 4/8 X X — —
64 16 X X —
128 32 X X — —
256 16 — — —
256 64 — —
TABLE 5: SILICON ISSUE SUMMARY (CONTINUED)
Module Feature Item Issue Summary
Affected Device
Flash
Memory
(KB)
Data
Memory
(KB)
Silicon
Revision
A0 A1 A2 A3
Legend: An ‘X’ indicates the issue is present in th is revision of silicon;
shaded cells with an Em dash (‘—’) indicate that this silicon revision does not exis t for this issue;
blank cells indicate an issue has been corrected in this revision of silicon.
2011-2018 Microchip Technology Inc. DS80000531J-page 7
PIC32MX1XX/2XX 28/36/44-PIN
Power-
Saving
Modes Idle 25. On exit from Sleep mode, the SLEEP and
IDLE st at us bits i n t he RC O N registe r are
being set.
16/32 4/8 X X — —
64 16 X X —X
128 32 X X — —
256 16 X — — —
256 64 —XX—
CTMU Temperature
Measurement 26. The CTMU internal temperature sensing
diode does not function for V
DD
/AV
DD
operating voltages that ar e less than 2.5V.
16/32 4/8 X X — —
64 16 X X —
128 32 X X — —
256 16 — — —
256 64 —
XX
—
I
2
CSlave
Addresses 27.
When t he I
2
C modul e i s op erating as a
Slave, some re served bus addresses may
be Acknowledged (ACKed) when they
shoul d be not Ack now l e dged (NAKed).
16/32 4/8 X X — —
64 16 X X —
128 32 X X — —
256 16 — — —
256 64 —
XX
—
Bus Matrix
Flash Size 28. The Flash Memory Size regi ster
(BMXPFMSZ) was not programmed with
the correct value.
16/32 4/8
Dat e code pre-
1750
64 16
128 32
256 16
256 64
TABLE 5: SILICON ISSUE SUMMARY (CONTINUED)
Module Feature Item Issue Summary
Affected Device
Flash
Memory
(KB)
Data
Memory
(KB)
Silicon
Revision
A0 A1 A2 A3
Legend: An ‘X’ indicates the issue is present in th is revision of silicon;
shaded cells with an Em dash (‘—’) indicate that this silicon revision does not exist for this issue;
blank cells indicate an issue has been corrected in this revision of silicon.
PIC32MX1XX/2XX 28/36/44-PIN
DS80000531J-page 8 2011-2018 Mic rochip Technology Inc.
Silicon Errat a Issues
1. Module: Voltage Regulator
Device may not exit the Brown-out Reset (BOR)
state if a BOR event occurs.
Work arounds
Work around 1:
V
DD
must remain within the published specification
(see param eter DC10 of the device data sheet).
Work around 2:
Reset the de vice by p rovidi ng the Powe r-on R eset
(POR) condition.
Affected Silicon Revisions
2. Module: Oscillator
If the Primary Oscillator (P
OSC
) mode is
implemented and a Fail-Safe Clock Monitor
(FSCM) event occurs (failure of the external
primary clock), the internal cl ock sourc e will switc h
to the FRC oscillator. Subsequent firmware clock
switch requests from the FRC oscillator to other
clock sources will fail and the device will continue
to execute on the FRC oscillator. On repair of the
external clock source and a power-on state, the
device will resume operation with the primary
oscillator clock source.
Work around
None.
Affected Silicon Revisions
Note 1: This do cument summarizes all silicon errata issues from all revisions of silicon, p revious as well as current.
The table provided in each issue indicates w hich issues exist for a particular revision of silicon based on
Flash memory size.
2: The following applies to the Affected Silicon Revision tables in each silicon is sue:
• An ‘X’ indicates the issue is present in this revision of silicon
• Shaded cells with an Em dash (‘—’) indicate that this silicon revision does not exist for this issue
• Blank cells indicate an issue has been corrected or does not exist in this revision of silicon
Device
Flash
Memory
(KB)
Data
Memory
(KB)
Device Silicon Revision
A0 A1 A2 A3
16/32 4/8 X — —
64 16 X —
128 32 X — —
256 16 — — —
256 64 — —
Device
Flash
Memory
(KB)
Data
Memory
(KB)
Device Silicon Revision
A0 A1 A2 A3
16/32 4/8 X X — —
64 16 X X —X
128 32 X X — —
256 16 X — — —
256 64 —XX—
2011-2018 Microchip Technology Inc. DS80000531J-page 9
PIC32MX1XX/2XX 28/36/44-PIN
3. Module: I
2
C
The slave address, 0x78, is one of a group of
reserve d addresses. It is us ed as the upper byte of
a 10-bit address when 10-bit addressing is
enabled. The I
2
C module control register allows
the programmer to enable both 10-bit addressing
and strict enforcement of reserved addressing,
with the A10M and STRICT bits, respectively.
When both bits are cleared, the device should
respond to the reserved address 0x78, but it does
not.
Work around
None.
Affected Silicon Revisions
4. Module: USB
If the bus has been idle for more than 3 ms, the
UIDLE interrupt flag is set. If software clears the
interrupt flag and the bus remains idle, the UIDLE
interrupt flag will not be set again.
Work around
Software can leave the UIDLE bit set until it has
received some indication of bus resumption (i.e.,
Resume, Reset, SOF, or Error).
Affected Silicon Revisions
5. Module: ADC
If the ADC module is configured to operate at a
maximum conversion rate of 1.1 Msps, missing
codes are possible every 2
5
codes and the DNL
parameter will not be within the published
specification.
Work around
Configure the ADC module to operate for a
maximum conversion rate of 500 ksps.
Affected Silicon Revisions
6. Module: ADC
If th e ADC mo dule i s used i n conj unction with the
CTMU module in Absolute Capacitive/Time
Measurement mode, Channel 0 positive input
must remain open (CH0SA<3:0> = 1111 or
CH0SB<3:0> = 1111) during the calibration step.
However, open selection for Channel 0 positive
input is not functional and connects this input to
AV
SS
.
Work around
Connect the ADC module to any unused pin and
perform the CTMU calibration step. This
connection will add a small amount of additional
capacitance, but will have minimal impact on
overall measurements.
Affected Silicon Revisions
Device
Flash
Memory
(KB)
Data
Memory
(KB)
Device Silicon Revision
A0 A1 A2 A3
16/32 4/8 X X — —
64 16 X X —X
128 32 X X — —
256 16 X — — —
256 64 —XX—
Note: Resum e and Res et are the o nly inter-
rupts that should be following UIDLE
assertion. If the UIDLE bit is set, it
should be okay to suspend the USB
module (as long as this code is pro-
tected by the GUARD and/or ACT-
PEND logic). This will require
software to clear the UIDLE interrupt
enable bit to exit the USB ISR (if
using interrupt driven code).
Device
Flash
Memory
(KB)
Data
Memory
(KB)
Device Silicon Revision
A0 A1 A2 A3
16/32 4/8 X X — —
64 16 X X —X
128 32 X X — —
256 16 X — — —
256 64 —XX—
Device
Flash
Memory
(KB)
Data
Memory
(KB)
Device Silicon Revision
A0 A1 A2 A3
16/32 4/8 X X — —
64 16 X X —X
128 32 X X — —
256 16 X — — —
256 64 —XX—
Device
Flash
Memory
(KB)
Data
Memory
(KB)
Device Silicon Revision
A0 A1 A2 A3
16/32 4/8 X X — —
64 16 —
128 32 — —
256 16 — — —
256 64 — —
PIC32MX1XX/2XX 28/36/44-PIN
DS80000531J-page 10 2011-2018 Microchip Technology Inc.
7. Module: ADC
When the ADC module is configured to start
conversion on an external interrupt
(SSRC<2:0> = 001), the start of conversion
always occurs on a rising edge detected at the
INT0 pin, even when the INT0 pin has been
configured to generate an interrupt on a falling
edge (INT0EP = 0).
Work around
Generate ADC conversion triggers on the rising
edge of the INT0 signal .
Alternately, use external circuitry to invert the
signal appearing at the INT0 pin, so that a falling
edge of the input signal is detected as a rising
edge by the INT0 pin.
Affected Silicon Revisions
8. Module: Parallel Master Port (PMP)
If the PMP module i s ena ble d, a ny pi n w ith a P MP
address ing capabi lity (PMAx) cannot be us ed as a
general purpose output pin, even when the
corresponding PTEN<10:0> bit in the PMAEN
register is cleared. All other functionality on these
pins, including GPIO input functionality is not
affected.
Work around
To use a GPIO pin as an output when this pin is
shared with PMP addressing functionality and
PMP is enabled, do the following:
1. Enable PMP addressing by setting the
corresponding PTEN<10:0> bit in the
PMAEN register.
2. Instead of using corresponding LATx
registers to output GPIO data, use the
PMADDR register.
Affected Silicon Revisions
9. Module: I/O Ports
When I2C1 is enabled, all digital output-only
functions and all analog functions on pin RA0 and
RA1 do not functi on corr ect ly.
Digital output V
OH
/I
OH
does not meet the
specification in the data sheet and analog signal
input loa ding incre ases w ith an incre ase in app lied
voltage on any enabled analog function on RA0/
RA1. If I2C1 is enabled, any analog or digital
output-on ly fun ction e nabled on RA 0/RA1 wi ll als o
cause a corres po ndi ng 40 mA/p in inc rea se in I
DD
.
Work around
Disable slew rate control of the I2C1 module by
setting the DISSLW bit (I2C1CON<9>) = 1.
Affected Silicon Revisions
10. Module: CPU
During normal operation, if a CPU write operation
is int errupted b y an i ncoming interr upt, it s hould b e
aborted (not completed) and resumed after the
interrupt is serv iced. How ever, some of the se write
operations may not be aborted, resulting in a
double write to peripherals by the CPU (the first
write during the interrupt and the second write after
the interrupt is serviced).
Work around
Most peripherals are not affected by this issue, as
a double write will not have a negative impact.
Howeve r , the followi ng communicat ion periphe rals
will double-send data if their respective transmit
buffers are written twice: SPI, I
2
C, UART, and
PMP. To avoid double transmission of data, utilize
DMA to transfer data to these peripherals or
disable interrupts while writing to these
peripherals.
Affected Silicon Revisions
Device
Flash
Memory
(KB)
Data
Memory
(KB)
Device Silicon Revision
A0 A1 A2 A3
16/32 4/8 X X — —
64 16 X X —X
128 32 X X — —
256 16 X — — —
256 64 —XX—
Device
Flash
Memory
(KB)
Data
Memory
(KB)
Device Silicon Revision
A0 A1 A2 A3
16/32 4/8 X X — —
64 16 X X —X
128 32 X X — —
256 16 X — — —
256 64 —XX—
Device
Flash
Memory
(KB)
Data
Memory
(KB)
Device Silicon Revision
A0 A1 A2 A3
16/32 4/8 X X — —
64 16 X X —
128 32 X X — —
256 16 — — —
256 64 — —
Device
Flash
Memory
(KB)
Data
Memory
(KB)
Device Silicon Revision
A0 A1 A2 A3
16/32 4/8 X X — —
64 16 X X —
128 32 X X — —
256 16 — — —
256 64 — —
2011-2018 Microchip Technology Inc. DS80000531J- page 11
PIC32MX1XX/2XX 28/36/44-PIN
11. Module: Oscillator
A clock signal is present on the CLKO pin,
regardless of the clock source and setting of the
CLKO Enable Configuration bit, OSCIOFNC
(DEVCFG1<10>), during a Power-on Reset
(POR) condition.
Work around
Do not connect the CLKO pin to a device that
would be adversely affected by rapid pin toggling
or a frequency other than that defined by the
oscillator configuration. Do not use the CLKO pin
as an input if the device connected to the CLKO
pin would be adversely affected by the pin driving
a signal out.
Affected Silicon Revisions
12. Module: Input Captur e
All input capture modes selectable by ICM<2:0>,
with the exception of Interrupt-only mode, will not
work when the CPU enters Idle or Sleep mode.
Work around
Conf igure t he Inpu t Captu re module for Int errupt -
only mode (ICM<2:0> = 111) when the CPU is in
Sleep or Idle mode.
Affected Silicon Revisions
13. Module: Watchdog Timer (WDT)
When the Watchdog Timer module is used in
Windowed mode, the module may issue a reset
even if the use r tri es to clea r the m odule withi n the
allowed window.
Work around
None.
Affected Silicon Revisions
14. Module: Non-5V Tole rant Pins
When internal pull-ups are enabled on non-5V
tolerant pin s, the level as measur ed on the pin and
availab le to e xternal d evice i nputs may not exc eed
the minimum value of V
IH
, and therefore qualify as
a logic “high”. However, with respect to the PIC32
device , as l ong as V
DD
3V a nd the loa d does not
exceed -50 µA, the internal pull-ups are
guaranteed to be recognized as a logic “high”
internally to the device.
Work around
It is recommend to only use external pull-ups:
• To guarantee a logic “high” for external logic
input circuits outside of the PIC32 device
• For PIC32 device inputs, if the external load
exceeds -50 µA or V
DD
< 3V
Affected Silicon Revisions
Device
Flash
Memory
(KB)
Data
Memory
(KB)
Device Silicon Revision
A0 A1 A2 A3
16/32 4/8 X X — —
64 16 X X —X
128 32 X X — —
256 16 X — — —
256 64 —XX—
Device
Flash
Memory
(KB)
Data
Memory
(KB)
Device Silicon Revision
A0 A1 A2 A3
16/32 4/8 X X — —
64 16 X X —X
128 32 X X — —
256 16 X ———
256 64 —XX—
Device
Flash
Memory
(KB)
Data
Memory
(KB)
Device Silicon Revision
A0 A1 A2 A3
16/32 4/8 X X — —
64 16 X X —X
128 32 X X — —
256 16 X — — —
256 64 —XX—
Device
Flash
Memory
(KB)
Data
Memory
(KB)
Device Silicon Revision
A0 A1 A2 A3
16/32 4/8 X X — —
64 16 X X —
128 32 X X — —
256 16 — — —
256 64 — —
PIC32MX1XX/2XX 28/36/44-PIN
DS80000531J-page 12 2011-2018 Microchip Technology Inc.
15. Module: 5V Tolerant Pins
When internal pull-ups are enabled on 5V tolerant
pins, the level as measured on the pin and
available to external device inputs may not exceed
the minimum value of V
IH
, and therefore qualify as
a logic “high”. However, with respect to the PIC32
devi ce, a s long as V
DD
3V and the load does not
exceed -50 µA, the internal pull-ups are
guaranteed to be recognized as a logic “high”
internally to the device.
Work around
It is recommend to only use external pull-ups:
• To guarantee a logic “high” for external logic
input ci rcuits outside of the PIC32 device
• For PIC32 device inputs, if the external load
exceeds -50 µA or V
DD
< 3V
Affected Silicon Revisions
16. Module: I/O Ports
The Ope n D rai n s ele cti on (OD Cx ) on I /O port pins
is not available when the pin is configured for
anything other than a standard port output. In
additio n, the Open Drain feature is not available for
dedicated or remappable Peripheral Pin Select
(PPS) output features .
Work around
None.
Affected Silicon Revisions
17. Module: I/O Ports
When the I2C2 module is enabled, all digital
output-only functions and all analog functions on
pins RB5 and RB6 do not function correctly.
Digital output (V
OH
/I
OH
) does not meet the
specif ica t io ns in the da ta sh eet, and an alo g si gna l
input loa ding incre ases w ith an incre ase in app lied
voltage on any enabled analog function on the
RB5 and RB6 pins. If the I2C2 is enabled, any
analog or digital output-only function enabled on
the RB5 and RB6 pins will also cause a
corresponding ~40 mA/pin increase in I
DD
.
Work around
Disable the I2C2 module slew rate by setting the
DISSLW bit in the I2C2CON register = 1.
Affected Silicon Revisions
18. Module: I/O Ports
Certain functions are not available when using
PGED3/PGEC3 or PGED4/PGEC4 while in
Debug mo de.
When using the PGED3/PGEC3 pins while
debugging, these functions are not available:
•V
REF
+/CV
REF
+/AN0/C3INC
•V
REF
-/CV
REF
-/AN1.
On 44-pin devices, when using the PGED4/
PGEC4 pins while debugging, these functions are
not available:
•AN6
•AN7
Work around
Use either the PGED1/PGEC1 pin pair or the
PGED2/PGEC2 pin pair for debugging.
Affected Silicon Revisions
Device
Flash
Memory
(KB)
Data
Memory
(KB)
Device Silicon Revision
A0 A1 A2 A3
16/32 4/8 X X — —
64 16 X X —X
128 32 X X — —
256 16 X — — —
256 64 —XX—
Device
Flash
Memory
(KB)
Data
Memory
(KB)
Device Silicon Revision
A0 A1 A2 A3
16/32 4/8 X X — —
64 16 X X —
128 32 X X — —
256 16 — — —
256 64 — —
Device
Flash
Memory
(KB)
Data
Memory
(KB)
Device Silicon Revision
A0 A1 A2 A3
16/32 4/8 X X — —
64 16 X X —
128 32 X X — —
256 16 — — —
256 64 — —
Device
Flash
Memory
(KB)
Data
Memory
(KB)
Device Silicon Revision
A0 A1 A2 A3
16/32 4/8 X X — —
64 16 X X —X
128 32 X X — —
256 16 X — — —
256 64 —XX—
2011-2018 Microchip Technology Inc. DS80000531J- page 13
PIC32MX1XX/2XX 28/36/44-PIN
19. Module: UART
During a RX FIFO overflow condition, the shift
register stops receiving data. This causes the
UART to lose synchronization with the serial data
stream. The on ly way to rec over from thi s is to turn
the UART OFF and ON until it sync hronizes. This
could require several OFF/ON sequences.
Work arounds
Work around 1:
Avoid the RX overrun condition by ensuring that
the UARTx module has a high enough interrupt
priority such that other peripheral interrupt
processing latencies do not exceed the time to
overrun the UART RX buffer based on the
application baud rate. Alternately or in addition to,
set the URXISEL bits in the UxSTA register to
generate an earlier RX interrupt based on RX
FIFO fill status to buy more time for interrupt
latency processing requirements.
Work around 2:
If avoiding RX FIFO overruns is not possible,
implement a ACK/NAK software handshake
protocol to repeat lost packet transfers after
restoring UART sync hron ization.
Affected Silicon Revisions
20. Module: Timer1
T imer1 will not genera te interrupts wi th an external
asynch ronous clock i nput and pr escaler othe r than
1:1.
Work around
With external clock asynchronous mode, use 1:1
prescaler mode with a software timer overflow
variable to keep track of desired equiv alent > 1:1
prescaler setting. Alternately, use external
synchr ono us clo ck mode if this is an opt ion for the
application.
Affected Silicon Revisions
21. Module: Flash Memory
The Program Write Protection (PWP) bits
(DEVCFG0<18:10>) are not enabled unless the
Boot Write Protect (BWP) bit (DEVCFG0<24> is
also enabled (i.e., = 0).
Work around
None.
Please refer to silicon issues 22, 23, and 24 for
related information.
Affected Silicon Revisions
Device
Flash
Memory
(KB)
Data
Memory
(KB)
Device Silicon Revision
A0 A1 A2 A3
16/32 4/8 X X — —
64 16 X X —X
128 32 X X — —
256 16 X — — —
256 64 —XX—
Device
Flash
Memory
(KB)
Data
Memory
(KB)
Device Silicon Revision
A0 A1 A2 A3
16/32 4/8 X X — —
64 16 X X —X
128 32 X X — —
256 16 X ———
256 64 —XX—
Device
Flash
Memory
(KB)
Data
Memory
(KB)
Device Silicon Revision
A0 A1 A2 A3
16/32 4/8 X X — —
64 16 X X —X
128 32 X X — —
256 16 X — — —
256 64 —XX—
PIC32MX1XX/2XX 28/36/44-PIN
DS80000531J-page 14 2011-2018 Microchip Technology Inc.
22. Module: Flash Memory
When enabled, the Boot Write Protect (BWP) bit
inadvertently also protects and overlaps the first
page of PWP user program sp ace below 0x0400,
(i.e., PWP<8:0> = 0x1FE), in addition to the boot
segment, regardless of the state of the Program
Write Protection (PWP) bits (DEVCFG0<18:10>).
If Boot Write Protect is enabled by settin g the BWP
bit (DEVCFG0<24>) = 0, users will not be able to
Page Erase or program the first page of the PWP
user program space. Only user run-time Page
Erase/Program operations are affected, which
does not include a Bulk erase of the entire Flash.
Work around
None.
Please refer to silicon issues 21., 23. , and 24. for
related information
Affected Silicon Revisions
23. Module: Flash Memory
The Progra m W rit e Protectio n (PWP ) bit fi eld is off
by one page rela tive to th e data sh eet defini tion. In
silicon, PWP<8:0> = (n + 1), where ‘n’ is the
DEVCFG0<18:10> value as defined in the data
sheet.
TABLE 6: PWP BITS (DEVCFG0<18:10>)
Work around
Set the PWP<8:0> bits (DEVCFG0<18:10>) =
{DEVCFG0<PWP> - 1 } to correct for the first pag e
protecti on offs et. Please refe r to silicon issues 21.,
22., and 24. for related information.
Affected Silicon Revisions
Device
Flash
Memory
(KB)
Data
Memory
(KB)
Device Silicon Revision
A0 A1 A2 A3
16/32 4/8 X X — —
64 16 X X —
128 32 X X — —
256 16 — — —
256 64 — —
Value Expected Actual
111111111 Disabled Disabled
111111110 Memory below
0x400 is write-
protected
Disabled
111111101 Memory below
0x800 is write-
protected
Memo ry bel ow
0x400 is write-
protected
•
•
•
011111111 Memory below
0x400 00 is write -
protected
Memo ry bel ow
0x3FC00 is write-
protected
Device
Flash
Memory
(KB)
Data
Memory
(KB)
Device Silicon Revision
A0 A1 A2 A3
16/32 4/8 X X — —
64 16 X X —
128 32 X X — —
256 16 — — —
256 64 — —
2011-2018 Microchip Technology Inc. DS80000531J- page 15
PIC32MX1XX/2XX 28/36/44-PIN
24. Module: Flash Memory
Attempts to p rote ct the entire Flash memory using
the follow ing values, will result in no pages being
protected.
Program Wri te Protection bits (DEVCFG0<PWP>):
111101111 = Memory below 0x4000 (16K)
address is write-protected.
111011111 = Memory below 0x8000 (32K)
address is write-protected.
110111111 = Memory below 0x10000 (64K)
address is write-protected.
101111111 = Memory below 0x20000 (128K)
address is write-protected.
Work around
To protect the enti re Flash including the las t pag e,
use the follow i ng val ue s:
DEVCFG0<PWP>:
111110000 = Memory below 0x4000 (16K)
address is write-protected.
111100000 = Memory below 0x8000 (32K)
address is write-protected.
111000000 = Memory below 0x10000 (64K)
address is write-protected.
10000000 = Memory below 0x20000 (128K)
address is write-protected.
Please refer to silicon issues 21., 22. , and 23. for
related information.
Affected Silicon Revisions
25. Module: Power-Saving Mode s
On exit from Sleep mode, both the SLEEP and
IDLE status bits in the RCON register are set.
Work around
Add the following code to the user application at
the point it wakes from Sleep mode:
rcon_var1 = RCON;
// ... enter Sleep mode
if (rcon_var1 & 0x4) Nop();
// If IDLE bit already set p reviously
// before sleep do nothing
else RCONbits.IDLE = 0x0;
// If IDLE bit is not set previously
// and is after Sleep mode then clear
Affected Silicon Revisions
26. Module: CTMU
The CTMU internal temperature sensing diode
does n ot function for V
DD
/AV
DD
operating v oltages
that are less than 2.5V.
Work around
None.
Affected Silicon Revisions
Device
Flash
Memory
(KB)
Data
Memory
(KB)
Device Silicon Revision
A0 A1 A2 A3
16/32 4/8 X X — —
64 16 X X —
128 32 X X — —
256 16 — — —
256 64 — —
Device
Flash
Memory
(KB)
Data
Memory
(KB)
Device Silicon Revision
A0 A1 A2 A3
16/32 4/8 X X — —
64 16 X X —X
128 32 X X — —
256 16 X — — —
256 64 —XX—
Device
Flash
Memory
(KB)
Data
Memory
(KB)
Device Silicon Revision
A0 A1 A2 A3
16/32 4/8 X X — —
64 16 X X —
128 32 X X — —
256 16 — — —
256 64 —XX—
PIC32MX1XX/2XX 28/36/44-PIN
DS80000531J-page 16 2011-2018 Microchip Technology Inc.
27. Module: I
2
C
When the I
2
C module is operating as a Slave,
some reserved bus addresses may be
Acknowledged (ACKed) when they should be not
Acknowledged (NAKed).
As a result, there will be multiple data NAK
interrupts until the Stop condition is asserted.
Work around
When the address interrupt arrives, check the
address to determine if it is actually a reserved
address. If the addres s is a reserved address, set
a flag and use the flag to ignore subsequent data
interrupts. When the Stop condition occurs, clear
the flag.
Affected Silicon Revisions
28. Module: Bus Matrix
The Flash Memory Size register (BMXPFMSZ)
was not pro gram med with the corre ct value.
Work around
Use a fixed number based on the size of the part
being used.
Affected Silicon Revisions
Device
Flash
Memory
(KB)
Data
Memory
(KB)
Device Silicon Revision
A0 A1 A2 A3
16/32 4/8 X X — —
64 16 X X —
128 32 X X — —
256 16 — — —
256 64 —XX—
Device
Flash
Memory
(KB)
Data
Memory
(KB)
Device Silicon Revision
A0 A1 A2 A3
16/32 4/8 --
64 16 Date code pre-1750
128 32 --
256 64 --
256 16 Date code pre-1808
2011-2018 Microchip Technology Inc. DS80000531J- page 17
PIC32MX1XX/2XX 28/36/44-PIN
Data Sheet Clarifications
The foll owing ty pographic c orrections and clar ification s
are to be no ted for the latest ve rsio n o f th e device data
sheet (DS60001168K):
No data sheet clarifications to be reported in this
revision.
Note: Corrections are shown in bold. Where
possible, the original bold text formatting
has been removed for clarity.
PIC32MX1XX/2XX 28/36/44-PIN
DS80000531J-page 18 2011-2018 Microchip Technology Inc.
APPENDIX A: REVISION HISTOR Y
Rev A D ocument (10/2011)
Initial release of this document; issued for revision
A0 sil icon.
Includes silicon issues 1 (Voltage Regulator),
2(Oscillator), 3 (I
2
C), 4 (USB), 5 (ADC), 6 (ADC),
7(ADC), 8 (Parallel Master Port (PMP)), and 9 (I/O
Ports).
Rev B Document (2/2012)
Added silicon revision A1 for 16/32 KB Flash devices.
Added 64/128 KB Flash devices.
Added silicon issues 10 (CPU) and 11 (Oscillator).
Rev C Document (4/2012)
Updated silicon i ssue 10 (CPU).
Added silicon issue 12 (Input Capture).
Rev D Document (10/2012)
Updated silicon i ssue 6 (ADC).
Added silicon issue 13 (Watchdog T imer (WDT)).
Update d the not e in the Si licon D EVREV Values tables
(see Table 1 and Table 2).
Rev E Document (4/2013)
Updated the Device ID for the PIC32MX150F128B in
Table 2.
Updated silicon i ssue 9 (I/O Ports).
Added silicon issues 14 (Non-5V Tolerant Pins) and
15 (5V Tolerant Pins).
Added data sheet clarification 1 (The following typo-
graphic corrections and clarifications are to be noted
for the latest version of the device data sheet
(DS60001168J):).
Rev F Document (6/2014)
Updated Device ID values in Table 1, Table 2, and
Table 3.
Added Silicon DEVREV Values for Devices with
256 KB Flash (see Table 3).
Removed Data Sheet Cla rification 1.
Updated silicon i ssue 9 (I/O Ports).
Added silicon issues 16 (I/O Ports), 17 (I/O Ports),
18 (I/O Ports), 19 (UART), 20 (Timer1), 21 (Flash
Memory), 22 (Flash Memory), 23 (Flash Memory), and
24 (Flash Memory).
Rev G Document (4/2015)
Updated the Rev A3 Silicon DEVREV Values for
Devices with 64/128 KB Flash in Table 2.
Updated the title of Table 3 to: Silicon DEVREV
Values for Devices with 256 KB Flash and 64 KB
RAM.
Added Silicon DEVREV Values for Devices with 256
KB Flash and 16 KB RAM (Table 4).
Updated the Affected Revisions for 256 KB Flash
Memory devices in Table 5 and in silicon issues
22 (Flash Memory) and 23 (Flash Memory).
Updated issue 9 (I/O Ports).
Added Silicon Issues 25 (Power-Saving Modes) and
26 (CTMU).
Added Data Sheet Clarification 1 (Power-Down
Current (I
PD
)).
Rev H Document (4/2016)
Removed Data Sheet Clarification 1.
Added the PIC32MX270FDB device to TABLE 3:.
Added silicon issue 27 ( I
2
C).
Rev J Document (5/2018)
Added silicon issue 28 ( Bus M atrix).
2011-2018 Microchip Technology Inc. DS80000531J- page 19
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be supers ed ed by u pda t es . I t is y o u r r es ponsibil it y to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR
FITNESS FOR PURPOSE. Microchip disclaims all liability
arising from this information and its use. Use of Microchip
devices in life support and/or safety applications is entirely at
the buyer’s risk, and the buyer agrees to defend, indemnify and
hold harmless Microchip from any and all damages, claims,
suits, or expenses resulting from such use. No licenses are
conveyed, implicitly or otherwise, under any Microchip
intellectual property rights unless otherwise stated.
Trademarks
The Microchip name and logo, the Microchip logo, AnyRate,
dsPIC, FlashFlex, flexPWR, Heldo, JukeBlox, KeeLoq,
KeeLoq logo, Kleer, LANCheck, LINK MD, MediaLB, MOST,
MOST logo, MPLAB, OptoLyzer, PIC, PICST ART, PIC32 logo,
RightTouch, SpyNIC, SST, SST Logo, SuperFlash and UNI/O
are registered trademarks of Microchip Technology
Incorporated in the U.S.A. and other countries.
ClockWorks, The Embedded Control Solutions Company,
ETHERSYNCH, Hyper Speed Control, HyperLight Load,
IntelliMOS, mTouch, Precision Edge, and QUIET-WIRE are
registered trademarks of Microchip Technology Incorporated
in the U.S.A.
Analog-for-the-Digital Age, Any Capacitor , AnyIn, AnyOut,
BodyCom, chipKIT, chipKIT logo, CodeGuard, dsPICDEM,
dsPICDEM.net, Dynam ic Average Matching, DAM, ECAN ,
EtherGREEN, In-Circuit Serial Programming, ICSP , Inter-Chip
Connectivity, JitterBlocker, KleerNet, KleerNet logo, MiWi,
motorBench, MPASM , MPF, MPLAB Certified logo, MPLIB,
MPLINK, MultiTRAK, NetDetach, Omniscient Code
Generation, PICDEM, PICDEM .net, PICkit, PICtail,
PureSilicon, RightTouch logo, REAL ICE, Ripple Blocker,
Serial Quad I/O, SQI, SuperSwitcher, SuperSwitc her II, Total
Endurance, TSHARC, USBCheck, VariSense, ViewSpan,
WiperLock, Wireless DNA, and ZENA are trademarks of
Microchip Technology Inc orporat ed in the U.S.A. and other
countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
Silicon Storage Technology is a registered trademark of
Microchip Technology Inc . in other countries.
GestIC is a registered trademarks of Microchip Technology
Germany II GmbH & Co. KG, a subsidiary of Microchip
Technology Inc., in other countries.
All other trademarks mentioned herein are property of their
respective companies.
© 2011-2018, Microchip Technology Incorporated, Printed in
the U.S.A., All Rights Reserved.
ISBN: 978-1-5224-2788-9
Note the following details of the code protection feature on Microchip devices:
• Microchip products meet the specification contained in their particular Microchip Data Sheet.
• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
• Microchip is willing to work with the customer who is concerned about the integrity of their code.
• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly e volving. We at M icrochip are c omm itted t o c ontinuously impr oving t he c ode pr otection feat ures of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such ac ts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue f or relief under that Act.
Microch ip rece iv ed ISO/T S -16 94 9:20 09 certific at ion for i ts worldw id e
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC
®
MCUs and dsPIC
®
DSCs, K
EE
L
OQ
®
code hopping
devices, Serial EEPROMs, microperiph erals, nonvolat ile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
QUALITY MANAGEMENT S
YSTEM
CERTIFIED BY DNV
== ISO/TS 16949
==
DS80000531J-page 20 2011-2018 Microchip Technology Inc.
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Japan - Osaka
Tel: 81-6-6152-7160
Fax: 81-6-6152-9310
Japan - To kyo
Tel: 81-3-6880- 3770
Fax: 81-3-6880-3771
Korea - Daegu
Tel: 82-53-744-4301
Fax: 82-53-744-4302
Korea - Seoul
Tel: 82-2-554-7200
Fax: 82-2-558-5932 or
82-2-558-5934
Malaysia - Kuala Lumpur
Tel: 60-3-6201-9857
Fax: 60-3-6201-9859
Malaysia - Penang
Tel: 60-4-227-8870
Fax: 60-4-227-4068
Philippines - Manila
Tel: 63-2-634-9065
Fax: 63-2-634-9069
Singapore
Tel: 65-6334-8870
Fax: 65-6334-8850
Taiwan - Hsin Chu
Tel: 886-3-5778-366
Fax: 886-3-5770-955
Taiwa n - Ka ohs iung
Tel: 886-7-213-7828
Taiwan - Taipei
Tel: 886-2-2508-8600
Fax: 886-2-2508-0102
Thail and - Bangkok
Tel: 66-2-694-1351
Fax: 66-2-694-1350
EUROPE
Austria - Wels
Tel: 43-7242-2244-39
Fax: 43-7242-2244-393
Denmark - Cop e nha ge n
Tel: 45-4450-2828
Fax: 45-4485-2829
France - Paris
Tel: 33-1-69-53-63-20
Fax: 33-1-69-30-90-79
Germany - Dusseldorf
Tel: 49-2129-3766400
Germany - Karlsruhe
Tel: 49-721-625370
Germany - Munich
Tel: 49-89-627-144-0
Fax: 49-89-627-14 4-44
Italy - Milan
Tel: 39-0331-742611
Fax: 39-0331-466781
Italy - Venice
Tel: 39-049-7625286
Netherlands - Drunen
Tel: 31-416-690399
Fax: 31-416-690340
Poland - Warsaw
Tel: 48-22-3325737
Spain - Ma drid
Tel: 34-91-708-08-90
Fax: 34-91-708-08 -91
Sweden - Stockholm
Tel: 46-8-5090-4654
UK - Wokingham
Tel: 44-118-921-5800
Fax: 44-118-921-5820
Worldwide Sales and Service
07/14/15
