DATASHEET
TWO OUTPUT DIFFERENTIAL BUFFER FOR PCIE GEN3 9DB233
IDT®
TWO OUTPUT DIFFERENTIAL BUFFER FOR PCIE GEN3 1
9DB233 REV D 041012
Description
The 9DB233 zero-delay buffer supports PCIe Gen3
requirements, while being backwards compatible to PCIe
Gen2 and Gen1. The 9DB233 is driven by a differential
SRC output pair from an IDT 932S421 or 932SQ420 or
equivalent main clock generator. It attenuates jitter on the
input clock and has a selectable PLL bandwidth to
maximize performance in systems with or without
Spread-Spectrum clocking. An SMBus interface allows
control of the PLL bandwidth and bypass options, while 2
clock request (OE#) pins make the 9DB233 suitable for
Express Card applications.
Recommended Application
2 output PCIe Gen3 zero-delay/fanout buffer
Output Features
•2 - 0.7V current mode differential HCSL output pairs
Features/Benefits
•OE# pins; suitable for Express Card applications
•PLL or bypass mode; PLL can dejitter incoming clock
•Selectable PLL bandwidth; minimizes jitter peaking in
downstream PLL's
•Spread Spectrum Compatible; tracks spreading input
clock for low EMI
•SMBus Interface; allows control of PLL BW and Mode
Key Specifications
•Cycle-to-cycle jitter < 50 ps
•Output-to-output skew < 50 ps
•PCIe Gen3 phase jitter < 1.0ps RMS
Block Diagram
SPREAD
COMPATIBLE
PLL
CONTROL
LOGIC
SMBDAT
SMBCLK
SRC_IN
SRC_IN#
PLL_BW
IREF
DIF_0
DIF_1
OE1#
OE0#
9DB233
TWO OUTPUT DIFFERENTIAL BUFFER FOR PCIE GEN3
IDT®
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9DB233 REV D 041012
Pin Configuration
Power Distribution Table
PLL_BW 1 20 VDDA
SRC_IN 2 19 GNDA
SRC_IN# 3 18 IREF
vOE0# 4 17 vOE1#
VDD 5 16 VDD
GND 6 15 GND
DIF_0 7 14 DIF_1
DIF_0# 8 13 DIF_1#
VDD 9 12 VDD
SMBDAT 10 11 SMBCLK
9DB233
Note:
Pins preceeded by ' v ' have internal
120K ohm pull down resistors
VDD GND
5,9,12,16 6,15 Differential Outputs
96 SMBUS
20 19 IREF
20 19 Analog VDD & GND for PLL core
Description
Pin Number
9DB233
TWO OUTPUT DIFFERENTIAL BUFFER FOR PCIE GEN3
IDT®
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9DB233 REV D 041012
Pin Descriptions
PIN # PIN
NAME PIN TYPE DESCRIPTION
1 PLL_BW IN 3.3V input for selecting PLL Band Width
0 = low, 1= high
2 SRC_IN IN 0.7 V Differential SRC TRUE input
3 SRC_IN# IN 0.7 V Differential SRC COMPLEMENTARY input
4 vOE0# IN Active low input for enabling DIF pair 0. This pin has an internal pull-down.
1 =disable outputs, 0 = enable outputs
5 VDD PWR Power supply, nominal 3.3V
6 GND PWR Ground pin.
7 DIF_0 OUT 0.7V differential true clock output
8 DIF_0# OUT 0.7V differential Complementary clock output
9 VDD PWR Power supply, nominal 3.3V
10 SMBDAT I/O Data pin of SMBUS circuitry, 5V tolerant
11 SMBCLK IN Clock pin of SMBUS circuitry, 5V tolerant
12 VDD PWR Power supply, nominal 3.3V
13 DIF_1# OUT 0.7V differential Complementary clock output
14 DIF_1 OUT 0.7V differential true clock output
15 GND PWR Ground pin.
16 VDD PWR Power supply, nominal 3.3V
17 vOE1# IN Active low input for enabling DIF pair 1. This pin has an internal pull-down.
1 =disable outputs, 0 = enable outputs
18 IREF OUT
This pin establishes the reference for the differential current-mode output
pairs. It requires a fixed precision resistor to ground. 475ohm is the standard
value for 100ohm differential impedance. Other impedances require
different values. See data sheet.
19 GNDA PWR Ground pin for the PLL core.
20 VDDA PWR 3.3V power for the PLL core.
Pins preceeded by ' v ' have internal 120K ohm pull down resistors
Note:
9DB233
TWO OUTPUT DIFFERENTIAL BUFFER FOR PCIE GEN3
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9DB233 REV D 041012
Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the 9DB233. These ratings, which are standard
values for IDT commercially rated parts, are stress ratings only. Functional operation of the device at these or any other
conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute
maximum rating conditions for extended periods can affect product reliability. Electrical parameters are guaranteed only over
the recommended operating temperature range.
Electrical Characteristics–Clock Input Parameters
Electrical Characteristics–Current Consumption
PARAMETER SYMBOL CONDITIONS
MIN TYP MAX
UNITS NOTES
3.3V Core Supply Voltage VDDA 4.6 V 1,2
3.3V Logic Supply Voltage VDD 4.6 V
1,2
Input Low Voltage V
IL
GND-0.5 V 1
Input High Voltage V
IH
Except for SMBus interface V
DD
+0.5V V 1
Input High Voltage V
IHSMB
SMBus clock and data pins 5.5V V 1
Storage Temperature Ts -65 150 °
C
1
Junction Temperature Tj 125 °C
1
Input ESD protection ESD prot Human Body Model 2000 V 1
1Guaranteed by design and characterization, not 100% tested in production.
2
Operation under these conditions is neither implied nor
g
uaranteed.
TA = TCOM or TIND; Supply Voltage VDD = 3.3 V +/-5%
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS NOTES
Input High Voltage - DIF_IN VI HDI F
Differential inputs
(sin
g
le-ended measurement)
600 800 1150 mV 1
Input Low Voltage - DIF_IN VILDIF
Differential inputs
(single-ended measurement) VSS - 300 0 300 mV 1
Input Common Mode
Volta
e - DIF_IN
VCOM Common Mode Input Voltage 300 400 1000 mV 1
Input Amplitude - DIF_IN V
SWING
Peak to Peak value 300 1450 mV 1
Input Slew Rate - DIF_IN dv/dt Measured differentially 0.4 8 V/ns 1,2
Input Leakage Current I
IN
V
IN
= V
DD ,
V
IN
=GND -5 -0.02 5 uA 1
Input Duty Cycle d
tin
Measurement from differential wavefrom 45 50 55 % 1
Input Jitter - Cycle to Cycle JDI FI n Differential Measurement 0 125 ps 1
1 Guaranteed by design and characterization, not 100% tested in production.
2
Slew rate measured throu
g
h +/-75mV window centered around differential zero
TA = TCOM or TIND; Supply Voltage VDD = 3.3 V +/-5%
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS NOTES
Operating Supply Current I
DD3.3OP
All outputs active @100MHz, C
L
= Full load; 70 80 mA 1
I
DD3.3PD
All diff pairs driven N/A mA 1
IDD3.3PDZ All differential pairs tri-stated N/A mA 1
1
Guaranteed by desi
g
n and characterization, not 100% tested in production.
Powerdown Current
9DB233
TWO OUTPUT DIFFERENTIAL BUFFER FOR PCIE GEN3
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9DB233 REV D 041012
Electrical Characteristics–Input/Supply/Common Parameters
TA = TCOM or TIND; Supply Voltage VDD = 3.3 V +/-5%
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS NOTES
T
COM
Commmercial range 0 70 °C 1
T
IND
Industrial range -40 85 °C 1
Input High Voltage VIH
Single-ended inputs, except SMBus, low
threshold and tri-level inputs
2V
DD + 0.3 V 1
Input Low Voltage VIL
Single-ended inputs, except SMBus, low
threshold and tri-level inputs GND - 0.3 0.8 V 1
I
IN
Single-ended inputs, V
IN
= GND, V
IN
= VDD -5 5 uA 1
IINP
Single-ended inputs
VIN
= 0 V; Inputs with internal pull-up resistors
VIN = VDD; Inputs with internal pull-down resistors
-200 200 uA 1
F
ib
yp
V
DD
= 3.3 V, Bypass mode 10 110 MHz 2
F
i
p
ll
V
DD
= 3.3 V, 100MHz PLL mode 33 100.00 110 MHz 2
Pin Inductance L
p
in
7nH1
C
IN
Logic Inputs, except DIF_IN 1.5 5 pF 1
C
INDIF_IN
DIF_IN differential clock inputs 1.5 2.7 pF 1,4
COUT Output pin capacitance 6 pF 1
Clk Stabilization TSTAB
From VDD Power-Up and after input clock
stabilization or de-assertion of PD# to 1st clock
0.800 1.8 ms 1,2
Input SS Modulation
Frequency fMODIN
Allowable Frequency
(Triangular Modulation) 30 33 kHz 1
OE# Latency tLATOE#
DIF start after OE# assertion
DIF stop after OE# deassertion
1 3 cycles 1,3
Tdrive_PD# tDRVPD
DIF output enable after
PD# de-assertion 300 us 1,3
Tfall t
F
Fall time of control inputs 5 ns 1,2
Trise t
R
Rise time of control inputs 5 ns 1,2
SMBus Input Low Voltage V
ILSMB
0.8 V 1
SMBus Input High Voltage V
IHSMB
2.1 V
DDSMB
V1
SMBus Output Low Voltage V
OLSMB
@ I
PULLUP
0.4 V 1
SMBus Sink Current I
PULLUP
@ V
OL
4mA1
Nominal Bus Voltage V
DDSMB
3V to 5V +/- 10% 2.7 5.5 V 1
SCLK/SDATA Rise Time t
RSMB
(Max VIL - 0.15) to (Min VIH + 0.15) 1000 ns 1
SCLK/SDATA Fall Time t
FSMB
(Min VIH + 0.15) to (Max VIL - 0.15) 300 ns 1
SMBus Operating
Frequency fMAXSMB Maximum SMBus operating frequency 100 kHz 1,5
1
Guaranteed by desi
g
n and characterization, not 100% tested in production.
2
Control input must be monotonic from 20% to 80% of input swin
g
.
5The differential input clock must be running for the SMBus to be active
Ambient Operating
Temperature
Input Current
3
Time from deassertion until out
p
uts are >200 mV
4DIF_IN input
Capacitance
Input Frequency
9DB233
TWO OUTPUT DIFFERENTIAL BUFFER FOR PCIE GEN3
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Electrical Characteristics–DIF 0.7V Current Mode Differential Outputs
Electrical Characteristics–Output Duty Cycle, Jitter, Skew and PLL
Characterisitics
TA = TCOM or TIND; Supply Voltage VDD = 3.3 V +/-5%
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS NOTES
Slew rate Trf Scope avera
g
in
g
on 0.6 2 4
V/ns
1, 2, 3
Slew rate matching ΔTrf Slew rate matching, Scope averaging on 4.2 20 %1, 2, 4
Voltage High VHigh 660 791 850 1
Voltage Low VLow -150 13 150 1
Max Voltage Vmax 801 1150 1
Min Voltage Vmin -300 5 1
Vswin
g
Vswin
g
Scope avera
g
in
g
off 300 1557 mV 1, 2
Crossing Voltage (abs) Vcross_abs Scope averaging off 250 367 550 mV 1, 5
Crossing Voltage (var) Δ-Vcross Scope averaging off 46 140 mV 1, 6
2 Measured from differential waveform
6 The total variation of all Vcross measurements in any particular system. Note that this is a subset of V_cross_min/max (V_cross
absolute
)
allowed. The intent is to limit Vcross induced modulation b
y
settin
g
V_cross_delta to be smaller than V_cross absolute.
mV
Statistical measurement on single-ended signal
using oscilloscope math function. (Scope
averaging on)
Measurement on single ended signal using
absolute value. (Scope averaging off) mV
1Guaranteed by design and characterization, not 100% tested in production. IREF = VDD/(3xRR). For RR = 475Ω (1%), IREF = 2.32mA.
IOH = 6 x IREF and VOH = 0.7V @ ZO=50Ω (100Ω differential impedance).
3 Slew rate is measured through the Vswing voltage range centered around differential 0V. This results in a +/-150mV window around
differential 0V.
4 Matching applies to rising edge rate for Clock and falling edge rate for Clock#. It is measured using a +/-75mV window centered on
the average cross point where Clock rising meets Clock# falling. The median cross point is used to calculate the voltage thresholds the
oscilloscope is to use for the edge rate calculations.
5 Vcross is defined as voltage where Clock = Clock# measured on a component test board and only applies to the differential rising
edge (i.e. Clock rising and Clock# falling).
TA = TCOM or TIND; Supply Voltage VDD = 3.3 V +/-5%
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS NOTES
-3dB point in Hi
g
h BW Mode 2 2.2 4 MHz 1
-3dB point in Low BW Mode 0.4 0.5 1 MHz 1
PLL Jitter Peaking t
JPEAK
Peak Pass band Gain 0.6 1.5 dB 1
Duty Cycle t
D
C
Measured differentially, PLL Mode 45 48 55 % 1
Duty Cycle Distortion tDCD Measured differentially, Bypass Mode @100MHz -2 0.4 2 % 1,4
t
p
dBYP
Bypass Mode, V
T
= 50% 2500 3660 4500 ps 1
t
p
dPLL
Hi BW PLL Mode V
T
= 50% -50 136 350 ps 1
Skew, Output to Output t
sk3
V
T
= 50% 16 50 ps 1
PLL mode 29 50 ps 1,3
Additive Jitter in Bypass Mode 0.2 50 ps 1,3
1Guaranteed by design and characterization, not 100% tested in production.
2 I
RE
F
= V
DD
/(3xR
R
). For R
R
= 475Ω (1%), I
RE
F
= 2.32mA. I
OH
= 6 x I
RE
F
and V
OH
= 0.7V @ Z
O
=50Ω.
3
Measured from differential waveform
4
Duty cycle distortion is the difference in duty cycle between the output and the input clock when the device is operated in bypass mode.
Skew, Input to Output
Jitter, Cycle to cycle tjcyc-cyc
PLL Bandwidth BW
9DB233
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Electrical Characteristics–PCIe Phase Jitter Parameters
TA = TCOM or TIND; Supply Voltage VDD = 3.3 V +/-5%
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Notes
t
jp
hPCIeG1
PCIe Gen 1 34 86 ps (p-p) 1,2,3
PCIe Gen 2 Lo Band
10kHz < f < 1.5MHz 13
ps
(rms) 1,2
PCIe Gen 2 High Band
1.5MHz < f < Nyquist (50MHz) 23.1 ps
(rms) 1,2
tjphPCIeG3
PCIe Gen 3
(PLL BW of 2-4MHz, CDR = 10MHz)
11ps
(rms)
1,2,4
t
jp
hPCIeG1
PCIe Gen 1 2 5 ps (p-p) 1,2,3
PCIe Gen 2 Lo Band
10kHz < f < 1.5MHz
0.2 0.3 ps
(rms)
1,2
PCIe Gen 2 High Band
1.5MHz < f < Nyquist (50MHz) 0.1 0.2 ps
(rms) 1,2
tjphPCIeG3
PCIe Gen 3
(PLL BW of 2-4MHz, CDR = 10MHz) 0.1 0.2 ps
(rms) 1,2,4
1
Applies to all outputs.
4 Subject to final ratification by PCI SIG.
tjphPCIeG2
2
See http://www.pcisi
g
.com for complete specs
tjphPCIeG2
Phase Jitter, PLL Mode
Additive Phase Jitter,
Bypass Mode
3
Sample size of at least 100K cycles. This fi
g
ures extrapolates to 108ps pk-pk @ 1M cycles for a BER of 1-12.
9DB233
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Common Recommendations for Differential Routing Dimension or Value Unit Figure
L1 length, route as non-coupled 50ohm trace 0.5 max inch 1
L2 length, route as non-coupled 50ohm trace 0.2 max inch 1
L3 length, route as non-coupled 50ohm trace 0.2 max inch 1
Rs 33 ohm 1
Rt 49.9 ohm 1
Down Device Differential Routing
L4 length, route as coupled microstrip 100ohm differential trace 2 min to 16 max inch 1
L4 length, route as coupled stripline 100ohm differential trace 1.8 min to 14.4 max inch 1
Differential Routing to PCI Express Connector
L4 length, route as coupled microstrip 100ohm differential trace 0.25 to 14 max inch 2
L4 length, route as coupled stripline 100ohm differential trace 0.225 min to 12.6 max inch 2
S RC Refer en c e Clo ck
HCSL Output Buffer
L1
L1'
Rs
L2
L2'
Rs
L4'
L4
L3L3'
Rt Rt PCI Express
Down Device
REF_CLK Input
Figure 1: Down Device Routing
HCSL Output Buffer
L1
L1'
Rs
L2
L2'
Rs
L4'
L4
L3L3'
Rt Rt PCI Express
Add-in Board
REF_CLK Input
Figure 2: PCI Express Connector Routing
9DB233
TWO OUTPUT DIFFERENTIAL BUFFER FOR PCIE GEN3
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9DB233 REV D 041012
Vdiff Vp-p Vcm R1 R2 R3 R4 Note
0.45v 0.22v 1.08 33 150 100 100
0.58 0.28 0.6 33 78.7 137 100
0.80 0.40 0.6 33 78.7 none 100 ICS874003i-02 input compatible
0.60 0.3 1.2 33 174 140 100 Standard LVDS
R1a = R1b = R1
R2a = R2b = R2
Al terna tive Termi nation for LV DS and othe r Com m on Diffe re ntial S i gnal s (fi gure 3)
HCSL Output Buffer
L1
L1'
R1b
L2
L2'
R1a
L4'
L4
L3
R2a R2b Down Device
REF_CLK Input
Figure 3
L3'
R3 R4
Component Value Note
R5a, R5b 8.2K 5%
R6a, R6b 1K 5%
Cc 0.1 µF
Vcm 0.350 volts
Cabl e Connecte d AC Coupled Appli cation (fi gure 4)
PCIe Device
REF_CLK Input
Figure 4
R5a
L4'
L4
3.3 Volts
R5b
R6a R6b
Cc
Cc
9DB233
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General SMBus Serial Interface Information for 9DB233
How to Write
•Controller (host) sends a start bit
•Controller (host) sends the write address
•IDT clock will acknowledge
•Controller (host) sends the beginning byte location = N
•IDT clock will acknowledge
•Controller (host) sends the byte count = X
•IDT clock will acknowledge
•Controller (host) starts sending Byte N through Byte
N+X-1
•IDT clock will acknowledge each byte one at a time
•Controller (host) sends a Stop bit
How to Read
•Controller (host) will send a start bit
•Controller (host) sends the write address
•IDT clock will acknowledge
•Controller (host) sends the beginning byte location = N
•IDT clock will acknowledge
•Controller (host) will send a separate start bit
•Controller (host) sends the read address
•IDT clock will acknowledge
•IDT clock will send the data byte count = X
•IDT clock sends Byte N+X-1
•IDT clock sends Byte 0 through Byte X (if X(H) was
written to Byte 8)
•Controller (host) will need to acknowledge each byte
•Controller (host) will send a not acknowledge bit
•Controller (host) will send a stop bit
Index Block Write Operation
Controller (Host) IDT (Slave/Receiver)
TstarT bit
Slave Address
WR WRite
ACK
Beginning Byte = N
ACK
Data Byte Count = X
ACK
Beginning Byte N
X Byte
ACK
O
OO
OO
O
Byte N + X - 1
ACK
PstoP bit
Read Address Write Address
D4(H) D5(H)
Index Block Read Operation
Controller (Host) IDT (Slave/Receiver)
TstarT bit
Slave Address
WR WRite
ACK
Beginning Byte = N
ACK
RT Repeat starT
Slave Address
RD ReaD
ACK
Data Byte Count=X
ACK
X Byte
Beginning Byte N
ACK
O
OO
OO
O
Byte N + X - 1
N Not acknowledge
PstoP bit
9DB233
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SMBus Table: Device Control Register, READ/WRITE ADDRESS (D4/D5)
Pin # Name Control Function T
yp
e0 1Defaul
t
Bit 7 SW_EN
Enables SMBus
Control of bite 1
and 0
RW
PLL Functions
controlled by
SMBus
registers
PLL
Functions
controlled by
device pins
1
Bit 6 RW X
Bit 5
RW X
Bit 4 RW X
Bit 3
RW X
Bit 2 RW X
Bit 1 PLL BW #adjust Selects PLL
Bandwidth
RW Low BW High BW 1
Bit 0 PLL Enable Bypasses PLL for
board test RW
PLL bypassed
(fan out mode)
PLL enabled
(ZDB mode) 1
SMBus Table: Output Enable Register
Pin # Name Control Function T
yp
e0 1Defaul
t
Bit 7 RW X
Bit 6
RW X
Bit 5 RW X
Bit 4
RW X
Bit 3 RW X
Bit 2
RW X
Bit 1 RW X
Bit 0 RW X
SMBus Table: Function Select Register
Pin # Name Control Function T
yp
e0 1Defaul
t
Bit 7
RW X
Bit 6 RW X
Bit 5
RW X
Bit 4 RW X
Bit 3
RW X
Bit 2 RW X
Bit 1
RW X
Bit 0 RW X
SMBus Table: Vendor & Revision ID Register
Pin # Name Control Function T
yp
e0 1Defaul
t
Bit 7 RID3 R - - 0
Bit 6
RID2 R - - 0
Bit 5 RID1 R - - 0
Bit 4
RID0 R - - 1
Bit 3 VID3 R - - 0
Bit 2 VID2 R - - 0
Bit 1 VID1 R - - 0
Bit 0 VID0 R - - 1
RESERVED -
RESERVED -
RESERVED
-
VENDOR ID
-
-
-
-
B
y
te 3
-
REVISION ID
-
-
-
-
-
-
-
-
-
-
-
-
B
y
te 2
-
RESERVED -
-
-
B
y
te 1
-
-
-
-
- RESERVED -
- RESERVED -
B
y
te 0
-
- RESERVED
- RESERVED
-
-
RESERVED -
RESERVED -
RESERVED
RESERVED -
RESERVED -
RESERVED
-
-
RESERVED -
RESERVED
-
-
RESERVED -
RESERVED -
RESERVED -
-
RESERVED -
RESERVED
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SMBus Table: DEVICE ID
Pin # Name Control Function T
yp
e0 1Defaul
t
Bit 7 R 0
Bit 6
R 0
Bit 5 R 0
Bit 4
R 0
Bit 3 R 0
Bit 2
R 1
Bit 1 R 1
Bit 0 R 0
SMBus Table: Byte Count Register
Pin # Name Control
Function
Type 0 1 Default
Bit 7 BC7 RW - - 0
Bit 6
BC6 RW - - 0
Bit 5 BC5 RW - - 0
Bit 4
BC4 RW - - 0
Bit 3 BC3 RW - - 0
Bit 2
BC2 RW - - 1
Bit 1 BC1 RW - - 1
Bit 0 BC0 RW - - 0
-
-
-
-
-
Writing to this
register will
configure how
many bytes will be
read back, default
is 06 = 6 bytes.
-
-
-
-
-
-
-
Byte 5
-
-
-
-
-
-
B
y
te 4
-
-
-
Device ID
= 06 Hex
-
-
-
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Marking Diagram
Notes:
1. ###### is the lot number.
2. YYWW is the last two digits of the year and week that the part was assembled.
3. “LF” denotes RoHS compliant package.
4. Bottom marking: country of origin if not USA.
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Package Outline and Package Dimensions (20-pin SSOP, 150 Mil. Wide Body)
INDEX
AREA
1 2
20
D
E1 E
SEATING
PLANE
A1
A
A2
e
- C -
b
aaa C
c
L
Millimeters Inches
Symbol MinMaxMinMax
A 1.35 1.75 0.053 0.069
A1 0.10 0.25 0.004 0.010
A2 -- 1.50 -- 0.059
b 0.20 0.30 0.008 0.012
c 0.18 0.25 0.007 0.010
D 8.55 8.75 0.337 0.344
E 5.80 6.20 0.228 0.244
E1 3.80 4.00 0.150 0.157
e .635 Basic .025 Basic
L 0.40 1.27 0.016 0.050
α0°8°0°8°
aaa -- 0.10 -- 0.004
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Package Outline and Package Dimensions (20-pin TSSOP, 4.4mm Narrow Body)
Ordering Information
"LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant.
“A” is the device revision designator (will not correlate with the datasheet revision).
While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology (IDT) assumes
no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No
other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications
such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not
recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT
does not authorize or warrant any IDT product for use in life support devices or critical medical instruments.
INDEX
AREA
1 2
20
D
E1 E
SEATING
PLANE
A1
A
A2
e
- C -
b
aaa C
c
L
*For reference only. Controlling dimensions in mm.
Millimeters Inches*
Symbol Min Max Min Max
A--1.20--0.047
A1 0.05 0.15 0.002 0.006
A2 0.80 1.05 0.032 0.041
b 0.19 0.30 0.007 0.012
C 0.09 0.20 0.0035 0.008
D 6.40 6.60 0.252 0.260
E 6.40 BASIC 0.252 BASIC
E1 4.30 4.50 0.169 0.177
e 0.65 Basic 0.0256 Basic
L 0.45 0.75 0.018 0.030
α0°8°0°8°
aaa -- 0.10 -- 0.004
Part / Orde r Number Shi pping P ackagi ng P ackage Tem pe rature
9DB233AFLF Tubes 20-pin SSOP 0 to +70°C
9DB233AFLFT Tape and Reel 20-pin SSOP 0 to +70°C
9DB233AFILF Tubes 20-pin SSOP -40 to +85°C
9DB233AFILFT Tape and Reel 20-pin SSOP -40 to +85°C
9DB233AGLF Tubes 20-pin TSSOP 0 to +70°C
9DB233AGLFT Tape and Reel 20-pin TSSOP 0 to +70°C
9DB233AGILF Tubes 20-pin TSSOP -40 to +85°C
9DB233AGILFT Tape and Reel 20-pin TSSOP -40 to +85°C
9DB233
TWO OUTPUT DIFFERENTIAL BUFFER FOR PCIE GEN3
IDT®
TWO OUTPUT DIFFERENTIAL BUFFER FOR PCIE GEN3 16
9DB233 REV D 041012
Revision History
Rev. Who Issue Date Description Page #
A RDW 6/30/2010 Released to final
B RDW 7/12/2010 1. Changed PWD to Default in SMBus tables. 10,11
C RDW 4/14/2011 Changed pull down indicator from '**' to ' v '.
D RDW 4/9/2012 1. Updated typical electrical characteristics to reflect improved performance 3-6
© 2011 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT, ICS, and the IDT logo are trademarks of Integrated
Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks or
registered trademarks used to identify products or services of their respective owners.
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9DB233
TWO OUTPUT DIFFERENTIAL BUFFER FOR PCIE GEN3