LP2951CMX3.3NOPB - NATIONAL SEMICONDUCTOR

LM49100

LM49100 Mono Class AB Audio Sub-System with a True-Ground Headphone

Amplifier

Literature Number: SNAS392E

September 2007

LM49100

Mono Class AB Audio Sub-System with a True-Ground

Headphone Amplifier

General Description

The LM49100 is a fully integrated audio subsystem capable

of delivering 1.275W of continuous average power into a

mono 8Ω bridged-tied load (BTL) with 1% THD+N and with a

5V power supply. The LM49100 also has a stereo true-ground

headphone amplifier capable of 50mW per channel of con-

tinuous average power into a 32Ω single-ended (SE) loads

with 1% THD+N.

The LM49100 has three input channels. One pair of SE inputs

can be used with a stereo signal. The other input channel is

fully differential and may be used with a mono input signal.

The LM49100 features a 32-step digital volume control and

ten distinct output modes. The mixer, volume control, and de-

vice mode select are controlled through an I2C compatible

interface.

Thermal overload protection prevent the device from being

damaged during fault conditions. Superior click and pop sup-

pression eliminates audible transients on power-up/down and

during shutdown.

Key Specifications

■ Power Output at VDD = 5V:

Loudspeaker (LS):

RL = 8Ω, THD+N ≤ 1% 1.275W

Headphone (VDDHP = 2.8V):

RL = 32Ω, THD+N ≤ 1% 50mW

■ Shutdown current 0.01µA

Features

■Mono and stereo inputs

■Thermal Overload Protection

■True-ground Headphone Drivers

■I2C Control Interface

■Input mute attenuation

■2nd Stage headphone attenuator

■32-step digital volume control

■10 Operating Modes

■Minimum external components

■Click and Pop suppression

■Micro-power shutdown

■Available in space-saving 3mm x 3mm 25 bump GR

package

■RF Suppression

Applications

■Mobile Phones

■PDAs

■Laptops

■Portable Electronics

Boomer® is a registered trademark of National Semiconductor Corporation.

LM49100 Mono Class AB Audio Sub-System with a True-Ground Headphone Amplifier

Typical Application

300015o4

FIGURE 1. Typical Audio Amplifier Application Circuit

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LM49100

Connection Diagrams

GR Package

3mm × 3mm × 1mm

300015o3

Top View

Order Number LM49100GR

See NS Package Number GRA25A

GR Package Marking

300015f6

Top View

XY — 2 Digit datecode

TT — Lot traceability

G — Boomer Family

C9 — LM49100GR

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LM49100

Bump Descriptions

Bump Name Description

A1 VDDCP Positive Charge Pump Power Supply

A2 GNDCP Charge Pump Ground

A3 MIN+ Positive Mono Input

A4 BYPASS Half-Supply Bypass

A5 RIN Right Input

B1 C1N Negative Terminal – Charge Pump Flying Capacitor

B2 C1P Positive Terminal – Charge Pump Flying Capacitor

B3 MIN- Negative Mono Input

B4 LIN Left Input

B5 LS− Negative Loudspeaker Output

C1 VSSCP Negative Charge Pump Power Supply

C2 VSSHP Negative Headphone Power Supply

C3 GND Ground

C4 ADDR I2C Address Identification

C5 VDDLS Loudspeaker Power Supply

D1 HPL Left Headphone Output

D2 VDDHP Positive Headphone Power Supply

D3 VDDI2C I2C Power Supply

D4 SDA I2C Data

D5 LS+ Loudspeaker Output Positive

E1 HPR Right Headphone Output

E2 VDDLS Loudspeaker Power Supply

E3 AGND Headphone Signal Ground (See Application Information section).

E4 GND Ground

E5 SCL I2C Clock

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LM49100

Absolute Maximum Ratings (Notes 1, 2)

If Military/Aerospace specified devices are required,

please contact the National Semiconductor Sales Office/

Distributors for availability and specifications.

Supply Voltage (Loudspeaker) 6V

Supply Voltage (Headphone) 3V

Storage Temperature −65°C to +150°C

Input Voltage −0.3V to VDD + 0.3V

Power Dissipation (Note 3) Internally Limited

ESD Susceptibility (Note 4) 2000V

ESD Susceptibility (Note 5) 200V

Junction Temperature 150°C

Thermal Resistance

θJA (GR) 50.2°C/W

Operating Ratings

Temperature Range

TMIN ≤ TA ≤ TMAX −40°C ≤ TA ≤ +85°C

Supply Voltage VDDLS 2.7V ≤ VDDLS ≤ 5.5V

Supply Voltage VDDHP 2.4 V ≤ VDDHP ≤ 2.9V

I2C Voltage (VDDI2C ) 1.7V ≤ VDDI2C ≤ 5.5V

VDDHP ≤ VDDLS

VDDI2C ≤ VDDLS

Electrical Characteristics VDDLS = 3.6V, VDDHP = 2.8V (Notes 1, 2)

The following specifications apply for all programmable gain set to 0 dB, CB = 4.7μF, RL (SP) = 8Ω, RL(HP) = 32Ω, f = 1 kHz unless

otherwise specified. Limits apply for TA = 25°C.

Symbol Parameter Conditions

LM49100 Units

(Limits)

Typical

(Note 6)

Limit

(Note 7)

IDD Supply Current

VDDLS = 3.0V

VDDHP = 2.8V

Modes 1, 3, 5

VIN = 0V, No Load 2.9 mA

Modes 2, 4, 6

VIN = 0V, No Load 3.4 mA

Modes 7, 10, 14

VIN = 0V, No Load 4.8 mA

VDDLS = 3.6V

VDDHP = 2.8V

Modes 1, 3, 5

VIN = 0V, No Load 2.9 4.3 mA (max)

Modes 2, 4, 6

VIN = 0V, No Load 3.5 5.4 mA (max)

Modes 7, 10, 14

VIN = 0V, No Load 4.8 7.4 mA (max)

VDDLS = 5.0V

VDDHP = 2.8V

Modes 1, 3, 5

VIN = 0V, No Load 3.1 mA

Modes 2, 4, 6

VIN = 0V, No Load 3.6 mA

Modes 7, 10, 14

VIN = 0V, No Load 5.0 mA

ISD Shutdown Supply Current Mode 0 0.01 1 µA (max)

VOS Output Offset Voltage

VIN = 0V, Mode 7, Mono 6.0 25 mV (max)

VIN = 0V, Mode 7, Headphone Gain = –24dB 2.2 5.5 mV

VIN = 0V, Mode 7, Headphone Gain = –18dB 2.4 mV (max)

VIN = 0V, Mode 7, Headphone Gain = –12dB 3.2 mV

VIN = 0V, Mode 7, Headphone Gain = 0dB 7 15 mV (max)

POUT Output Power VDDLS = 3.0V

f = 1kHz

RL = 8Ω

10%

425

525

f = 1kHz

RL = 16Ω

10%

RL = 32Ω

10%

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LM49100

Symbol Parameter Conditions

LM49100 Units

(Limits)

Typical

(Note 6)

Limit

(Note 7)

POUT Output Power VDDLS = 3.6V

f = 1kHz

RL = 8Ω

10%

640

790

600 mW (min)

f = 1kHz

RL = 16Ω

10%

RL = 32Ω

10%

46 mW (min)

POUT Output Power VDDLS = 5.0V

f = 1kHz

RL = 8Ω

10%

1275

1575

f = 1kHz

RL = 16Ω

10%

RL = 32Ω

10%

THD+N Total Harmonic Distortion +

Noise VDDLS = 3.0V f = 1kHz

Loudspeaker;

Mode 1, RL =

8Ω, POUT =

215mW

0.05 %

Headphone;

Mode 4, RL =

32Ω, POUT =

25mW

0.02 %

THD+N Total Harmonic Distortion +

Noise VDDLS = 3.6V f = 1kHz

Loudspeaker;

Mode 1, RL =

8Ω, POUT =

320mW

0.05 %

Headphone;

Mode 4, RL =

32Ω, POUT =

25mW

0.02 %

THD+N Total Harmonic Distortion +

Noise VDDLS = 5.0V f = 1kHz

Loudspeaker;

Mode 1, RL =

8Ω, POUT =

630mW

0.035 %

Headphone;

Mode 4, RL =

32Ω, POUT =

25mW

0.02 %

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LM49100

Symbol Parameter Conditions

LM49100 Units

(Limits)

Typical

(Note 6)

Limit

(Note 7)

eNNoise

A-weighted, 0 dB, inputs

terminated to GND, output

referred

Headphone

Mode 2,10 12 µV

Mode 4, 7 13 µV

Mode 6, 14 16 µV

Loudspeaker

Mode 1 14 µV

Mode 3, 7, 10,

14 23 µV

Mode 5 27 µV

TON Turn-on Time 26 ms

TOFF Turn-off Time 1 ms

ZIN Input Impedance

Maximum gain setting 12.5 10

kΩ (min)

kΩ (max)

Maximum attenuation setting 110 90

130

kΩ (min)

kΩ (max)

AVVolume Control

Stereo (Left

and Right

Channels)

Input referred maximum

attenuation −54 –52

–56

dB (min)

dB (max)

Input referred maximum gain 18 17.5

18.5

dB (min)

dB (max)

Mono

Input referred maximum

attenuation −60 –58

–62

dB (min)

dB (max)

Input referred maximum gain 12 11.5

12.5

dB (min)

dB (max)

CMRR Common Mode Rejection Ratio

Headphone Mode 2, f = 217 Hz,

VCM = 1 VPP,RL = 32Ω 64 dB

Loudspeaker Mode 1, f = 217 Hz, VCM = 1 VPP,

RL = 8Ω 58 dB

PSRR Power Supply Rejection Ratio

VRIPPLE = 200mVpp on VDD LS, output referred, inputs terminated to GND, f = 217Hz

LS, Mode 1 90 dB

LS, Mode 3, 7, 10, 14 78 dB

LS, Mode 5 77 dB

PSRR Power Supply Rejection Ratio VRIPPLE = 200mVpp on VDD HP, output referred, inputs terminated to GND, f = 217Hz

LS, Mode 7, 10, 14 83 dB

PSRR Power Supply Rejection Ratio

VRIPPLE = 200mVpp on VDD LS, output referred, inputs terminated to GND, f = 217Hz

HP, Mode 2, 10 90 dB

HP, Mode 4, 7 88 dB

HP, Mode 6, 14 87 dB

PSRR Power Supply Rejection Ratio

VRIPPLE = 200mVpp on VDD HP, output referred, inputs terminated to GND, f = 217Hz

HP, Mode 2, 10 83 dB

HP, Mode 4, 7 83 dB

HP, Mode 6, 14 80 dB

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LM49100

I2C (Notes 2, 7)

The following specifications apply for VDD = 5.0V and 3.3V, TA = 25°C, 2.2V ≤ VDDI2C ≤ 5.5V, unless otherwise specified.

Symbol Parameter Conditions (Note 8) LM49100 Units

(Limits)

Typical

(Note 6)

Limits

(Note 7)

t1I2C Clock Period 2.5 µs (min)

t2I2C Data Setup Time 100 ns (min)

t3I2C Data Stable Time 0 ns (min)

t4Start Condition Time 100 ns (min)

t5Stop Condition Time 100 ns (min)

t6I2C Data Hold Time 100 ns (min)

VIH I2C Input Voltage High 0.7xVDDI2CV (min)

VIL I2C Input Voltage Low 0.3xVDDI2CV (max)

I2C (Notes 2, 7)

The following specifications apply for VDD = 5.0V and 3.3V, TA = 25°C, 1.7V ≤ VDDI2C ≤ 2.2V, unless otherwise specified.

Symbol Parameter Conditions (Note 8) LM49100 Units

(Limits)

Typical

(Note 6)

Limits

(Note 7)

t1I2C Clock Period 2.5 µs (min)

t2I2C Data Setup Time 250 ns (min)

t3I2C Data Stable Time 0 ns (min)

t4Start Condition Time 250 ns (min)

t5Stop Condition Time 250 ns (min)

t6I2C Data Hold Time 250 ns (min)

VIH I2C Input Voltage High 0.7xVDDI2CV (min)

VIL I2C Input Voltage Low 0.3xVDDI2CV (max)

Note 1: All voltages are measured with respect to the GND pin unless other wise specified.

Note 2: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is

functional but do not guarantee specific performance limits. Electrical Characteristics state DC and AC electrical specifications under particular test conditions

which guarantee specific performance limits. This assumes that the device is within the Operating Ratings. Specifications are not guaranteed for parameters

where no limit is given, however, the typical value is a good indication of device performance.

Note 3: The maximum power dissipation must be derated at elevated temperatures and is dictated by TJMAX, θJA, and the ambient temperature, TA. The maximum

allowable power dissipation is PDMAX = (TJMAX – TA)/ θJA or the number given in Absolute Maximum Ratings, whichever is lower. For the LM49100, see power

derating currents for more information.

Note 4: Human body model, 100 pF discharged through a 1.5kΩ resistor.

Note 5: Machine Model, 220pF - 240pF discharged through all pins.

Note 6: Typicals are measured at 25°C and represent the parametric norm.

Note 7: Limits are guaranteed to National’s AOQL (Average Outgoing Quality Level).

Note 8: Please refer to Figure 3 (I2C Timing Diagram).

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LM49100

Typical Performance Characteristics

THD+N vs Frequency

VDD = 3.6V, RL = 8Ω, PO = 320mW

BW = 22kHz, LS, Mode 1

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THD+N vs Frequency

VDD = 3.6V, RL = 32Ω, PO = 25mW

HP, BW = 22kHz, Mode 4,7

300015o6

THD+N vs Frequency

VDD = 3V, RL = 8Ω, PO = 215mW

BW = 22kHz, LS, Mode 1

300015o8

THD+N vs Frequency

VDD = 3V, RL = 32Ω, PO = 25mW

BW = 22kHz, HP, Mode 4, 7

300015q2

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LM49100

THD+N vs Frequency

VDD = 5V, RL = 8Ω, PO = 630mW

BW = 22kHz, Loudspeaker, Mode 1

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THD+N vs Frequency

VDD = 5V, RL = 32Ω, PO = 25mW

BW = 22kHz, Headphone, Mode 4,7

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THD+N vs Output Power

RL = 32Ω, f = 1kHz

BW = 22kHz, HP, Mode 4

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THD+N vs Output Power

RL = 8Ω, f = 1kHz

BW = 22kHz, LS, Mode 1

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Output Power vs Supply Voltage

VDDHP = 2.8V, RL = 8Ω,

f = 1kHz, LS

300015d8

Output Power vs Supply Voltage

VDDHP = 2.8V, RL = 32Ω,

f = 1kHz, HP

300015p8

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LM49100

Power Dissipation vs Output Power

VDD = 3.6V, RL = 8Ω,

f = 1kHz, Mode 1

300015p5

Power Dissipation vs Output Power

VDD = 3V, RL = 8Ω,

f = 1kHz, Mode 1

300015p6

Power Dissipation vs Output Power

VDD = 5V, RL = 8Ω,

f = 1kHz, Mode 1

300015p7

Supply Current vs VDDLS

VDDHP = 2.8V, Mode 1, 3, 5, No Load

30001564

Supply Current vs VDDLS

VDDHP = 2.8V, Mode 2, 4, 6, No Load

30001565

Supply Current vs VDDLS

VDDHP = 2.8V, Mode 7,10, 14, No Load

30001570

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LM49100

PSRR vs Frequency

RL = 32Ω, VRIPPLE = 200mVPP on VDDHP

VDDHP = 2.8V, CB = 4.7μF, Mode 2, 10, HP

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PSRR vs Frequency

RL = 32Ω, VRIPPLE = 200mVPP on VDDHP

VDDHP = 2.8V, CB = 4.7μF, Mode 4, 7, HP

300015k5

PSRR vs Frequency

RL = 32Ω, VRIPPLE = 200mVPP on VDDHP

VDDHP = 2.8V, CB = 4.7μF, Mode 6, HP

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PSRR vs Frequency

RL = 32Ω, VRIPPLE = 200mVPP on VDDLS

VDDLS = 3.6V, CB = 4.7μF, Mode 2, 10, HP

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PSRR vs Frequency

RL = 32Ω, VRIPPLE = 200mVPP on VDDLS

VDDLS = 3.6V, CB = 4.7μF, Mode 4, 7, HP

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PSRR vs Frequency

RL = 32Ω, VRIPPLE = 200mVPP on VDDLS

VDDLS = 3.6V, CB = 4.7μF, Mode 6, 14, HP

300015l2

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LM49100

PSRR vs Frequency

RL = 8Ω, VRIPPLE = 200mVPP on VDDHP

VDDHP = 2.8V, CB = 4.7μF, Mode 7, 10, 14, LS+HP

300015m3

PSRR vs Frequency

RL = 8Ω, VRIPPLE = 200mVPP on VDDLS

VDDLS = 3.6V, CB = 4.7μF, Mode 1, LS

300015l6

PSRR vs Frequency

RL = 8Ω, VRIPPLE = 200mVPP on VDDLS

VDDLS = 3.6V, CB = 4.7μF, Mode 7, 10, 14, LS+HP

300015m0

PSRR vs Frequency

RL = 8Ω, VRIPPLE = 200mVPP on VDDLS

VDDLS = 3.6V, CB = 4.7μF, Mode 3, LS

300015l7

PSRR vs Frequency

RL = 8Ω, VRIPPLE = 200mVPP on VDDLS

VDDLS = 3.6V, CB = 4.7μF, Mode 5, LS

300015l8

Crosstalk vs Frequency

PO = 12mW, f = 1kHz, Mode 4, HP

30001525

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LM49100

LM49100 Control Tables

TABLE 1. I2C Control Register Table

The LM49100 is controlled through an I2C compatible interface. The I2C chip address is 0xF8 (ADR pin = 0) or 0xFAh (ADDR pin

= 1).

D7 D6 D5 D4 D3 D2 D1 D0

Modes Control 0 0 1 1 MC3 MC2 MC1 MC0

HP Volume (Gain)

Control 0 1 INPUT_MU

TE 0 0 HPR_SD HPVC1 HPVC0

Mono Volume

Control 1 0 0 MV4 MV3 MV2 MV1 MV0

Left Volume (Gain)

Control 1 1 0 LV4 LV3 LV2 LV1 LV0

Right Volume (Gain)

Control 1 1 1 RV4 RV3 RV2 RV1 RV0

TABLE 2. Headphone Attenuation Control

The following bits have added for extra headphone output attenuation:

Gain Select HPVC1 HPVC0 Gain, dB

0 0 0 0

1 0 1 −12

2 1 0 −18

3 1 1 −24

TABLE 3. Output Mode Selection

Output

Mode

Number

MC3 MC2 MC1 MC0 Handsfree Mono Output Right HP Output Left HP Output

0 0 0 0 0 SD SD SD

1 0 0 0 1 2 × GM × M SD SD

2 0 0 1 0 SD GHP × (GM × M) GHP × (GM × M)

3 0 0 1 1 2 × (GL × L + GR × R) SD SD

4 0 1 0 0 SD GHP × (GR × R) GHP × (GL × L)

5 0 1 0 1 2 × (GL × L + GR × R

+ GM × M) SD SD

6 0 1 1 0 SD GHP × (GR × R + GM × M) GHP × (GL × L + GM × M)

7 0 1 1 1 2 × (GL × L + GR × R) GHP × (GR × R) GHP × (GL × L)

10 1 0 1 0 2 × (GL × L + GR × R) GHP × (GM × M) GHP × (GM × M)

14 1 1 1 0 2 × (GL × L + GR × R) GHP × (GR × R + GM × M) GHP × (GL × L + GM × M)

GL— Left channel gain

GR — Right channel gain

GM — Mono channel gain

GHP — Headphone Amplifier gain

R — Right input signal

L — Left input signal

SD — Shutdown

M — Mono input signal

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LM49100

TABLE 4. Mono/Stereo Left/Stereo Right Input Gain Control

Volume Step MV4/LV4/RV4 MV3/LV3/RV3 MV2/LV2/RV2 MV1/LV1/RV1 MV0/LV0/RV0 R/L Gain, dB MonoGain,

1 0 0 0 0 0 −54 −60

2 0 0 0 0 1 −47 −53

3 0 0 0 1 0 −40.5 −46.5

4 0 0 0 1 1 −34.5 −40.5

5 0 0 1 0 0 −30.0 −36

6 0 0 1 0 1 −27 −33

7 0 0 1 1 0 −24 −30

8 0 0 1 1 1 −21 −27

9 0 1 0 0 0 −18 −24

10 0 1 0 0 1 −15 −21

11 0 1 0 1 0 −13.5 −19.5

12 0 1 0 1 1 −12 −18

13 0 1 1 0 0 −10.5 −16.5

14 0 1 1 0 1 −9 −15

15 0 1 1 1 0 −7.5 −13.5

16 0 1 1 1 1 −6 −12

17 1 0 0 0 0 −4.5 −10.5

18 1 0 0 0 1 −3 −9

19 1 0 0 1 0 −1.5 −7.5

20 1 0 0 1 1 0 −6

21 1 0 1 0 0 1.5 −4.5

22 1 0 1 0 1 3 −3

23 1 0 1 1 0 4.5 −1.5

24 1 0 1 1 1 6 0

25 1 1 0 0 0 7.5 1.5

26 1 1 0 0 1 9 3

27 1 1 0 1 0 10.5 4.5

28 1 1 0 1 1 12 6

29 1 1 1 0 0 13.5 7.5

30 1 1 1 0 1 15 9

31 1 1 1 1 0 16.5 10.5

32 1 1 1 1 1 18 12

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LM49100

Application Information

MINIMIZING CLICK AND POP

To minimize the audible click and pop heard through a head-

phone, maximize the input signal through the corresponding

volume (gain) control registers and adjust the output amplifier

gain accordingly to achieve the user’s desired signal gain. For

example, setting the output of the headphone amplifier to

-24dB and setting the input volume control gain to 24dB will

reduce the output offset from 7mV (typical) to 2.2mV (typical).

This will reduce the audible click and pop noise significantly

while maintaining a 0dB signal gain.

SIGNAL GROUND NOISE

The LM49100 has proprietary suppression circuitry, which

provides an additional -50dB (typical) attenuation of the head-

phone ground noise and its incursion into the headphone. For

optimum utilization of this feature the headphone jack ground

should connect to the AGND (E3) bump.

300015m9

I2C PIN DESCRIPTION

SDA: This is the serial data input pin.

SCL: This is the clock input pin.

ADDR: This is the address select input pin.

I2C COMPATIBLE INTERFACE

The LM49100 uses a serial bus which conforms to the I2C

protocol to control the chip's functions with two wires: clock

(SCL) and data (SDA). The clock line is uni-directional. The

data line is bi-directional (open-collector). The LM49100's

I2C compatible interface supports standard (100kHz) and fast

(400kHz) I2C modes. In this discussion, the master is the

controlling microcontroller and the slave is the LM49100.

The I2C address for the LM49100 is determined using the

ADDR pin. The LM49100's two possible I2C chip addresses

are of the form 111110X10 (binary), where X1 = 0, if ADDR pin

is logic LOW; and X1 = 1, if ADDR pin is logic HIGH. If the

I2C interface is used to address a number of chips in a system,

the LM49100's chip address can be changed to avoid any

possible address conflicts.

The bus format for the I2C interface is shown in Figure 2. The

bus format diagram is broken up into six major sections:

The "start" signal is generated by lowering the data signal

while the clock signal is HIGH. The start signal will alert all

devices attached to the I2C bus to check the incoming address

against their own address.

The 8-bit chip address is sent next, most significant bit first.

The data is latched in on the rising edge of the clock. Each

address bit must be stable while the clock level is HIGH.

After the last bit of the address bit is sent, the master releases

the data line HIGH (through a pull-up resistor). Then the mas-

ter sends an acknowledge clock pulse. If the LM49100 has

received the address correctly, then it holds the data line LOW

during the clock pulse. If the data line is not held LOW during

the acknowledge clock pulse, then the master should abort

the rest of the data transfer to the LM49100.

The 8 bits of data are sent next, most significant bit first. Each

data bit should be valid while the clock level is stable HIGH.

After the data byte is sent, the master must check for another

acknowledge to see if the LM49100 received the data.

If the master has more data bytes to send to the LM49100,

then the master can repeat the previous two steps until all

data bytes have been sent.

The "stop" sign