SC18IS602BIPW/S8HP - NXP SEMICONDUCTORS

1. General description

The SC18IS602B is designed to serve as an interface between a standard I2C-bus of a

microcontroller and an SPI bus. This allows the microcontroller to communicate directly

with SPI devices through its I2C-bus. The SC18IS602B operates as an I2C-bus

slave-transmitter or slave-receiver and an SPI master. The SC18IS602B controls all the

SPI bus-specific sequences, protocol, and timing. The SC18IS602B has its own internal

oscillator, and it supports four SPI chip select outputs that may be configured as GPIO

when not used.

2. Features and benefits

I2C-bus slave interface operating up to 400 kHz

SPI master operating up to 1.8 Mbit/s

200-byte data buffer

Up to four slave select outputs

Up to four programmable I/O pins

Operating supply voltage: 2.4 V to 3.6 V

Low power mode

Internal oscillator option

Active LOW interrupt output

ESD protection exceeds 2000 V HBM per JESD22-A114, 200 V MM per

JESD22-A115, and 1000 V CDM per JESD22-C101

Latch-up testing is done to JEDEC Standard JESD78 that exceeds 100 mA

Very small 16-pin TSSOP

3. Applications

Converting I2C-bus to SPI

Adding additional SPI bus controllers to an existing system

SC18IS602B

I2C-bus to SPI bridge

Rev. 7 — 21 October 2019 Product data sheet

Product data sheet Rev. 7 — 21 October 2019 2 of 25

NXP Semiconductors SC18IS602B

I2C-bus to SPI bridge

4. Ordering information

4.1 Ordering options

[1] NXP plans to supply the /S8 device with an expected discontinuation in the 2024-2025 timeframe, but in the meantime, Failure Analysis

for /S8 devices will consist of Automated Test Equipment (ATE) and electrical overstress verification along with package and wire bond

validation only. Detailed device failure analysis will not be available; refer to CIN 201708035I.

5. Block diagram

Table 1. Ordering information

Type number Topside

marking Package

Name Description Version

SC18IS602BIPW/S8 IS602B TSSOP16 plastic thin shrink small outline package; 16 leads;

body width 4.4 mm SOT403-1

Table 2. Ordering options

Type number Orderable part nu mbe r Package Packing method Minimum

order

quantity

Temperature

SC18IS602BIPW/S8 SC18IS602BIPW/S8HP[1] TSSOP16 REEL 13" Q4/T2

*STANDARD

MARK SMD

2500 Tamb =40 C to

+85 C

(1) Unused slave select outputs may be used for GPIO.

Fig 1. Block diagram of SC18IS602B

MOSI

SC18IS602B

002aac443

I2C-BUS

INTERRUPT

CONTROL

LOGIC

INT

CONTROL

SCL

RESET

SDA BUFFER

SPI

MISO

SPICLK

SS0

SS1

SS2

SS3

(1)

INTERNAL

OSCILLATOR

Product data sheet Rev. 7 — 21 October 2019 3 of 25

NXP Semiconductors SC18IS602B

I2C-bus to SPI bridge

6. Pinning information

6.1 Pinning

6.2 Pin description

Fig 2. Pin confi gura tio n for TSSOP 16

SC18IS602BIPW/S8

SS0/GPIO0 A2

SS1/GPIO1 A1

RESET A0

VSS SS3/GPIO3

MISO VDD

MOSI SPICLK

SDA SS2/GPIO2

SCL INT

002aac441

Table 3. Pin description

Symbol Pin Type Description

SS0/GPIO0 1 I/O SPI slave select output 0 (active LOW) or GPIO 0

SS1/GPIO1 2 I/O SPI slave select output 1 (active LOW) or GPIO 1

RESET 3 I reset input (active LOW)

VSS 4 - ground supp l y

MISO 5 I Master In, Slave Out

MOSI 6 O Master Out, Slave In

SDA 7 I/O I2C-bus data

SCL 8 I I2C-bus clock

INT 9 O Interrupt output (active LOW). This pin is an open-drain pin.

SS2/GPIO2 10 I/O SPI slave select output 2 (active LOW) or GPIO 2

SPICLK 11 O SPI clock

VDD 12 - supply voltage

SS3/GPIO3 13 I/O SPI slave select output 3 (active LOW) or GPIO 3

A0 14 I address input 0

A1 15 I address input 1

A2 16 I address input 2

Product data sheet Rev. 7 — 21 October 2019 4 of 25

NXP Semiconductors SC18IS602B

I2C-bus to SPI bridge

7. Functional description

The SC18IS602B act s as a br idg e be tw ee n an I2C- bu s and an SP I interfa ce . It allo ws an

I2C-bus master device to communicate with any SPI-enabled device.

7.1 I2C-bus interface

The I2C-bus uses two wires (SDA and SCL) to transfer information between devices

connected to the bus, and it has the following features:

•Bidirectional data transfer between masters and slaves

•Multi-master bus (no central master)

•Arbitration between simultaneou sly transmitting masters without corruption of serial

data on the bus

•Serial clock synchronization allows devices with diff erent bit rates to communicate via

one serial bus

•Serial clock synchronization can be used as a handshake me chanism to suspend and

resume serial transfer

•The I2C-bus may be used for test and diagnostic purposes

A typical I2C-bus configuration is shown in Figure 3. (Refer to NXP Semiconductors

UM10204, “I2C-bus specification and user manual”, at

www.nxp.com/documents/user_manual/UM10204.pdf.)

The SC18IS602B device provides a byte-oriented I2C-bus interface that supports da ta

transfers up to 400 kHz. When the I2C-bus master is reading data from SC18IS602B, the

device will be a slave-transmitter. The SC18IS602B will be a slave-receiver when the

I2C-bus master is sending data. At no time does the SC18IS602B act as an I2C-bus

master, however, it does have the ability to hold the SCL line LOW between bytes to

complete its internal processes.

Fig 3. I2C-bus configuration

RPU

002aac445

VDD

SC18IS602B I2C-BUS

DEVICE I2C-BUS

DEVICE

I2C-bus SDA

SCL

RPU

Product data sheet Rev. 7 — 21 October 2019 5 of 25

NXP Semiconductors SC18IS602B

I2C-bus to SPI bridge

7.1.1 Addressing

The first sev en bits of the firs t byte sent after a START cond ition defines the slave address

of the device being accessed on the bus. The eighth bit determines the direction of the

message. A ‘0’ in the least significant position of the first byte means that the master will

write information to a selected slave. A ‘1’ in this position means that the master will read

information from the slave. When an address is sent, each device in a system compares

the first seven bits after the START condition with its address. If they m atc h, the devic e

considers itself addressed by the master as a slave-receiver or slave-transmitter,

depending on the R/W bit.

A slave address of the SC18IS602B is comprised of a fixed and a programmable part.

The programmable part of the slave address enables the maximum possible number of

such devices to be connected to the I2C-bus. Since the SC18IS602B has three

programmable addr ess bi ts (defined by the A2, A1, and A0 pins), it is possible to have

eight of these devices on the same bus.

The state of the A2, A1, and A0 pins are latched at reset. Changes made after reset will

not alter the address.

When SC18IS602B is busy after the address byte is transmitted, it will not acknowledge

its address.

7.1.2 Write to data buffer

All communications to or from the SC18IS602B occur through the data buffer. The data

buffe r is 200 bytes deep. A message begins with the SC18IS602B address, followed by

the Function ID. Depending upon the Function ID, zero to 200 data bytes can follow.

The SC18IS602B will place the data received into a buffer and continue loading the buffer

until a STOP condition is received. After the STOP condition is detected, further

communications will not be acknowledged until the function designated by the Function ID

has been completed.

7.1.3 SPI read and write - Function ID 01h to 0Fh

Data in the buffer will be sent to the SPI port if the Function ID is 01h to 0Fh. The Function

ID contains the Slave Select (SS) to be used for the transmission on the SPI port. There

are four Slave Selects tha t can be used , with each SS being sele cted by one o f the bits in

Fig 4. Slave address

R/W

002aac446

0 1 0 1 A2 A1 A0

fixed programmable

slave address

Fig 5. Write to data buffer

002aac447

A P

FUNCTION ID

SLAVE ADDRESS 0 TO 200 BYTES A

Product data sheet Rev. 7 — 21 October 2019 6 of 25

NXP Semiconductors SC18IS602B

I2C-bus to SPI bridge

the Function ID. There is no restriction on the number or combinatio n of Slave Selects that

can be enabled for an SPI message . If more th an one SSn pin is enable d at one time, the

user should be aware of possible contention on the data outputs of the SPI slave devices.

The data on the SPI port will contain the same information as the I2C-bus data , but without

the slave address and Function ID. For example, if the message shown in Figure 6 is

transmitted on the I2C-bus, the SPI bus will send the message shown in Figure 7.

The SC18IS602B counts the number of data bytes sent to the I2C-bus port and will

automatically send this same number of bytes to the SPI bus. As the data is transmitted

from the MOSI pin, it is also read from the MISO pin and saved in the data buffer.

Therefore, the old data in th e buf fer is over written. The data in the buffer can then be read

back.

If the data from the SPI bus needs to be returned to the I2C-bus master, the process must

be completed by reading the data buffer. Section 8 gives an example of an SPI read.

7.1.4 Read from buffer

A read from the data buffer requires no Fun ction ID. The slave address with the R/W bit

set to a ‘1’ will cause the SC18IS602B to send the buffer contents to the I2C-bus master.

The buf fer contents are not modifie d during the read process.

A typical write and read from an SPI EEPROM is shown in Section 8.

Table 4. Function ID 01h to 0Fh

76543210

0000SS3SS2SS1SS0

Fig 6. I2C-bus message

Fig 7. SPI message

002aac448

A P

FUNCTION

WSLAVE ADDRESS

write to buffer

DATA 1 A A DATA n A

002aac451

SPI data

DATA 1 DATA n

Fig 8. Read from buffer

002aac449

SLAVE ADDRESS DATA 1 A A DATA n NA

Product data sheet Rev. 7 — 21 October 2019 7 of 25

NXP Semiconductors SC18IS602B

I2C-bus to SPI bridge

7.1.5 Configure SPI Interface - Function ID F0h

The SPI hardware operating mode, data direction, and frequency can be changed by

sending a ‘Configure SPI Interface’ command to the I2C-bus.

After the SC18IS602B addr ess is transmitted on the bus, the Configure SPI Interface

Function ID (F0h) is sent followed by a byte which will define the SPI communications.

The Clock Phase bit (CPHA) allows the user to set the edges for sampling and changing

data. The Clock Polar ity bit (CPOL) allows the user to set the clock polar ity. Figure 19 and

Figure 20 show the different settings of Clock Phase bit CPHA.

Fig 9. Configure SPI Interface

Table 5. Configure SPI Interface (F0h) bit allocation

Bit 7 6 5 4 3 2 1 0

Symbol X X ORDER X MODE1 MODE0 F1 F0

Reset XX0X0000

Table 6. Configure SPI Interface (F0h) bit description

Bit Symbol Description

7:6 - reserved

5 ORDER When logic 0, the MSB of the data word is transmitted first.

If logic 1, the LSB of the data word is transmitted first.

4 - reserved

3:2 MODE1:MODE0 Mode selection

00 - SPICLK LOW when idle; data clocked in on leading edge

(CPOL = 0, CPHA = 0)

01 - SPICLK LOW when idle; data clocked in on trailing edge

(CPOL = 0, CPHA = 1)

10 - SPICLK HIGH when idle; data clocked in on trailing edge

(CPOL = 1, CPHA = 0)

11 - SPICLK HIGH when idle; data clocked in on leading edge

(CPOL = 1, CPHA = 1)

1:0 F1:F0 SPI clock rate

00 - 1843 kHz

01 - 461 kHz

10 - 115 kHz

11 - 58 kHz

002aac450

SLAVE ADDRESS F0h A A

DATA

Product data sheet Rev. 7 — 21 October 2019 8 of 25

NXP Semiconductors SC18IS602B

I2C-bus to SPI bridge

7.1.6 Clear Interrupt - Function ID F1h

An interrupt is generated by the SC18IS602B after any SPI transmission has been

completed. This interrupt can be cleared (INT pin HIGH) by sending a ‘Clear Interrupt’

command. It is not necessary to clear the interrupt; when polling the device, this function

may be ignored.

7.1.7 Idle mode - Function ID F2h

A low-power mode may be entered by sending the ‘Idle Mode’ command.

The Idle mode will be exited when its I2C-bus address is detected.

7.1.8 GPIO Write - Function ID F4h

The state of the pins defined as GPIO may be changed using the Port Write function.

The data byte following the F4h command will determine the state of SS3, SS2, SS1, and

SS0, if they are configured as GPIO. The Port Enable function will define if these pins are

used as SPI Slave Selects or if they are GPIO.

Fig 10. Clear Interrupt

002aac452

SLAVE ADDRESS F1h A

Fig 11. Idle mode

002aac453

SLAVE ADDRESS F2h A

Fig 12. GPIO Write

Table 7. GPIO Write (F0h) bit allocation

Bit 7 6 5 4 3 2 1 0

Symbol X X X X SS3 SS2 SS1 SS0

Reset XXXX0000

002aac454

SLAVE ADDRESS F4h A A

DATA

Product data sheet Rev. 7 — 21 October 2019 9 of 25

NXP Semiconductors SC18IS602B

I2C-bus to SPI bridge

7.1.9 GPIO Read - Function ID F5h

The state of the pins defined as GPIO may be re ad into the SC18IS602B data buf fer using

the GPIO Read function.

Note that this function does not return the value of the GPIO. To receive the GPIO

contents, a one-byte Read Buffer command would be required. The value of the Read

Buffer command will return the following byte.

Data for pins not defined as GPIO are undefined.

A GPIO Read is always performed to update the GPIO data in the buffer. The buffer is

undefined after the GPIO data is read back from the buffer. Therefore, reading data from

the GPIO always requires a two-message sequence (GPIO Read, followed by Read

Buffer).

7.1.10 GPIO Enable - Function ID F6h

At reset, the Slave Select pins (SS0, SS1, SS2 and SS3) are configured to be used as

slave select outputs. If these pins are n ot require d for the SPI fun ctions, they can be u sed

as GPIO after they are enabled as GPIO. Any combination of pins may be configured to

function as GPIO or Slave Selects.

After the GPIO Enable function is sent, the ports defined as GPIO will be configured as

quasi-bidirectional.

The data byte following the F6h command byte will determine which pins can be used as

GPIO. A logic 1 will enable the pin as a GPIO, while a logic 0 will disable GPIO control.

Fig 13. GPIO Read

Table 8. GPIO Read (F5h) bit allocation

76543210

XXXXSS3SS2SS1SS0

002aac455

SLAVE ADDRESS F5h A A

DATA

Fig 14. GPIO Enable

Table 9. GPIO Enable (F6h) bit allocation

76543210

XXXXSS3SS2SS1SS0

002aac456

SLAVE ADDRESS F6h A A

DATA

Product data sheet Rev. 7 — 21 October 2019 10 of 25

NXP Semiconductors SC18IS602B

I2C-bus to SPI bridge

7.1.11 GPIO Configuration - Function ID F7h

The pins defined as GPIO may be configured by software to one of four types on a

pin-by-pin basis. These are: quasi-bidirectional, push-pull, open-drain, and input-only.

Two bits select the output type for each port pin.

The SSn pins defined as GPIO, for example SS0.0 and SS0.1, may be configured by

software to one of four types. These are: quasi-bidirectional, push-pull, open-drain, and

input-only. Two configuration bits in GPIO Configuration register for each pin select the

type for each pin. A pin has Schmitt-triggered input that also has a glitch suppression

circuit.

7.1.11.1 Quasi-bidirectional output configuration

Quasi-bidirectional outputs can be used both as an input and output without the need to

reconfigure the pin . This is possible because when the pin outputs a logic HIGH, it is

weakly driven, allowing an external device to pull the pin LOW. When the pin is driven

LOW, it is driven strongly and able to sink a large current. There are three pull-up

transistors in the quasi-bidirectional output that serve different purposes.

One of these pull-ups, called the ‘very weak’ pull-up, is turned on whenever the port latch

for the pin contains a logic 1. This very weak pull-up sources a very small current that will

pull the pin HIGH if it is left floating.

A second pull-up, called the ‘weak’ pull-up, is turned on when the port latch for the pin

contains a logic 1 and the pin itself is also at a logic 1 level. This pull-up provides the

primary source current for a quasi-bidirectional pin that is outputting a 1. If this pin is

Table 10. GPIO Configuration (F7h) bit allocation

76543210

SS3.1 SS3.0 SS2.1 SS2.0 SS1.1 SS1.0 SS0.1 SS0.0

Table 11. GPIO Configuration (F7h) bit descriptio n

Bit Symbol Description

7 SS3.1 SS3[1:0] = 00: quasi-bidirectional

SS3[1:0] = 01: push-pull

SS3[1:0] = 10: input-only (high-impedance)

SS3[1:0] = 11: open-drain

6 SS3.0

5 SS2.1 SS2[1:0] = 00: quasi-bidirectional

SS2[1:0] = 01: push-pull

SS2[1:0] = 10: input-only (high-impedance)

SS2[1:0] = 11: open-drain

4 SS2.0

3 SS1.1 SS1[1:0] = 00: quasi-bidirectional

SS1[1:0] = 01: push-pull

SS1[1:0] = 10: input-only (high-impedance)

SS1[1:0] = 11: open-drain

2 SS1.0

1 SS0.1 SS0[1:0] = 00: quasi-bidirectional

SS0[1:0] = 01: push-pull

SS0[1:0] = 10: input-only (high-impedance)

SS0[1:0] = 11: open-drain

0 SS0.0

Product data sheet Rev. 7 — 21 October 2019 11 of 25

NXP Semiconductors SC18IS602B

I2C-bus to SPI bridge

pulled LOW by an external device, the weak pull-up turns off, and only the very weak

pull-up remains on. In order to pull the pin LOW under these conditions, the exte rnal

device has to sin k enough current to over power the weak pull-up a nd pull the pin below its

input threshold voltage.

The third pull-up is referr ed to as the ‘strong’ pull-up. This pull-up is used to speed up

LOW-to-HIGH transitions on a quasi-bidirectional pin when th e port latch changes from a

logic 0 to a logic 1. When this occurs, the strong pull-up turns on for two CPU clocks

quickly pulling the pin HIGH.

The quasi-bidirectional pin configuration is shown in Figure 15.

Although the SC18IS602B is a 3 V device, most of the pins are 5 V tolerant. If 5 V is

applied to a pin configured in quasi-bidirectional mode, there will be a current flowing from

the pin to VDD causing extra power consumption. Therefore, applying 5 V to pins

configured in quasi-bidirectional mode is discouraged.

A quasi-bidirectional pin has a Schmitt-triggered input that also has a glitch suppression

circuit.

7.1.11.2 Open-drain output configuration

The open-drain output configuratio n turns off all pull-ups and only drives the pull-down

transistor of the pin when the port latch contains a logic 0. To be used as a logic output, a

pin configured in this manner must have an external pull-up, typically a resistor tied to

VDD. The pull-down for this mode is the same as for the quasi-bidirectional mode.

The open-drain pin configuration is shown in Figure 16.

An open-drain pin has a Schmitt-triggered input that also has a glitch suppression circuit.

Fig 15. Qua si -bidirectional output configurat io n

002aac548

2 SYSTEM

CLOCK

CYCLES weakstrong very

weak

VDD

PPP

VSS

pin latch data

GPIO pin

glitch rejection

input data

Product data sheet Rev. 7 — 21 October 2019 12 of 25

NXP Semiconductors SC18IS602B

I2C-bus to SPI bridge

7.1.11.3 Input-only configuration

The input-only pin configuration is shown in Figure 17. It is a Schmitt-triggered input that

also has a glitch suppression circuit.

7.1.11.4 Push-pull output configuration

The push-pull output configuration has the same pull-down structure as both the

open-drain and the quasi-bidirectional output modes but provides a continuous strong

pull-up when the port latch contains a logic 1. The push-pull mode may be used when

more source current is needed from a pin output.

The push-pull pin configuration is shown in Figure 18.

A push-pull pin has a Schmitt-triggered input that also has a glitch suppression circuit.

Fig 16. Open-drain output configuration

002aab883

VSS

pin latch data

GPIO pin

glitch rejection

input data

Fig 17. Input-only configuration

002aab884

GPIO pin

glitch rejection

input data

Fig 18. Push-pull output configuration

002aab885

strong

pin latch data

GPIO pin

glitch rejection

input data

Product data sheet Rev. 7 — 21 October 2019 13 of 25

NXP Semiconductors SC18IS602B

I2C-bus to SPI bridge

7.2 SPI interface

The SPI interface can support Mode 0 through Mode 3 of the SPI spec ifica tio n an d ca n

operate up to 1.8 Mbit/s. The SPI inter face u ses at least four pi ns : SPICLK, MOSI, MISO,

and Slave Select (SSn).

SSn are the slave select pins. In a typical configuration, an SPI master selects one SPI

device as the curr en t sl av e.

There are actually four SSn pins (SS0, SS1, SS2 and SS3) to allow the SC18IS602B to

communicate with multiple SPI devices.

The SC18IS602B generates the SPICLK (SPI clock) signal in order to send and receive

data. The SCLK, MOSI, and MISO are typica lly tied together between two or more SPI

devices. Data flows from the SC18IS602B (master) to slave on the MOSI pin (Pin 6) and

the data flows from slave to SC18IS602B (master) on the MISO pin (Pin 5).

8. I2C-bus to SPI communications example

The following example describes a typical sequen ce of events requir ed to read the

contents of an SPI-based EEPROM. This example assumes that the SC18IS602B is

configured to respond to address 5 0h. A START condition is shown as ‘ST’, while a STOP

condition is ‘SP’. The data is presented in hexadecimal format.

1. The first message is used to configure the SPI port for mode and frequency.

ST,50,F0,02,SP SPI frequency 115 kHz using Mode 0

2. An SPI EEPROM first requires that a Write Enable command be sent before data can

be written.

ST,50,04,06,SP EEPROM write enable using SS2, assuming the Write Enable is

06h

3. Clear the interrupt. This is not required if using a polling method rather than interrupts.

ST,50,F1,SP Clear interrupt

4. Write the 8 data bytes. The first byte (Functio n ID) tells the SC18IS602B which Slave

Select output to use. This example uses SS2 (shown as 04h). The first byte sent to

the EEPROM is normally 02h for the EEPROM write command. The next one or two

bytes represent the subaddress in the EEPROM. In this example, a two-byte

subaddress is used. Bytes 00 and 30 would cause the EEPROM to write to

subaddress 0030h. The next eight bytes are the eight data bytes that will be written to

subaddresses 0030h through 0037h.

ST,50,04,02,00,30,01,02,03,04,05,06,07,08,SP Write 8 bytes using SS2

5. When an interrupt occurs, do a Clear Interrupt or wa it until the SC18IS602B responds

to its I2C-bus address.

ST,50,F1,SP Clear interrupt

Product data sheet Rev. 7 — 21 October 2019 14 of 25

NXP Semiconductors SC18IS602B

I2C-bus to SPI bridge

6. Read the 8 bytes from the EEPROM. Note that we are writing a command, even

though we are going to perform a read from the SPI port. The Function ID is again

04h, indicating that we are going to use SS2. The EEPROM requires that you send a

03h for a read, followed by the subaddress you would like to read. We are going to

read back the same d ata previously written, so this means that the subaddress should

be 0030h. We would like to read back 8 bytes so we can send eight bytes of FFh to

tell the SC18IS602B to send eight more bytes on MOSI. While it is sending these

eight data byte s, it is also re ad ing the MI SO pin and saving the data in the buffer.

ST,50,04,03,00,30,FF,FF,FF,FF,FF,FF,FF,FF,SP Read 8 bytes using SS2

7. The interrupt can be cleared, if needed.

ST,50,F1,SP Clear interrupt

8. Read back the data buffer. Note that we will actually need to read back 11 data bytes

since the first three bytes sent on the SPI port were the read code (03h) and the two

subaddress bytes.

ST,50,00,00,00,01,02,03,04,05,06,07,08,SP Read the data buffer

You can see that on the I2C-bus the first four bytes do not contain the data from the

SPI bus. The first byte is the SC18IS602B address, followed by three dum my data

bytes. These dummy data bytes correspond to the three bytes sent to the EEPROM

before it actually places data on the bus (command 03h, subaddress 0030h).

9. Limiting values

[1] This product includes circuitry specifically designed for the protection of its internal devices from the damaging effects of excessive static

charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying greater than the rated maximum.

[2] Parameters are valid over the operating temperature range unless otherwise specified. All voltages are with respect to VSS unless

otherwise noted.

[3] Based on package heat transfer, not device power consumption.

Table 12. Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134).[1][2]

Symbol Parameter Conditions Min Max Unit

Tamb(bias) bias ambient temperature operating 55 +125 C

Tstg storage temperature 65 +150 C

Vnvoltage on any other pin referenced to VSS 0.5 +5.5 V

IOH(I/O) HIGH-level output current per input/output pin - 8 mA

IOL(I/O) LOW-level output current per input/output pin - 20 mA

II/O(tot)(max) maximum total I/O current - 120 mA

Ptot/pack total power dissipa tion per package [3] -1.5W

Product data sheet Rev. 7 — 21 October 2019 15 of 25

NXP Semiconductors SC18IS602B

I2C-bus to SPI bridge

10. Static characteristics

[1] Typical ratings are not guaranteed. The values listed are at room temperature, 3 V.

[2] Pin capacitance is characterized but not tested.

[3] Measured with pins in quasi-bidirectional mode.

[4] Measured with pins in high-impedance mode.

[5] Pins in quasi-bidirectional mode with weak pull-up (applies to all pins with pull-ups).

[6] Pins source a transition current when used in quasi-bidirectional mode and externally driven from logic 1 to logic 0. This current is

highest when VI is approximately 2 V.

Table 13. Static characteristics

VDD = 2.4 V to 3.6 V; Tamb =





Cto+85



C (industrial); unless otherwise specified.

Symbol Parameter Conditions Min Typ[1] Max Unit

IDD(oper) opera ting supply current V DD = 3.6 V ; f = 7.3728 MHz - 5.6 6.7 mA

IDD(idle) Idle mode supply current VDD = 3.6 V ; f = 7.3728 MHz - 3.3 3.9 mA

Vth(HL) HIGH-LOW threshold voltage Schmitt trigger input 0.22VDD 0.4VDD -V

Vth(LH) LOW-HIGH threshold voltage Schmitt trigger input - 0.6VDD 0.7VDD V

Vhys hysteresis voltage - 0.2VDD -V

VOL LOW-level output voltage all pins

IOL =20mA - 0.6 1.0 V

IOL =10mA - 0.3 0.5 V

IOL =3.2mA - 0.2 0.3 V

VOH HIGH-level output voltage all pins

IOH =8mA;

push-pull mode VDD 1- - V

IOH =3.2 mA;

push-pull mode VDD 0.7 VDD 0.4 - V

IOH =20 A;

quasi-bidirectional mode VDD 0.3 VDD 0.2 - V

Cig input capacitance at gate [2] --15pF

IIL LOW-level input current logical 0; VI=0.4V [3] --80 A

ILI input leakage current all ports; VI=V

IL or VIH [4] --10 A

ITHL HIGH-LOW transition current all ports; logical 1-to-0;

VI=2.0VatV

DD =3.6V [5][6] 30 - 450 A

RRESET_N(int) internal pull-up resistance on

pin RESET 10 - 30 k

Product data sheet Rev. 7 — 21 October 2019 16 of 25

NXP Semiconductors SC18IS602B

I2C-bus to SPI bridge

11. Dynamic characteristics

Table 14. Dynamic character istics

VDD = 2.4 V to 3.6 V; Tamb =





Cto+85



C (industrial); unless otherwise specified.

Symbol Parameter Conditions Min Typ Max Unit

fosc(RC) internal RC oscillator

frequency nominal f = 7.3728 MHz;

trimmed to 1% at T

amb =25C7.189 - 7.557 MHz

Glitch filter

tgr glitch rejection time RESET pin --50ns

any pin except RESET 125 - - ns

tsa signal acceptance time RESET pin --15ns

any pin except RESET 50 - - ns

SPI master interface

fSPI SPI operating frequency 1.843 MHz - - 1.843 MHz

TSPICYC SPI cycle time 1.843 MHz 543 - - ns

tSPICLKH SPICLK HIGH time 271 - - ns

tSPICLKL SPICLK LOW time 271 - - ns

tSPIDSU SPI data set-up time 100 - - ns

tSPIDH SPI data hold time 100 - - ns

tSPIDV SPI enable to output data

valid time - - 160 ns

tSPIOH SPI output data hold time 0 - - ns

tSPIR SPI rise time SPI outputs (SPICLK, MOSI, MISO) - - 100 ns

SPI inputs (SPICLK, MOSI, MISO, SSn) - - 2000 ns

tSPIF SPI fall time SPI outputs (SPICLK, MOSI, MISO) - - 100 ns

SPI inputs (SPICLK, MOSI, MISO, SSn) - - 2000 ns

Fig 19. SPI master timing (CPHA = 0)

TSPICYC

tSPICLKH tSPICLKL

master LSB/MSB outmaster MSB/LSB out

tSPIDH

tSPIDSU

tSPIF

tSPIOH tSPIDV tSPIR

tSPIDV

tSPIF tSPIR

SPICLK

(CPOL = 0)

(output)

002aac457

SPICLK

(CPOL = 1)

(output)

MISO

(input)

MOSI

(output)

LSB/MSB inMSB/LSB in

tSPICLKL

tSPIF tSPICLKH

tSPIR

Product data sheet Rev. 7 — 21 October 2019 17 of 25

NXP Semiconductors SC18IS602B

I2C-bus to SPI bridge

Fig 20. SPI master timing (CPHA = 1)

TSPICYC

tSPICLKL tSPICLKH

master LSB/MSB outmaster MSB/LSB out

tSPIDH

tSPIDSU

tSPIF

tSPIOH tSPIDV tSPIR

tSPIDV

tSPIR

SPICLK

(CPOL = 0)

(output)

002aac458

SPICLK

(CPOL = 1)

(output)

MISO

(input)

MOSI

(output)

LSB/MSB inMSB/LSB in

tSPICLKH

tSPIF

tSPICLKL

tSPIF tSPIR

tSPIDV

Product data sheet Rev. 7 — 21 October 2019 18 of 25

NXP Semiconductors SC18IS602B

I2C-bus to SPI bridge

12. Package outline

Fig 21. Package outline SOT403-1 (TSSOP16)

UNIT A1A2A3bpcD

(1) E(2) (1)

ELL

pQZywv θ

REFERENCES

OUTLINE

VERSION EUROPEAN

PROJECTION ISSUE DATE

IEC JEDEC JEITA

mm 0.15

0.05 0.95

0.80 0.30

0.19 0.2

0.1 5.1

4.9 4.5

4.3 0.65 6.6

6.2 0.4

0.3 0.40

0.06 8

0.13 0.10.21

DIMENSIONS (mm are the original dimensions)

Notes

1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.

2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.

0.75

0.50

SOT403-1 MO-153 99-12-27

03-02-18

0.25

16 9

detail X

(A )

vMA

0 2.5 5 mm

scale

TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm SOT403-1

max.

1.1

pin 1 index

Product data sheet Rev. 7 — 21 October 2019 19 of 25

NXP Semiconductors SC18IS602B

I2C-bus to SPI bridge

13. Soldering of SMD packages

This text provides a very brief insight into a complex technology. A more in-depth account

of soldering ICs can be found in Application Note AN10365 “Surface mount reflow

soldering description”.

13.1 Introduction to soldering

Soldering is one of the most common methods through which packages are attached to

Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both

the mechanical and the electrical connection. There is no single soldering method that is

ideal for all IC packages. Wave soldering is often preferred when through-hole and

Surface Mount Devices (SMDs) are mixed on on e printed wiring board; however, it is not

suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high

densities that come with increased miniaturization.

13.2 Wave and reflow soldering

W ave soldering is a joining technolo gy in which the joints are mad e by solder coming from

a standing wave of liquid solder . The wave soldering process is suitable for the following:

•Through-hole components

•Leaded or leadless SMDs, which are glued to the surface of the printed circuit board

Not all SMDs can be wave soldered. Packages with solder balls, and some leadless

packages which have solder lands underneath the body, cannot be wave soldered. Also,

leaded SMDs with leads ha ving a pitch smaller than ~0.6 mm cannot be wave soldered,

due to an increased probability of bridging.

The reflow soldering process involves applying solder paste to a board, followed by

component placement and exposure to a temperature profile. Leaded packages,

packages with solder balls, and leadless packages are all reflow solderable.

Key characteristics in both wave and reflow soldering are:

•Board specifications, including the board finish, solder masks and vias

•Package footprints, including solder thieves and orientation

•The moisture sensitivity level of the packages

•Package placement

•Inspection and repair

•Lead-free soldering ve rsus SnPb soldering

13.3 Wave soldering

Key characteristics in wave soldering are:

•Process issues, such as application of adhesive and flux, clinching of leads, board

transport, the so lder wave parameters , an d the time du rin g which com pon en ts ar e

exposed to the wave

•Solder bath specifications, including temperature and impurities

Product data sheet Rev. 7 — 21 October 2019 20 of 25

NXP Semiconductors SC18IS602B

I2C-bus to SPI bridge

13.4 Reflow soldering

Key characteristics in reflow soldering are :

•Lead-free ve rsus SnPb soldering; note th at a lead-free reflow process usua lly leads to

higher minimum peak temperatures (see Figure 22) than a SnPb process, thus

reducing the process window

•Solder paste printing issues including smearing, release, and adjusting the process

window for a mix of large and small components on one board

•Reflow temperature profile; this profile includes preheat, reflow (in which the board is

heated to the peak temperature) an d cooling down. It is imperative that the peak

temperature is high en ough for the solder to make reliable solder joints (a solder paste

characteristic). In addition, the peak temperature must be low en ough that the

packages and/or boards are not damaged. The peak temperature of the package

depends on pack ag e th ickn es s an d volum e an d is classifie d in ac cor d an ce with

Table 15 and 16

Moisture sensitivity precautions, as indicated on the packing, must be respected at all

times.

Studies have shown that small packages reach higher temperatures during reflow

soldering, see Figure 22.

Table 15. SnPb eutectic process (from J-STD-020C)

Package thickness (mm) Package reflow temperature (C)

Volume (mm3)

< 350  350

< 2.5 235 220

 2.5 220 220

Table 16. Lead-free process (from J-STD-020C)

Package thickness (mm) Package reflow temperature (C)

Volume (mm3)

< 350 350 to 2000 > 2000

< 1.6 260 260 260

1.6 to 2.5 260 250 245

> 2.5 250 245 245

Product data sheet Rev. 7 — 21 October 2019 21 of 25

NXP Semiconductors SC18IS602B

I2C-bus to SPI bridge

For further informa tion on temperature profiles, refer to Application Note AN10365

“Surface mount reflow soldering description”.

14. Abbreviations

MSL: Moisture Sensitivity Level

Fig 22. Temperature profiles for large and small components

001aac844

temperature

time

minimum peak temperature

= minimum soldering temperature

maximum peak temperature

= MSL limit, damage level

peak

temperature

Table 17. Abbreviations

Acronym Description

CDM Charged Device Model

CPU Central Processing Unit

EEPROM Electrically Erasable Programmable Read-Only Memory

ESD ElectroStatic Discharge

GPIO General Purpose Input/Output

HBM Hu ma n Body Model

I/O Input/Output

I2C-bus Inter-Integrated Circuit bus

LSB Least Significant Bit

MM Machine Model

MSB Most Significant Bit

SPI Serial Peripheral Interface

Product data sheet Rev. 7 — 21 October 2019 22 of 25

NXP Semiconductors SC18IS602B

I2C-bus to SPI bridge

15. Revision history

Table 18. Revision history

Document ID Release date Data sheet status Change notice Supersedes

SC18IS602B v.7 20191021 Product data sheet - SC18IS602_602B_603 v.6

Modifications: •Removed discontinued versions

SC18IS602B v.6 20171013 Product data sheet 201708035I SC18IS602 _602B_603 v.5.2

Modifications: •Added SC18IS602B/S8

•Updated Section 4.1 “Ordering options”

SC18IS602B v.5.2 20161026 Product data sh eet 2 01610010I SC18IS602_602B_603 v.5.1

Modifications: •Table 2 “Ordering options”, packing method: Device orientation corrected from Q2/T3 to

Q4/T2; no change to device functionality or product identification

SC18IS602B v.5.1 20150211 Product data sheet - SC18IS602_602B_603 v.5

Modifications: •Table 3 “Pin description”: Added “This pin is an open-d ra in pin” to INT pin description

•Updated Section 4 “Ordering information”

SC18IS602B v.5 20100803 Product data sheet SC18IS602_602B_603 v.4

SC18IS602_602B_603 v.4 20080311 Product data sheet - SC18IS602_603 v.3

SC18IS602_603 v.3 20070813 Product data sheet - SC18IS602_603 v.2

SC18IS602_603 v.2 20061213 Product data sheet - SC18IS602_603 v.1

SC18IS602_603 v.1 20060926 Product data sheet - -

Product data sheet Rev. 7 — 21 October 2019 23 of 25

NXP Semiconductors SC18IS602B

I2C-bus to SPI bridge

16. Legal information

16.1 Data sheet status

[1] Please consult the most recently issued document before initiating or completing a design.

[2] The term ‘short data sheet’ is explained in section “Definitions”.

[3] The product status of device (s) describ ed in this docume nt may have change d since this docu ment was published and may dif fer in case of multiple devices. The latest prod uct status

information is available on the Internet at URL http://www.nxp.com.

16.2 Definitions

Draft — The document is a draft version only. The content is still under

internal review and subject to formal approval, which may result in

modifications or additions. NXP Semiconductors does not give any

representations or warranti es as to the accuracy or completeness of

information included herein and shall hav e no liability for the consequences of

use of such information.

Short data sheet — A short data sheet is an extract from a full data sheet

with the same product t ype number(s) and title. A short data sheet is intended

for quick refere nce only and shou ld not be relied upon to contain detailed and

full information. For detailed and full information see the relevant full data

sheet, which is available on request via the local NXP Semiconductors sales

office. In case of any inconsistency or conflict with the short data sheet, the

full data sheet shall prevail.

Product specificatio n — The information and data provided in a Product

data sheet shall define the specification of the prod uct as agreed between

NXP Semiconduct ors and its customer, unless NXP Semiconductors and

customer have explicitly agreed otherwise i n wri ting. In no event however,

shall an agreement be valid in which the NXP Semiconductors product is

deemed to off er functions and qualities beyond those described in the

Product data sheet.

16.3 Disclaimers

Limited warr a nty and liability — Information in this document is believed to

be accurate and reliable. However, NXP Semiconductors does not give any

representations or warranti es, expressed or implied, as to the accuracy or

completeness of such information and shall have no liability for the

consequences of use of such information. NXP Semiconductors takes no

responsibility for the content in this document if provided by an information

source outside of NXP Semiconductors.

In no event shall NXP Semiconductors be liable for any i ndirect, incidental,

punitive, special or consequentia l damages (including - without limitation - lost

profits, lost savings, business interru ption, costs related to the removal or

replacement of any products or re work charges) whether or not such

damages are based on tort (including negligence), warranty, breach of

contract or any other legal theory.

Notwithstanding any damages that customer might incur for any reason

whatsoever , NXP Semiconductors’ aggregate and cumulative liability towards

customer for the products described herei n shall be limited in accordance

with the Terms and conditions of commercial sale of NXP Semiconductors.

Right to make changes — NXP Semiconductors reserves the right to make

changes to information published in this document, including without

limitation specifications and product descriptions, at any time and without

notice. This document supersedes a nd repla ces all information suppli ed prior

to the publication hereof .

Suitability for use — NXP Semiconductors products are not designed,

authorized or warranted to be suitable f or use in life support, life-critical or

safety-critical systems or equipme nt, nor in applications where failure or

malfunction of an NXP Semiconductors product can reasonably be expected

to result in perso nal injury, death or severe property or envi ronmental

damage. NXP Semiconductors and its suppliers accept no liabil i ty for

inclusion and/or use of NXP Semiconductors products in such equipment or

applications and theref ore su ch incl usion and/o r use is at the cu stome r’s own

risk.

Applications — Applications that are described herein for any of these

products are for illustrative purposes only. NXP Semiconductors makes no

representation or warranty th at such applications will be suitable for the

specified use without further testing or modification.

Customers are responsible for the design and ope ration of their applications

and products using NXP Semicondu ctors products, and NXP Se miconductors

accepts no liability for any assistance with applications or customer pro duct

design. It is customer’s sole responsibility to determine whether the NXP

Semiconductors product is suitable and fi t for the customer’s application s and

products planned, as well as for the planned application and use of

customer’s third party customer(s). Customer s should provide appropriate

design and operating safeguards to minimize the risks associated with t heir

applications and products.

NXP Semiconductors does not accept any liability related to any default,

damage, costs or problem which is based on any weakness or default in the

customer’s applications or products, or the application or use by customer’s

third party customer(s). Customer is resp onsible for doing all necessary

testing for th e customer’s applications and products using NXP

Semiconductors products in order to avoid a default of the applicatio ns and

the products or of the application or use by customer’s third party

customer(s). NXP does not accept any liability in this respect.

Limiting values — Stress above one or more limit ing values (as defined in

the Absolute Maximum Ratings System of IEC 60134) will cause permanent

damage to the device. Limiting values are stress ratings only and (proper)

operation of the device at these or any other conditions above those given in

the Recommended operating conditions section (if present) or the

Characteristics sections of this document is not warranted. Constant or

repeated exposure to limiting values will permanent ly and irreversibly affect

the quality and reliability of the device.

Terms and conditions of commercial sale — NXP Semiconductors

products are sold subject to the general terms and conditions of commercial

sale, as published at http://www.nxp.com/profile/terms, unless otherwise

agreed in a valid written individua l agreement. In case an individual

agreement is concluded only the ter m s and conditions of the respective

agreement shall apply. NXP Semiconductors hereby expressly objects to

applying the customer’s general terms and conditions with regar d to t he

purchase of NXP Semiconductors products by customer.

No offer to sell or license — Nothing i n this document may be interpreted or

construed as an of fe r to sell pr oducts that is open for acceptance or the grant,

conveyance or implication of any license under any copyri ghts, patents or

other industrial or intellectual property rights.

Document status[1][2] Product status[3] Definition

Objective [short] data sheet Development This document contains data from the objective specification for product development.

Preliminary [short] data sheet Qualification This document contains data from the preliminary specification.

Product [short] data sh eet Production This document contains the product specification.

Product data sheet Rev. 7 — 21 October 2019 24 of 25

NXP Semiconductors SC18IS602B

I2C-bus to SPI bridge

Export control — This document as well as the item(s) described herein

may be subject to export control regulations. Export might require a prior

authorization from competent authorities.

Non-automotive qualified products — Unless this data sheet expressly

states that this specific NXP Semiconductors product is a utomotive qualified,

the product i s not sui table f or au tomotive use. It is ne ither quali fie d nor test ed

in accordance with automotive testing or application requirements. NXP

Semiconductors accepts no liability for inclusion and/or use of

non-automotive qualified products in automotive equipment or applications.

In the event that customer uses the product for design-in and use in

automotive applications to au tomotive specificat ions and standards, customer

(a) shall use the product without NXP Semiconductors’ warranty of the

product for such au tomotive applications, use and specificatio ns, and (b)

whenever customer uses the product for automotive applications beyond

NXP Semiconductors’ specifications such use shall be solely at customer’s

own risk, and (c) customer fully indemnifies NXP Semiconductors for any

liability, damages or failed product cl aims resulting from custome r design and

use of the product for automotive applications beyond NXP Semiconductors’

standard warranty and NXP Semiconductors’ product specifications.

Translations — A non-English (translated) version of a document is for

reference only. The English version shall prevail in case of any discrepancy

between the translated and English versions.

16.4 Trademarks

Notice: All referenced br ands, product names, service names and tradema rks

are the property of their respective ow ners.

I2C-bus — logo is a trademark of NXP B.V.

17. Contact information

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to : salesaddresses@nxp.com

NXP Semiconductors SC18IS602B

I2C-bus to SPI bridge

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

Date of release: 21 October 2019

Document identifier: SC18IS602B

Please be aware that important notices concerning this document and the product(s)

described herein, have been included in section ‘Legal information’.

18. Contents

1 General description. . . . . . . . . . . . . . . . . . . . . . 1

2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1

3 Applications. . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

4 Ordering information. . . . . . . . . . . . . . . . . . . . . 2

4.1 Ordering options. . . . . . . . . . . . . . . . . . . . . . . . 2

5 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 2

6 Pinning information. . . . . . . . . . . . . . . . . . . . . . 3

6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3

7 Functional description . . . . . . . . . . . . . . . . . . . 4

7.1 I2C-bus interface. . . . . . . . . . . . . . . . . . . . . . . . 4

7.1.1 Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

7.1.2 Write to data buffer. . . . . . . . . . . . . . . . . . . . . . 5

7.1.3 SPI read and write - Function ID 01h to 0Fh . . 5

7.1.4 Read from buffer. . . . . . . . . . . . . . . . . . . . . . . . 6

7.1.5 Configure SPI Interface - Function ID F0h . . . . 7

7.1.6 Clear Interrupt - Fun c tion ID F1h . . . . . . . . . . . 8

7.1.7 Idle mode - Function ID F2h. . . . . . . . . . . . . . . 8

7.1.8 GPIO Write - Function ID F4h. . . . . . . . . . . . . . 8

7.1.9 GPIO Read - Function ID F5h . . . . . . . . . . . . . 9

7.1.10 GPIO Enable - Function ID F6h . . . . . . . . . . . . 9

7.1.11 GPIO Configuration - Function ID F7h . . . . . . 10

7.1.11.1 Quasi-bidirectional output configuration . . . . . 10

7.1.11.2 Open-drain output configuration. . . . . . . . . . . 11

7.1.11.3 Input-only configuration . . . . . . . . . . . . . . . . . 12

7.1.11.4 Push-pull output configuration . . . . . . . . . . . . 12

7.2 SPI interface. . . . . . . . . . . . . . . . . . . . . . . . . . 13

8 I2C-bus to SPI communications example . . . 13

9 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 14

10 Static characteristics. . . . . . . . . . . . . . . . . . . . 15

11 Dynamic characteristics . . . . . . . . . . . . . . . . . 16

12 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 18

13 Soldering of SMD packages . . . . . . . . . . . . . . 19

13.1 Introduction to soldering . . . . . . . . . . . . . . . . . 19

13.2 Wave and reflow soldering . . . . . . . . . . . . . . . 19

13.3 Wave soldering. . . . . . . . . . . . . . . . . . . . . . . . 19

13.4 Reflow soldering. . . . . . . . . . . . . . . . . . . . . . . 20

14 Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 21

15 Revision history. . . . . . . . . . . . . . . . . . . . . . . . 22

16 Legal information. . . . . . . . . . . . . . . . . . . . . . . 23

16.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 23

16.2 Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

16.3 Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 23

16.4 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 24

17 Contact information. . . . . . . . . . . . . . . . . . . . . 24

18 Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25