©2001 Fairch ild Semicond uctor C orpo ration HUF75823D3, HUF75823D3S Rev. B
HUF75823D3, HUF75823D3S
14A, 15 0V, 0.150 Ohm, N-Channel,
UltraFET® Power MOSFET
Packaging
Symbol
Features
• Ultra Low On-Resistan ce
-r
DS(ON) = 0.150Ω, VGS = 10V
• Simulation Models
- Temperature Compensated PSPICE® and SABER™
Electrical Models
- Spice and SABER Thermal Impedance Mo de ls
- www.fairchildsemi.com
• Peak Current vs Pu lse Width Curve
• UIS Rating Curve
Ordering Information
Absolute Maximum Ratings TC = 25oC, Unless Otherwise Specified
Product reliability information can be found at http://www.fairchildsemi.com/products/disc rete/reliability/index.html
For severe environments, see our Autom otive HUFA series.
All Fairchild semiconducto r products are manufactured, assembled and tested under ISO9000 an d QS9000 quality systems c e rtification.
JEDEC TO-251AA JEDEC TO-252AA
DRAIN
(FLANGE)
DRAIN
SOURCE
GATE
HUF75823D3
GATE
SOURCE
DRAIN
(FLANGE)
HUF75823D3S
D
G
S
PART NUMBER PACKAGE BRAND
HUF75823D3 TO-251AA 75823D
HUF75823D3S TO-252AA 75823D
NOT E: When ord ering, use the entire part number. Add the s uffix T
to obtain the variant in tape and reel, e.g., HUF75823D3ST.
HUF75823D3, HUF75823D3S UNITS
Drain to Source Volt age (Not e 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDSS 150 V
Drain to Gate Voltage (RGS = 20kΩ) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDGR 150 V
Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .VGS ±20 V
Drain Current
Continuous (TC= 25oC, VGS = 10V) (Figure 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID
Continuous (TC= 100oC, VGS = 10V) (Figure 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID
Pulsed Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IDM
14
10
Figure 4
A
A
Pulsed Avalanche Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . UIS Figures 6, 14, 15
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PD
Derate Above 25oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
0.57 W
W/oC
Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TJ, TSTG -55 to 175 oC
Maximum Temperature for Soldering
Leads at 0.063in (1.6mm) from Case fo r 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TL
Package Body for 10s, See Techbrief TB334. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Tpkg 300
260
oC
oC
NOTES:
1. TJ = 25oC to 150oC.
CAUTION: Stresses ab ove those liste d in “Absolu te Maximum Rati ngs” may cause per manent damage to the device. This is a stress on ly rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
Data Sheet December 2001
©2001 Fairch ild Semicond uctor C orpo ration HUF75823D3, HUF75823D3S Rev. B
Electrical Specifications TC = 25oC, Unless Otherwise Specified
PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS
OFF STATE SPECIFICATIONS
Drain to Source B reakdown Voltage BVDSS ID = 250µA, VGS = 0V (Figure 11) 150 - - V
Zero Gate Vo ltage Drain C urrent IDSS VDS = 140V, VGS = 0V - - 1 µA
VDS = 135V, VGS = 0V, TC = 150oC - - 250 µA
Gate to Source Leakage Current IGSS VGS = ±20V - - ±100 nA
ON STATE SPECIFICATIONS
Gate to Source Threshold Voltage VGS(TH) VGS = VDS, ID = 250µA (Figure 10) 2 - 4 V
Drain to Source On Resist ance rDS(ON) ID = 14A, VGS = 10V (Figure 9) - 0.125 0.150 Ω
THERMAL SPECIFICATIONS
Thermal Resistance Junction to Case RθJC TO-251 and TO -252 - - 1.76 oC/W
Thermal Resistance Junction to
Ambient RθJA - - 100 oC/W
SWITCHING SPECIFICATIONS (VGS = 10V)
Turn-On Time tON VDD = 75V, ID = 14A
VGS = 10V,
RGS = 12Ω
(Figures 18, 19)
- - 48 ns
Turn-On De lay Time td(ON) -7.7-ns
Rise Time tr-24-ns
Turn-Off De lay Time td(OFF) -45-ns
Fall Time tf-26-ns
Turn-Off T ime tOFF - - 105 ns
GATE CHARGE SPECIFICATIONS
Total Gate Charge Qg(TOT) VGS = 0V to 20V VDD = 75V,
ID = 14A,
Ig(REF) = 1.0mA
(Figures 13, 16, 17)
-4354nC
Gate Charge at 10V Qg(10) VGS = 0V to 10V - 23 29 nC
Threshold Gate Charge Qg(TH) VGS = 0V to 2V - 1.5 1.9 nC
Gate to Source Gate C harge Qgs -3.4-nC
Gate to Drain "Miller" Charge Qgd -8.8-nC
CAPACITANCE SPECIFICATIONS
Input Capacitance CISS VDS = 25V, VGS = 0V,
f = 1MHz
(Figure 12)
- 800 - pF
Output Capacitance COSS - 180 - pF
Reverse Transfer Capacitance CRSS -65-pF
Source to Drain Diode Specifications
PARAMETER S YMBOL TEST CONDITIONS MIN TYP MAX UNITS
Source to D rain Diode Volt age VSD ISD = 14A - - 1.25 V
ISD = 7A - - 1.00 V
Reverse Recovery Time trr ISD = 14A, dISD/dt = 100A/µs - - 150 ns
Reverse Recovered Charge QRR ISD = 14A, dISD/dt = 100A/µs - - 750 nC
HUF75823D3, HUF75823D3S
©2001 Fairch ild Semicond uctor C orpo ration HUF75823D3, HUF75823D3S Rev. B
Typical Performance Curves
FIGURE 1. NORMALIZED POWER DISSIPATION vs
CASE TEMPERATURE FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRE NT vs
CASE TEMPERATURE
FIGURE 3. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE
FIGURE 4. PEAK CURRENT CAPABILITY
T
C
, CASE TEMPERATURE (
o
C)
POWER DISSIPATION MULTIPLIER
00255075100 17
5
0.2
0.4
0.6
0.8
1.0
1.2
125 150
9
15
50 75 100 125 150
025
ID, DRAIN CURRENT (A)
T
C
, CASE TEMPERATURE (
o
C)
V
GS
= 10V
175
3
6
12
0.1
1
2
10
-4
10
-3
10
-2
10
-1
10
0
10
1
0.0110
-5
t, RE CTA NG U LA R P UL SE DU R ATION (s)
Z
θ
JC
, NORMALIZED
THERMAL IMPEDANCE
SINGLE PULS E
NOTES:
DUTY FACTOR: D = t
1
/t
2
PEAK T
J
= P
DM
x Z
θ
JC
x R
θ
JC
+ T
C
P
DM
t
1
t
2
DUTY CYCLE - DESCENDING ORDER
0.5
0.2
0.1
0.05
0.01
0.02
100
200
10 10
-4
10
-3
10
-2
10
-1
10
0
10
1
10
-5
I
DM
, PEAK CU RRENT (A)
t, PULSE WIDTH (s)
TRANSCONDUCTANCE
MAY LIMIT CURRENT
IN THIS REGION
T
C
= 25
o
C
I = I
25
175 - T
C
150
FOR TE MPE RATURES
ABOVE 25
o
C DERATE PEAK
CURRENT AS FOLLOWS:
V
GS
= 10V
HUF75823D3, HUF75823D3S
©2001 Fairch ild Semicond uctor C orpo ration HUF75823D3, HUF75823D3S Rev. B
FIGURE 5. FORWARD BIAS SAFE OPERATING AREA
NOTE: Refer to Fairchild Application Notes AN9321 and AN9322.
FIGURE 6. UNCLAMPED INDUCTIVE SWITCHING
CAPABILITY
FIGURE 7. TRANSFER CHARACTERISTICS FIGURE 8. SATURATION CHARACTERISTICS
FIGURE 9. NORMALIZED DRAIN T O SOURCE ON
RESISTANCE vs JUNCTION TEMPERATURE FIGURE 10. NORMALIZED GATE THRESHOLD VOLTAGE vs
JUNCTION TEMPERATURE
Typical Performance Curves (Continued)
10
10 300
100
1
1V
DS
, DRAIN TO SOURCE VOLTAGE (V)
I
D
, DRAIN CURRENT (A)
T
J
= MAX RATED
T
C
= 25
o
C
SING LE PULSE
100
100
µ
s
10ms
1ms
LIMITED BY r
DS(ON)
AREA MAY BE
OP ERATION IN TH IS
0.5
80
0.001 0.01 0.1 1
0
I
AS
, AVALANCHE CURRENT (A)
tAV, TIME IN AVALANCHE (ms )
STARTING TJ = 25oC
STARTING TJ = 150oC
1
10
1
t
AV
= (L)(I
AS
)/(1 .3*RATED BV
DSS
- V
DD
)
If R = 0
If R
≠
0
t
AV
= (L/R)ln[(I
AS
*R)/(1.3*RATED BV
DSS
- V
DD
) +1]
0.5
0
12
20
28
234 6
ID, DRAIN CURRENT (A)
V
GS
, GA TE TO SOURCE VOLTAGE (V)
PULSE DURATION = 80
µ
s
DUTY CYCLE = 0.5% MAX
V
DD
= 15V
T
J
= 175
o
C
T
J
= 25
o
C
T
J
= -55
o
C
5
4
16
24
8
0
12
20
28
4
16
24
8
0123
4
I
D
, DRAIN CURRENT (A)
VDS, DRAIN TO SOURCE VOLTAGE (V)
VGS = 5V
PULSE DURATION = 80
µ
s
DUTY CYCLE = 0.5% MAX
TC = 25oC
VGS = 10V
VGS = 6V
0.4
0.8
1.2
1.6
2.8
-80 -40 0 40 80 120 200
NORMALIZED DRAIN TO SOURCE
T
J
, JUNCTION TEMPERATURE (
o
C)
ON RESISTANCE
V
GS
= 10V, I
D
= 14A
PULSE DURATION = 80
µ
s
DUT Y CYCL E = 0.5% M AX
160
2.0
2.4
0.6
0.8
1.0
1.2
-80 -40 0 40 80 120 200
NORMALIZED GATE
T
J
, JUNCTION TEMP ERATU RE (
o
C)
V
GS
= V
DS
, I
D
= 250
µ
A
THRESHOLD VOLTAGE
160
HUF75823D3, HUF75823D3S
©2001 Fairch ild Semicond uctor C orpo ration HUF75823D3, HUF75823D3S Rev. B
FIGURE 11. NORMALIZED DRAIN T O SOURCE BREAKDOWN
VOLTAGE vs JUNCTION TEMPERATURE FIGURE 12. CAPACITANCE vs D RAIN TO SOURCE VOLTAGE
NOTE: Refer to Fairchild Application Notes AN7254 and AN7260.
FIGURE 13. GATE CHARGE WAVEFORMS FOR CONSTANT GATE CURRENT
Typical Performance Curves (Continued)
0.9
1.0
1.1
1.2
-80 -40 0 40 80 120 200
T
J
, JUNCTION TEMPERATURE (
o
C)
NORMALIZED DRAIN TO SOURCE
BREAKDOWN VOLTAGE
I
D
= 250
µ
A
160 10
100
1000
3000
0.1 1.0 10 100
C, CAPACITANCE (pF)
V
DS
, DRAIN TO SOURCE VOLTAGE (V)
V
GS
= 0V, f = 1MHz
C
ISS
=
C
GS
+ C
GD
C
RSS
=
C
GD
C
OSS
≅
C
DS
+ C
GD
0
2
4
6
8
10
020
V
GS
, GATE TO SOURCE VOLTAGE (V)
V
DD
= 75V
Q
g
, GATE CHARGE (nC)
I
D
= 14A
I
D
= 7A
WAVEFORMS IN
DES CE N DI NG O R DE R:
10 15 2
5
5
HUF75823D3, HUF75823D3S
©2001 Fairch ild Semicond uctor C orpo ration HUF75823D3, HUF75823D3S Rev. B
Test Circuits and W aveforms
FIGURE 14. UNCLAMPED ENERGY TEST CIRCUIT FIGURE 15. UNCLAMPED ENERGY WAVEFORMS
FIGURE 16. GATE CHARGE TEST CIRCUIT FIGURE 17. GATE CHARGE WAVEFORMS
FIGURE 18. SWITCHING TIME TEST CIRCUIT FIGURE 19. SWITCHING TIME WAVEFORM
tP
VGS
0.01Ω
L
IAS
+
-
VDS
VDD
RG
DUT
VARY tP TO OBTAIN
REQUIRED PEAK IAS
0V
VDD
VDS
BVDSS
tP
IAS
tAV
0
RL
VGS +
-
VDS
VDD
DUT
Ig(REF)
VDD
Qg(TH)
VGS = 2V
Qg(10)
VGS = 10V
Qg(TOT)
VGS = 20
V
VDS
VGS
I
g(REF)
0
0
Qgs Qgd
VGS
RL
RGS DUT
+
-VDD
VDS
VGS
tON
td(ON)
tr
90%
10%
VDS 90%
10%
tf
td(OFF)
tOFF
90%
50%
50%
10% PULSE WIDTH
VGS
0
0
HUF75823D3, HUF75823D3S
©2001 Fairch ild Semicond uctor C orpo ration HUF75823D3, HUF75823D3S Rev. B
PSPICE Ele ctrical Model
.SUBCKT HUF75823 2 1 3 ; rev 18 February 2000
CA 12 8 1.2e-9
CB 15 14 1.3e-9
CIN 6 8 7.4e - 10
DBODY 7 5 DBODYMOD
DBRE AK 5 11 DB REAK MOD
DPLCAP 10 5 DPLCAPMOD
EBREAK 11 7 17 18 1 57.1
EDS 14 8 5 8 1
EGS 13 8 6 8 1
ESG 6 10 6 8 1
EVTH R ES 6 21 19 8 1
EVTEMP 20 6 18 22 1
IT 8 17 1
LDRA IN 2 5 1.0e - 9
LGATE 1 9 3.11e-9
LSOURCE 3 7 3.72e-9
MMED 16 6 8 8 MMEDMOD
MSTRO 16 6 8 8 MSTROMOD
MWEAK 16 21 8 8 MWEAKMOD
RBREAK 17 18 RBREAKMOD 1
RDRAIN 50 16 RDRAINMOD 7. 7e-2
RGATE 9 20 2.13
RLDRAIN 2 5 10
RLGATE 1 9 31.1
RLSOURCE 3 7 37.2
RSLC1 5 51 RSLCMOD 1e-6
RSLC2 5 50 1e3
RSOURCE 8 7 RSOURCEMOD 3.0e-2
RVTHRES 22 8 RVTHRESMOD 1
RVTE M P 18 19 RVTEMPMOD 1
S1A 6 12 13 8 S1AMOD
S1B 13 12 13 8 S1BMOD
S2A 6 15 14 13 S2AMOD
S2B 13 15 14 13 S 2 BMOD
VBAT 22 1 9 DC 1
ESL C 51 50 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e-6*25),3))}
.MODEL DBODYMOD D (IS = 6.5e-13 RS = 1.06e-2 XTI = 5 TRS1 = 2.4e-3 TRS2 = 1.5e-6 CJO = 8.0e-10 TT = 1.1e-7 M = 0.6)
.MODEL DBREAKMOD D (RS = 2. 0TRS1 = 2 .0e- 3TRS2 = 1.0e-6)
.MODEL DPLCAPMOD D (CJO = 8.9e-1 0IS = 1e-3 0M = 0.8)
.MODEL MMEDMOD NMOS (VTO = 3.36 KP = 5 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 2.13)
.MODEL MSTRO M OD NMOS (VTO = 3.84 KP = 63 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u)
.MODEL MWEA KM OD NMOS (VTO = 2 . 89 K P = 0.08 IS = 1 e -30 N = 10 TO X = 1 L = 1u W = 1u RG = 21.3 )
.MODE L RBR EAKMO D RES (TC1 = 1.08e- 3TC 2 = -6.0e-7)
.MODEL RDRAINMOD RES (TC1 = 1.1e-2 TC2 = 2.7e-5)
.MODEL RSLCMOD RES (TC1 = 3.5e-3 TC2 = 2.0e-6)
.MODEL RSOURCEMOD RES (TC1 = 1e-3 TC2 = 1e-6 )
.MODEL RVTHRESMOD RES (TC1 = -2.8e-3 TC2 = -9.0e-6)
.MODEL RVTEMPMOD RES (TC1 = -2.1e- 3TC2 = -9.0e-7)
.MODEL S1AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -5.8 VOFF= -2.4)
.MODEL S1BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -2.4 VOFF= -5.8)
.MODEL S2AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -1.8 VOFF= 0.5)
.MODEL S2BM OD VSWITCH (RON = 1 e-5 ROFF = 0.1 VON = 0.5 VOFF= -1.8)
.ENDS
NOTE: For further discussion of the PSPICE model, consult A New PSPI CE Sub-Circuit for th e Po wer MOSFET Fe a turing Glob al
Temperature Options; IEEE Power El ectronics Specialist Conference Records, 1991, writ t en by William J . Hepp and C. Frank Wheatley.
18
22
+-
6
8
+
-
5
51
+
-
19
8
+-
17
18
6
8
+
-
5
8+
-
RBREAK
RVTEMP
VBAT
RVTHRES
IT
17 18
19
22
12
13
15
S1A
S1B
S2A
S2B
CA CB
EGS EDS
14
8
13
814
13
MWEAK
EBREAK DBODY
RSOURCE
SOURCE
11
73
LSOURCE
RLSOURCE
CIN
RDRAIN
EVTHRES 16
21
8
MMED
MSTRO
DRAIN
2
LDRAIN
RLDRAIN
DBREAK
DPLCAP
ESLC
RSLC1
10
5
51
50
RSLC2
1
GATE RGATE EVTEMP
9
ESG
LGATE
RLGATE 20
+
-
+
-
+
-
6
HUF75823D3, HUF75823D3S
©2001 Fairch ild Semicond uctor C orpo ration HUF75823D3, HUF75823D3S Rev. B
SABER Electrical Model
REV 18 February 2000
templ ate huf75823 n2,n1,n3
electrical n2,n1,n3
{
var i iscl
dp..model dbodymod = (is = 6.5e-13, rs = 1.06e-2, xti = 5, trs1 = 2.4e-3, trs2 = 1.5e-6, cjo = 8.0e-10, tt = 1.1e-7, m = 0.6)
dp..model dbreakmod = (rs = 2.0, trs1 = 2.0e-3, trs2 = 1.0e-6)
dp..mo del dplc apmod = (cjo = 8.9e -10, is = 10e-30, m = 0.8)
m..model mmedmod = (typ e=_n, vto = 3.36, kp = 5, is = 1e-30, tox = 1)
m..model mstrongmod = (type=_n, vto = 3.84, kp = 63, is = 1e-30, tox = 1)
m..model mweakmod = (type=_n, vto = 2.89, kp = 0.08, is = 1e-30, tox = 1)
sw_vcsp..model s1amod = (ron = 1e-5, roff = 0.1, von = -5.8, voff = -2.4)
sw_vcsp..model s1bmod = (ron = 1e-5, roff = 0.1, von = -2.4, voff = -5.8)
sw_vcsp..model s2amod = (ron = 1e-5, roff = 0.1, von = -1.8, voff = 0.5)
sw_vcsp..model s2bmod = (ron = 1e-5, roff = 0.1, von = 0.5, voff = -1.8)
c.ca n12 n8 = 1.2e-9
c.cb n15 n14 = 1.3e-9
c.cin n6 n8 = 7.4e-10
dp.dbody n7 n5 = model=dbodymod
dp.dbreak n5 n11 = model=dbreakmod
dp.dplc ap n10 n5 = model=dplcapmod
i.it n8 n17 = 1
l.ldrain n2 n5 = 1.0e-9
l.lgate n1 n9 = 3.11e-9
l.lsourc e n3 n7 = 3.72e-9
m.mmed n16 n6 n8 n8 = model=mmedmod, l=1u, w=1u
m.mstrong n16 n6 n8 n8 = model=mstrongmod, l=1u, w=1u
m.mweak n16 n21 n8 n8 = model=mweakmod, l=1u, w=1u
res.rbreak n17 n18 = 1, tc1 = 1.08e-3, tc2 = -6.0e-7
res.rdrain n50 n16 = 7.7e-2, tc1 = 1.1e-2, tc2 = 2.7e-5
res.rgate n9 n20 = 2.13
res.r ldrain n2 n5 = 10
res.rlgate n1 n9 = 31.1
res.rlsource n3 n7 = 37.2
res.rs lc1 n5 n51 = 1e-6, tc1 = 3.5e-3, tc2 = 2.0e-6
res.r slc2 n5 n50 = 1e3
res.rs ource n8 n7 = 3.0e-2, tc1 = 1e-3, tc2 = 1e-6
res.rv temp n18 n19 = 1, tc1 = -2.1e-3, tc2 = -9.0e-7
res.rvthres n22 n8 = 1, tc1 = -2.8e-3, tc2 = -9.0e-6
spe.ebreak n11 n7 n17 n18 = 157.1
spe.e ds n14 n8 n5 n8 = 1
spe.e gs n13 n8 n6 n8 = 1
spe.esg n6 n10 n6 n8 = 1
spe.evtemp n20 n6 n18 n22 = 1
spe.evthres n6 n21 n19 n8 = 1
sw_vcsp.s1a n6 n12 n13 n8 = model=s1amod
sw_vcsp.s1b n13 n12 n13 n8 = model=s1bmod
sw_vcsp.s2a n6 n15 n14 n13 = model=s2amod
sw_vcsp.s2b n13 n15 n14 n13 = model=s2bmod
v.vbat n22 n19 = dc=1
equations {
i (n51->n50) +=iscl
iscl: v(n51,n50) = ((v(n5,n51)/(1e-9+abs(v(n5 ,n51))))*((abs(v(n5,n51)*1e6/25))** 3))
}
}
18
22
+-
6
8
+
-
19
8
+-
17
18
6
8
+
-
5
8+
-
RBREAK
RVTEMP
VBAT
RVTHRES
IT
17 18
19
22
12
13
15
S1A
S1B
S2A
S2B
CA CB
EGS EDS
14
8
13
814
13
MWEAK
EBREAK DBODY
RSOURCE
SOURCE
11
73
LSOURCE
RLSOURCE
CIN
RDRAIN
EVTHRES 16
21
8
MMED
MSTRO
DRAIN
2
LDRAIN
RLDRAIN
DBREAK
DPLCAP
ISCL
RSLC1
10
5
51
50
RSLC2
1
GATE RGATE EVTEMP
9
ESG
LGATE
RLGATE 20
+
-
+
-
+
-
6
HUF75823D3, HUF75823D3S
©2001 Fairch ild Semicond uctor C orpo ration HUF75823D3, HUF75823D3S Rev. B
SPICE Thermal Model
REV 25 October 1999
HUF75823D
CTHERM1 th 6 1.40e-3
CTHERM2 6 5 5 .55e-3
CTHERM3 5 4 5 .65e-3
CTHERM4 4 3 6 .10e-3
CTHERM5 3 2 9 .80e-3
CTHERM6 2 tl 7.70e-2
RTHERM1 th 6 1.10e-2
RTHERM2 6 5 5 .80e-2
RTHERM3 5 4 1 .35e-1
RTHERM4 4 3 3 .60e-1
RTHERM5 3 2 4 .13e-1
RTHERM6 2 tl 4.30e-1
SABER Thermal Model
SABER thermal model HUF75823D
template thermal_model th tl
thermal_c th, tl
{
ctherm.ctherm 1 t h 6 = 1.40e-3
ctherm.ctherm 2 6 5 = 5.55e-3
ctherm.ctherm 3 5 4 = 5.65e-3
ctherm.ctherm 4 4 3 = 6.10e-3
ctherm.ctherm 5 3 2 = 9.80e-3
ctherm.ctherm6 2 tl = 7.70e-2
rtherm.rtherm1 th 6 = 1.10e-2
rtherm.rtherm2 6 5 = 5.80e-2
rtherm.rtherm3 5 4 = 1.35e-1
rtherm.rtherm4 4 3 = 3.60e-1
rtherm.rtherm5 3 2 = 4.13e-1
rtherm.rtherm6 2 t l = 4.30e- 1
}
RTHERM4
RTHERM6
RTHERM5
RTHERM3
RTHERM2
RTHERM1
CTHERM4
CTHERM6
CTHERM5
CTHERM3
CTHERM2
CTHERM1
tl
2
3
4
5
6
th JUNCTION
CASE
HUF75823D3, HUF75823D3S
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