INDUSTRIAL TEMPERATURE RANGE
IDT74ALVCH32374
3.3V CMOS 32-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP
1
AUGUST 2009INDUSTRIAL TEMPERATURE RANGE
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
©2009 Integrated Device Technology, Inc. DSC-4909/5
FEATURES:
• 0.5 MICRON CMOS Technology
• Typical tSK(o) (Output Skew) < 250ps
• ESD > 2000V per MIL-STD-883, Method 3015; > 200V using
machine model (C = 200pF, R = 0)
•VCC = 3.3V ± 0.3V, Normal Range
•VCC = 2.7V to 3.6V, Extended Range
•VCC = 2.5V ± 0.2V
• CMOS power levels (0.4μμ
μμ
μ W typ. static)
• Rail-to-Rail output swing for increased noise margin
• Available in 96-ball LFBGA package
FUNCTIONAL BLOCK DIAGRAM
DRIVE FEATURES:
• High Output Drivers: ±24mA
• Suitable for Heavy Loads
APPLICATIONS:
• 3.3V high speed systems
• 3.3V and lower voltage computing systems
IDT74ALVCH32374
3.3V CMOS 32-BIT
EDGE-TRIGGERED D-TYPE
FLIP-FLOP WITH 3-STATE
OUTPUTS AND BUS-HOLD
DESCRIPTION:
This 32-bit edge-triggered D-type flip-flop is built using advanced dual
metal CMOS technology. This high-speed, low-power register is ideal for
use as a buffer register for data synchronization and storage. The Output
Enable (OE) and clock (CLK) controls are organized to operate the device
as four 8-bit registers, two 16-bit registers, or one 32-bit register with
common clock. Flow-through organization of signal pins simplifies layout. All
inputs are designed with hysteresis for improved noise margin.
The ALVCH32374 has been designed with a ±24mA output driver. This
driver is capable of driving a moderate to heavy load while maintaining
speed performance.
The ALVCH32374 has “bus-hold” which retains the inputs’ last state
whenever the input goes to a high impedance. This prevents floating inputs
and eliminates the need for pull-up/down resistor.
1
OE
D
C
1
CLK
1
D
1
1
Q
1
TO SEVEN OTHER CHANNELS
3
OE
D
C
3
CLK
3
D
1
3
Q
1
TO SEVEN OTHER CHANNELS
2
OE
D
C
2
CLK
2
D
1
2
Q
1
TO SEVEN OTHER CHANNELS
4
OE
D
C
4
CLK
4
D
1
4
Q
1
TO SEVEN OTHER CHANNELS
A3
A4
A5
H3
H4
E5
J3
J4
J5
T3
T4
N5
E2
A2 J2
N2
INDUSTRIAL TEMPERATURE RANGE
2
IDT74ALVCH32374
3.3V CMOS 32-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP
LFBGA
TOPVIEW
96 BALL LFBGA PACKAGE ATTRIBUTES
PIN CONFIGURATION
1.5mm Max.
1.4mm Nom.
1.3mm Min.
0.8mm
6
5
4
3
2
1
TOP VIEW
ABCDE FGHJKLMNPR T
ABC DEFGHJK LMNPRT
6
5
4
3
2
1
13.5mm
5.5mm
ABCEFGHJKLMNP
DT
R
6
5
4
3
2
1
1
D
61
D
8
2
D
1
2
D
22
D
4
2
D
8
2
OE
1
D
4
1
D
51
D
7
2
D
62
D
7
2
D
32
D
5
1
D
2
1
D
3
1
D
1
GND
3
D
8
3
D
23
D
4
4
D
14
D
3
4
D
2
3
D
33
D
5
4
D
4
3
D
1
4
D
6
GND GND
1
Q
1
V
CC
GND V
CC
1
Q
2
1
Q
3
4
Q
6
4
Q
8
GND GND
2
Q
22
Q
4
1
Q
4
1
Q
51
Q
7
2
Q
62
Q
7
3
Q
7
4
Q
2
3
Q
33
Q
5
4
Q
4
3
Q
1
1
Q
61
Q
8
2
Q
12
Q
8
2
Q
32
Q
5
3
Q
63
Q
8
3
Q
23
Q
4
4
Q
14
Q
3
GND
V
CC
GND
V
CC
GND GND
V
CC
GND
GND V
CC
GND
V
CC
3
D
7
3
D
6
1
OE
1
CLK
3
CLK
4
D
54
D
8
4
D
7
4
OE
4
Q
7
4
Q
5
V
CC
GND
GND
3
OE
2
CLK
GND
4
CLK
INDUSTRIAL TEMPERATURE RANGE
IDT74ALVCH32374
3.3V CMOS 32-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP
3
Pin Names Description
xDx Data Inputs(1)
xCLK Clock Inputs
xQx 3-State Outputs
xOE 3-State Output Enable Inputs (Active LOW)
PIN DESCRIPTION
Symbol Description Max Unit
VTERM(2) Terminal Voltage with Respect to GND –0.5 to +4.6 V
VTERM(3) Terminal Voltage with Respect to GND –0.5 to VCC+0.5 V
TSTG Storage Temperature –65 to +150 °C
IOUT DC Output Current –50 to +50 mA
IIK Continuous Clamp Current, ±50 mA
VI < 0 or VI > VCC
IOK Continuous Clamp Current, VO < 0 –50 mA
ICC Continuous Current through each ±100 mA
ISS VCC or GND
ABSOLUTE MAXIMUM RATINGS(1)
NOTES:
1 . Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
2. VCC terminals.
3. All terminals except VCC.
NOTE:
1. These pins have "Bus-Hold". All other pins are standard inputs, outputs, or I/Os.
FUNCTION TABLE (EACH FLIP-FLOP)(1)
NOTES:
1 . H = HIGH Voltage Level
L = LOW Voltage Level
X = Don’t Care
Z = High Impedance
↑ = LOW-to-HIGH Transition
2. Output level of Q before the indicated steady-state conditions were established.
Inputs Outputs
xOE xCLK xDx xQx
L↑HH
L↑LL
L H or L X Q(2)
HX X Z
NOTE:
1. As applicable to the device type.
Symbol Parameter(1) Conditions Typ. Max. Unit
CIN Input Capacitance VIN = 0V 5 7 pF
COUT Output Capacitance VOUT = 0V 7 9 pF
CI/O I/O Port Capacitance VIN = 0V 7 9 pF
CAPACITANCE (TA = +25°C, F = 1.0MHz)
INDUSTRIAL TEMPERATURE RANGE
4
IDT74ALVCH32374
3.3V CMOS 32-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP
Symbol Parameter Test Conditions Min. Typ.(1) Max. Unit
VIH Input HIGH Voltage Level VCC = 2.3V to 2.7V 1.7 — — V
VCC = 2.7V to 3.6V 2 — —
VIL Input LOW Voltage Level VCC = 2.3V to 2.7V — — 0.7 V
VCC = 2.7V to 3.6V — — 0.8
IIH Input HIGH Current VCC = 3.6V VI = VCC ——±5µA
IIL Input LOW Current VCC = 3.6V VI = GND — — ±5µA
IOZH High Impedance Output Current VCC = 3.6V VO = VCC ——±10 µA
IOZL (3-State Output pins) VO = GND — — ±10
VIK Clamp Diode Voltage VCC = 2.3V, IIN = –18mA — –0.7 –1.2 V
VHInput Hysteresis VCC = 3.3V — 100 — mV
ICCL Quiescent Power Supply Current VCC = 3.6V — 0.1 40 µA
ICCH VIN = GND or VCC
ICCZ
ΔICC Quiescent Power Supply Current One input at VCC - 0.6V, other inputs at VCC or GND — — 750 µA
Variation
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
Operating Condition: TA = –40°C to +85°C
NOTE:
1. Typical values are at VCC = 3.3V, +25°C ambient.
BUS-HOLD CHARACTERISTICS
Symbol Parameter(1) Test Conditions Min. Typ.(2) Max. Unit
IBHH Bus-Hold Input Sustain Current VCC = 3V VI = 2V – 75 — — µA
IBHL VI = 0.8V 75 — —
IBHH Bus-Hold Input Sustain Current VCC = 2.3V VI = 1.7V – 45 — — µA
IBHL VI = 0.7V 45 — —
IBHHO Bus-Hold Input Overdrive Current VCC = 3.6V VI = 0 to 3.6V — — ±500 µA
IBHLO
NOTES:
1. Pins with Bus-Hold are identified in the pin description.
2. Typical values are at VCC = 3.3V, +25°C ambient.
INDUSTRIAL TEMPERATURE RANGE
IDT74ALVCH32374
3.3V CMOS 32-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP
5
OPERATING CHARACTERISTICS, TA = 25°C
VCC = 2.5V ± 0.2V VCC = 3.3V ± 0.3V
Symbol Parameter Test Conditions Typical Typical Unit
CPD Power Dissipation Capacitance Outputs enabled CL = 0pF, f = 10Mhz 62 60 pF
CPD Power Dissipation Capacitance Outputs disabled 32 36
NOTES:
1. See TEST CIRCUITS AND WAVEFORMS. TA = – 40°C to + 85°C.
2 Skew between any two outputs of the same package and switching in the same direction.
SWITCHING CHARACTERISTICS(1)
VCC = 2.5V ± 0.2V VCC = 2.7V VCC = 3.3V ± 0.3V
Symbol Parameter Min. Max. Min. Max. Min. Max. Unit
fMAX 150 — 150 — 150 — MHz
tPLH Propagation Delay 1 5.3 — 4.9 1 4.2 ns
tPHL xCLK to xQx
tPZH Output Enable Time 1 6.2 — 5.9 1 4.8 ns
tPZL xOE to xQx
tPHZ Output Disable Time 1 5.3 — 4.7 1.2 4.3 ns
tPLZ xOE to xQx
tSU Setup Time, data before CLK↑2.1 — 2.2 — 1.9 — ns
tHHold Time, data after CLK↑0.6 — 0.5 — 0.5 — ns
tWPulse Duration, CLK HIGH or LOW 3 .3 — 3.3 — 3.3 — ns
tSK(O) Output Skew(2) — ————500ps
NOTE:
1. VIH and VIL must be within the min. or max. range shown in the DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE table for the appropriate VCC range.
TA = – 40°C to + 85°C.
OUTPUT DRIVE CHARACTERISTICS
Symbol Parameter Test Conditions(1) Min. Max. Unit
VOH Output HIGH Voltage VCC = 2.3V to 3.6V IOH = – 0.1mA VCC – 0.2 — V
VCC = 2.3V IOH = – 6mA 2 —
VCC = 2.3V IOH = – 12mA 1 .7 —
VCC = 2.7V 2.2 —
VCC = 3V 2.4 —
VCC = 3V IOH = – 24mA 2 —
VOL Output LOW Voltage VCC = 2.3V to 3.6V IOL = 0.1mA — 0.2 V
VCC = 2.3V IOL = 6m A — 0.4
IOL = 12mA — 0.7
VCC = 2.7V IOL = 12mA — 0. 4
VCC = 3V IOL = 24mA — 0.55
INDUSTRIAL TEMPERATURE RANGE
6
IDT74ALVCH32374
3.3V CMOS 32-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP
Open
VLOAD
GND
VCC
Pulse
Generator D.U.T.
500Ω
500Ω
CL
RT
VIN VOUT
(1, 2)
ALVC Link
INPUT
VIH
0V
VOH
VOL
tPLH1
tSK
(x)
OUTPUT 1
OUTPUT 2
tPHL1
tSK
(x)
tPLH2 tPHL2
VT
VT
VOH
VT
VOL
tSK
(x)
= tPLH2
-
tPLH1
or
tPHL2
-
tPHL1
ALVC Link
SAME PHASE
INPUT TRANSITION
OPPOSITE PHASE
INPUT TRANSITION
0V
0V
VOH
V
OL
tPLH tPHL
tPHL
tPLH
OUTPUT
VIH
VT
VT
VIH
VT
ALVC Link
DATA
INPUT 0V
0V
0V
0V
tREM
TIMING
INPUT
SYNCHRONOUS
CONTROL
tSU tH
tSU tH
VIH
VT
VIH
VT
VIH
VT
VIH
VT
ALVC Link
ASYNCHRONOUS
CONTROL
LOW-HIGH-LOW
PULSE
HIGH-LOW-HIGH
PULSE
VT
tW
VT
ALVC Link
CONTROL
INPUT
tPLZ 0V
OUTPUT
NORMALLY
LOW t
PZH
0V
SWITCH
CLOSED
OUTPUT
NORMALLY
HIGH
ENABLE DISABLE
SWITCH
OPEN
tPHZ
0V
VLZ
VOH
V
T
VT
tPZL
VLOAD/2 VLOAD/2
VIH
VT
VOL
VHZ
ALVC Link
TEST CIRCUITS AND WAVEFORMS
Propagation Delay
Test Circuit for All Outputs
Enable and Disable Times
Set-up, Hold, and Release Times
NOTES:
1. For tSK(o) OUTPUT1 and OUTPUT2 are any two outputs.
2. For tSK(b) OUTPUT1 and OUTPUT2 are in the same bank.
DEFINITIONS:
CL = Load capacitance: includes jig and probe capacitance.
RT = Termination resistance: should be equal to ZOUT of the Pulse Generator.
NOTES:
1. Pulse Generator for All Pulses: Rate ≤ 1.0MHz; tF ≤ 2.5ns; tR ≤ 2.5ns.
2. Pulse Generator for All Pulses: Rate ≤ 1.0MHz; tF ≤ 2ns; tR ≤ 2ns.
Output Skew - tSK(X)
Pulse Width
NOTE:
1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH.
Symbol VCC(1)= 3.3V±0.3V VCC(1)= 2.7V VCC(2)= 2.5V±0.2V Unit
VLOAD 6 6 2 x Vcc V
VIH 2.7 2.7 Vcc V
VT1.5 1.5 Vcc / 2 V
VLZ 300 300 150 mV
VHZ 300 300 150 mV
CL50 50 30 pF
TEST CONDITIONS
SWITCH POSITION
Test Switch
Open Drain
Disable Low VLOAD
Enable Low
Disable High GND
Enable High
All Other Tests Open
INDUSTRIAL TEMPERATURE RANGE
IDT74ALVCH32374
3.3V CMOS 32-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP
7
ORDERING INFORMATION
XX ALVC XXXX XX
Package
Device Type
Temp. Range
BF
BFG
32
74
Low-Profile Fine Pitch Ball Grid Array
LFBGA - Green
32-Bit Edge Triggered D-Type Flip-Flop
with 3-State Outputs
-40°C to +85°C
XXX
Family
Bus-Hold
374
Bus-Hold
32-Bit Bus Density, ±24mA
H
CORPORATE HEADQUARTERS for SALES: for Tech Support:
6024 Silver Creek Valley Road 800-345-7015 or 408-284-8200 logichelp@idt.com
San Jose, CA 95138 fax: 408-284-2775
www.idt.com
