3 V, Voltage Monitoring
Microprocessor Supervisory Circuits
Data Sheet ADM706P/ADM706R/ADM706S/ADM706T, ADM708R/ADM708S/ADM708T
Rev. E Document Feedback
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FEATURES
Precision supply voltage monitor
2.63 V (ADM706P, ADM706R, ADM708R)
2.93 V (ADM706S, ADM708S)
3.08 V (ADM706T, ADM708T)
100 µA quiescent current
200 ms reset pulse width
Debounced manual reset input (MR)
Independent watchdog timer
1.6 sec timeout (ADM706P, ADM706R, ADM706S,
ADM706T)
Reset output
Active high (ADM706P)
Active low (ADM706R, ADM706S, ADM706T)
Both active high and active low (ADM708R, ADM708S,
ADM708T)
Voltage monitor for power fail or low battery warning
Guaranteed RESET valid with VCC = 1 V
Superior upgrade for MAX706P/R/S/T, MAX708R/S/T
APPLICATIONS
Microprocessor systems
Computers
Controllers
Intelligent instruments
Critical microprocessor monitoring
Battery operated systems
Portable instruments
FUNCTIONAL BLOCK DIAGRAMS
WATCHDOG
TRANSITION
DETECTOR
WATCHDOG
INPUT (WDI)
POWER-FAIL
INPUT (PFI) POWER-FAIL
OUTPUT (PFO)
WATCHDOG
OUTPUT (WDO)
RESET,
(P = RESET)
*VOLTAGE REFERENCE = 2.63V (P/R), 2.93V (S), 3.08V (T)
ADM706P/ADM706R/
ADM706S/ADM706T
RESET AND
WATCHDOG
TIMEBASE
RESET
GENERATOR
MR
VCC
70μA
VCC
WATCHDOG
TIMER
VREF*
1.25V
06435-001
Figure 1. ADM706P/ADM706R/ADM706S/ADM706T
1.25V
POWER-FAIL
INPUT (PFI)
RESET
* VOLTAGE REFERENCE = 2.63V (R), 2.93V (S), 3.08V (T)
RESET
GENERATOR
MR
V
CC
70μA
V
CC
RESET
06435-002
V
REF
*
POWER-FAIL
OUTPUT (PFO)
ADM708R/ADM708S/
ADM708T
Figure 2. ADM708R/ADM708S/ADM708T
GENERAL DESCRIPTION
The ADM706P/ADM706R/ADM706S/ADM706T and the
ADM708R/ADM708S/ADM708T microprocessor supervisory
circuits are suitable for monitoring either 3 V or 3.3 V power
supplies.
The ADM706P/ADM706R/ADM706S/ADM706T provide
power supply monitoring circuitry that generate a reset output
during power-up, power-down, and brownout conditions. The
reset output remains operational with VCC as low as 1 V.
Independent watchdog monitoring circuitry is also provided. This
activates if the watchdog input does not toggle within 1.6 sec.
In addition, there is a 1.25 V threshold detector for a power fail
warning, low battery detection, or to monitor an additional
power supply. An active low debounced MR input is also
included.
The ADM706R, ADM706S, and ADM706T are identical except
for the reset threshold monitor levels, which are 2.63 V, 2.93 V, and
3.08 V, respectively. The ADM706P is identical to the ADM706R
in that the reset threshold is 2.63 V. It differs only in that it has
an active high reset output.
The ADM708R/ADM708S/ADM708T provide similar functio-
nality as the ADM706R/ADM706S/ADM706T and only differ
in that a watchdog timer function is not available. Instead, an
active high reset output (RESET) is provided in addition to the
active low (RESET) output.
All devices are available in narrow 8-lead PDIP and 8-lead
SOIC packages.
ADM706P/ADM706R/ADM706S/ADM706T, ADM708R/ADM708S/ADM708T Data Sheet
Rev. E | Page 2 of 16
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
Functional Block Diagrams ............................................................. 1
General Description ......................................................................... 1
Revision History ............................................................................... 2
Specifications ..................................................................................... 3
Absolute Maximum Ratings ............................................................ 5
ESD Caution .................................................................................. 5
Pin Configurations and Function Descriptions ........................... 6
Typical Performance Characteristics ............................................. 8
Circuit Information ........................................................................ 10
Power Fail Reset .......................................................................... 10
Manual Reset ............................................................................... 10
Watchdog Timer (ADM706P/ADM706R/
ADM706S/ADM706T) .............................................................. 10
Power Fail Comparator .............................................................. 11
Adding Hysteresis to the Power Fail Comparator ................. 11
Va li d RESET Below 1 V VCC ..................................................... 11
Applications Information .............................................................. 12
Monitoring Additional Supply Levels ...................................... 12
Microprocessors with Bidirectional RESET ........................... 12
Outline Dimensions ....................................................................... 13
Ordering Guide .......................................................................... 14
REVISION HISTORY
1/16—Rev. D to Rev. E
Changes to Table 3 ............................................................................ 6
Changes to Table 4 ............................................................................ 7
Changes to Power Fail Comparator Section, Figure 17,
and Figure 18 ................................................................................... 10
Changes to Figure 20 and Figure 22 ............................................. 12
Changes to Ordering Guide .......................................................... 14
10/14—Rev. C to Rev. D
Changes to Pin 4 Description; Table 3 ........................................... 6
Changes to Pin 4 Description; Table 4 ........................................... 7
Changes to Ordering Guide .......................................................... 14
5/08—Rev. B to Rev. C
Changes to Applications Section ..................................................... 1
Changes to Table 2 ............................................................................. 5
Changes to Table 3 ............................................................................. 6
Changes to Figure 8 ........................................................................... 7
Changes to Figure 16 ......................................................................... 9
2/07—Rev. A to Rev. B
Updated Format .................................................................. Universal
Changes to Table 1 ............................................................................. 3
Updated Outline Dimensions ....................................................... 12
Changes to Ordering Guide .......................................................... 13
Data Sheet ADM706P/ADM706R/ADM706S/ADM706T, ADM708R/ADM708S/ADM708T
Rev. E | Page 3 of 16
SPECIFICATIONS
VCC = 2.70 V to 5.5 V (ADM706P/ADM706R/ADM708R), VCC = 3.00 V to 5.5 V (ADM70xS), VCC = 3.15 V to 5.5 V (ADM70xT), TA =
TMIN to TMAX unless otherwise noted.
Table 1.
Parameter Min Typ Max Unit Test Conditions/Comments
POWER SUPPLY
VCC Operating Voltage Range 1.0 5.5 V
Supply Current 100 200 μA VCC < 3.6 V
150 350 μA VCC < 5.5 V
LOGIC OUTPUT
Reset Threshold (VRST) 2.55 2.63 2.70 V ADM706P/ADM706R/ADM708R
2.85 2.93 3.00 V ADM706S/ADM708S
3.00 3.08 3.15 V ADM706T/ADM708T
Reset Threshold Hysteresis 20 mV
RESET PULSE WIDTH 160 200 280 ms ADM706P/ADM706R/ADM708R, VCC = 3 V
160 200 280 ms ADM706S/ADM708S/ADM706T/ADM708T,
VCC = 3.3 V
200 ms VCC = 5.0 V
RESET OUTPUT VOLTAGE (ADM706R/ADM708R/
ADM706S/ADM708S/ADM706T/ADM708T)
VOH 0.8 × VCC V VRST (max) < VCC < 3.6 V, ISOURCE = 500 μA
VOL 0.3 V VRST (max) < VCC < 3.6 V, ISINK = 1.2 mA
VOH VCC − 1.5 V V 4.5 V < VCC < 5.5 V, ISOURCE = 800 μA
VOL 0.4 V 4.5 V < VCC < 5.5 V, ISINK = 3.2 mA
V
OL
0.3
V
V
CC
= 1 V, I
SINK
= 100 μA
RESET OUTPUT VOLTAGE (ADM706P)
VOH VCC − 0.6 V V VRST (max) < VCC < 3.6 V, ISOURCE = 215 μA
VOL 0.3 V VRST (max) < VCC < 3.6 V, ISINK = 1.2 mA
VOH VCC − 1.5 V V 4.5 V < VCC < 5.5 V, ISOURCE = 800 μA
VOL 0.4 V 4.5 V < VCC < 5.5 V, ISINK = 3.2 mA
RESET OUTPUT VOLTAGE
(ADM708R/ADM708S/ADM708T)
VOH 0.8 × VCC V VRST (max) < VCC < 3.6 V, ISOURCE = 500 μA
VOL 0.3 V VRST (max) < VCC < 3.6 V, ISINK = 500 μA
VOH VCC − 1.5 V V 4.5 V < VCC < 5.5 V, ISOURCE = 800 μA
VOL 0.4 V 4.5 V < VCC < 5.5 V, ISINK = 1.2 mA
WATCHDOG INPUT (ADM706P/ADM706R/
ADM706S/ADM706T)
Watchdog Timeout Period
1.00
1.60
2.25
sec
ADM706P/ADM706R: V
CC
= 3 V;
ADM706S/ADM706T: VCC = 3.3 V;
VIL = 0.4 V, VIH = VCC × 0.8 V
WDI Pulse Width 100 ns VRST (max) < VCC < 3.6 V
50 ns 4.5 V < VCC < 5.5 V
WDI Input Threshold
VIL 0.6 V VRST (max) < VCC < 3.6 V
VIH 0.7 × VCC V VRST (max) < VCC < 3.6 V
VIL 0.8 V VCC = 5.0 V
VIH 3.5 V VCC = 5.0 V
WDI Input Current −1.0 +0.02 +1.0 μA WDI = 0 V or VCC
ADM706P/ADM706R/ADM706S/ADM706T, ADM708R/ADM708S/ADM708T Data Sheet
Rev. E | Page 4 of 16
Parameter Min Typ Max Unit Test Conditions/Comments
WDO OUTPUT VOLTAGE
VOH 0.8 × VCC V VRST (max) < VCC < 3.6 V, ISOURCE = 500 μA
VCC − 1.5 V V 4.5 V < VCC < 5.5 V, ISOURCE = 800 μA
VOL 0.3 V VRST (max) < VCC < 3.6 V, ISINK = 500 μA
0.4 V 4.5 V < VCC < 5.5 V, ISINK = 1.2 mA
MANUAL RESET INPUT
MR Pull-Up Current (MR = 0 V) 25 70 250 μA VRST (max) < VCC < 3.6 V
100
250
600
μA
4.5 V < V
CC
< 5.5 V
MR Pulse Width 500 ns VRST (max) < VCC < 3.6 V
150 ns 4.5 V < VCC < 5.5 V
MR
INPUT THRESHOLD
VIL 0.6 V VRST (max) < VCC < 3.6 V
VIH 0.7 × VCC V VRST (max) < VCC < 3.6 V
VIL 0.8 V 4.5 V < VCC < 5.5 V
VIH 2.0 V 4.5 V < VCC < 5.5 V
MR TO RESET OUTPUT DELAY 750 ns VRST (max) < VCC < 3.6 V
250 ns 4.5 V < VCC < 5.5 V
POWER FAIL INPUT
PFI Input Threshold 1.2 1.25 1.3 V ADM706P/ADM706R/ADM708R, VCC = 3 V
ADM706S/ADM708S/ADM706T/ADM708T,
V
CC
= 3.3 V, PFI falling
PFI Input Current
−25
+0.01
+25
nA
PFO OUTPUT VOLTAGE
VOH 0.8 × VCC V VRST (max) < VCC < 3.6 V, ISOURCE = 500 μA
V
OL
0.3
V
V
RST
(max) < V
CC
< 3.6 V, I
SINK
= 1.2 mA
VOH VCC − 1.5 V V 4.5 V < VCC < 5.5 V, ISOURCE = 800 μA
VOL 0.4 V 4.5 V < VCC < 5.5 V, ISINK = 3.2 mA
Data Sheet ADM706P/ADM706R/ADM706S/ADM706T, ADM708R/ADM708S/ADM708T
Rev. E | Page 5 of 16
ABSOLUTE MAXIMUM RATINGS
TA = 25°C unless otherwise noted.
Table 2.
Parameter Rating
VCC −0.3 V to +6 V
All Other Inputs −0.3 V to VCC + 0.3 V
Input Current
VCC 20 mA
GND 20 mA
Digital Output Current 20 mA
Power Dissipation, N-8 (PDIP)
727 mW
θJA Thermal Impedance 135°C/W
Power Dissipation, R-8 (SOIC) 470 mW
θJA Thermal Impedance 110°C/W
Operating Temperature Range
Industrial (Version A) −40°C to +85°C
Lead Temperature (Soldering, 10 sec) 300°C
Vapor Phase (60 sec) 215°C
Infrared (15 sec) 220°C
Storage Temperature Range −65°C to +150°C
ESD Rating >4.5 kV
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
ESD CAUTION
ADM706P/ADM706R/ADM706S/ADM706T, ADM708R/ADM708S/ADM708T Data Sheet
Rev. E | Page 6 of 16
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
RESET
ADM706P
TOP VIEW
(Not to Scale)
1
2
3
45
8
7
6
06435-003
MR
PFO
WDI
WDO
VCC
GND
PFI
Figure 3. ADM706P
RESET
TOP VIEW
(Not to Scale)
1
2
3
45
8
7
6
06435-004
MR
PFO
WDI
V
CC
GND
PFI
WDO
ADM706R/
ADM706S/
ADM706T
Figure 4. ADM706R/ADM706S/ADM706T
Table 3. Pin Function Descriptions ADM706P/ADM706R/ADM706S/ADM706T
Pin No. Mnemonic Description
1 MR Manual Reset Input. When taken below 0.6 V, a RESET/RESET is generated. MR can be driven
from TTL, CMOS logic, or from a manual reset switch because it is internally debounced. An
internal 70 μA pull-up current holds the input high when floating.
2 VCC Power Supply Input. Place a 0.1 µF decoupling capacitor between the VCC and GND pins.
3 GND Ground. Ground reference for all signals (0 V).
4 PFI Power Fail Input. PFI is the noninverting input to the power fail comparator. When PFI is less
than 1.25 V, PFO goes low. If unused, PFI connects to GND.
5 PFO Power Fail Output. PFO is the output from the power fail comparator. It goes low when PFI is
less than 1.25 V.
6 WDI Watchdog Input. If WDI remains either high or low for longer than the watchdog timeout period, the
watchdog output, WDO, goes low. The timer resets with each transition at the WDI input. Either
a high to low or a low to high transition clears the counter. The internal timer is also cleared
whenever reset is asserted.
7 (ADM706R/ADM706S/
ADM706T Only)
RESET Logic Output. RESET goes low for 200 ms when triggered. It is triggered either by VCC being
below the reset threshold or by a low signal on the MR input. RESET remains low whenever VCC
is below the reset threshold. It remains low for 200 ms after VCC goes above the reset threshold
or MR goes from low to high. A watchdog timeout does not trigger RESET unless WDO is
connected to MR.
7 (ADM706P Only)
RESET
Logic Output. RESET is an active high output suitable for systems that use active high reset logic. It is
the inverse of RESET.
8 WDO Watchdog Output. WDO goes low if the internal watchdog timer times out as a result of inactivity on
the WDI input. It remains low until the watchdog timer is cleared. WDO also goes low during
low line conditions. Whenever VCC is below the reset threshold, WDO remains low. As soon as VCC
goes above the reset threshold, WDO goes high immediately.
Data Sheet ADM706P/ADM706R/ADM706S/ADM706T, ADM708R/ADM708S/ADM708T
Rev. E | Page 7 of 16
RESET
TOP VIEW
(Not to Scale)
1
2
3
45
8
7
6
06435-005
MR
PFO
NC
V
CC
GND
PFI
NC = NO CONNECT
RESET
ADM708R/
ADM708S/
ADM708T
Figure 5. ADM708R/ADM708S/ADM708T
Table 4. Pin Function Descriptions ADM708R/ADM708S/ADM708T
Pin No. Mnemonic Description
1 MR Manual Reset Input. When taken below 0.6 V, a RESET/RESET is generated. MR can be driven from TTL, CMOS
logic, or from a manual reset switch because it is internally debounced. An internal 70 μA pull-up current holds
the input high when floating.
2 VCC Power Supply Input. Place a 0.1 µF decoupling capacitor between the VCC and GND pins.
3 GND Ground. Ground reference for all signals (0 V).
4
PFI
Power Fail Input. PFI is the noninverting input to the power fail comparator. When PFI is less than 1.25 V,
PFO
goes low. If unused, PFI must connect to GND.
5 PFO Power Fail Output. PFO is the output from the power fail comparator. It goes low when PFI is less than 1.25 V.
6 NC No Connect.
7 RESET Logic Output. RESET goes low for 200 ms when triggered. It is triggered either by VCC being below the reset
threshold or by a low signal on the MR input. RESET remains low whenever VCC is below the reset threshold. It
remains low for 200 ms after VCC goes above the reset threshold or MR goes from low to high. A watchdog
timeout does not trigger RESET unless WDO is connected to MR.
8 RESET Logic Output. RESET is an active high output suitable for systems that use active high reset logic. It is the
inverse of RESET.
ADM706P/ADM706R/ADM706S/ADM706T, ADM708R/ADM708S/ADM708T Data Sheet
Rev. E | Page 8 of 16
TYPICAL PERFORMANCE CHARACTERISTICS
06435-013
RESET
V
CC
400ms/DIV
Figure 6. ADM706R/ADM706S/ADM706T and the
ADM708R/ADM708S/ADM708T RESET Output Voltage vs. Supply Voltage
06435-014
RESET
VCC
400ms/DIV
Figure 7. RESET Output Voltage vs. Supply Voltage
06435-015
3V
1.2V
0V
1.3V
PFI
500ns/DIV
V
CC
= 3.3V
T
A
= 25°C
PFO
Figure 8. PFI Assertion Response Time
06435-016
0V
1.3V
PFI
3V
1.2V
500ns/DIV
V
CC
= 3.3V
T
A
= 25°C
PFO
Figure 9. PFI Deassertion Response Time
06435-017
0V 0V
3V3V
100ns/DIV
V
CC
= V
RT
T
A
= 25°C
RESETRESET
Figure 10. RESET, RESET Assertion
06435-018
0V 0V
3V3V
100ns/DIV
V
CC
= V
RT
T
A
= 25°C
RESET RESET
Figure 11. RESET, RESET Deassertion
ADM706P/ADM706R/ADM706S/ADM706T, ADM708R/ADM708S/ADM708T Data Sheet
Rev. E | Page 10 of 16
CIRCUIT INFORMATION
WATCHDOG
TRANSITION
DETECTOR
WATCHDOG
INPUT (WDI)
POWER-FAIL
INPUT (PFI) POWER-FAIL
OUTPUT (PFO)
WATCHDOG
OUTPUT (WDO)
RESET,
(P = RESET)
*VOLTAGE REFERENCE = 2.63V (P/R), 2.93V (S), 3.08V (T)
RESET AND
WATCHDOG
TIMEBASE
RESET
GENERATOR
MR
V
CC
70μA
V
CC
WATCHDOG
TIMER
V
REF
*
1.25V
06435-006
ADM706P/ADM706R/
ADM706S/ADM706T
Figure 13. ADM706P/ADM706R/ADM706S/ADM706T Functional Block
Diagram
1.25V
POWER-FAIL
INPUT (PFI)
RESET
* VOLTAGE REFERENCE = 2.63V (R), 2.93V (S), 3.08V (T)
RESET
GENERATOR
MR
V
CC
70μA
V
CC
RESET
06435-007
V
REF
*
POWER-FAIL
OUTPUT (PFO)
ADM708R/ADM708S/
ADM708T
Figure 14. ADM708R/ADM708S/ADM708T Functional Block Diagram
POWER FAIL RESET
The reset output provides a reset (RESET or RESET) output
signal to the microprocessor whenever the VCC input is below
the reset threshold. The actual reset threshold voltage is dependent
on whether a P, R, S, or T suffix device is used. An internal timer
holds the reset output active for 200 ms after the voltage on VCC
rises above the threshold. This is intended as a power-on reset
signal for the microprocessor. It allows time for both the power
supply and the microprocessor to stabilize after power-up. If a
power supply brownout or interruption occurs, the reset line is
similarly activated and remains active for 200 ms after the supply
recovers. If another interruption occurs during an active reset
period, the reset timeout period continues for an additional 200 ms.
The reset output is guaranteed to remain valid with VCC as low
as 1 V. This ensures that the microprocessor is held in a stable
shutdown condition as the power supply starts up.
The ADM706P provides an active high RESET signal; the
ADM706R/ADM706S/ADM706T provide an active low RESET
signal; and the ADM708R/ADM706S/ADM706T provide both
RESET and RESET.
MANUAL RESET
The MR input allows other reset sources, such as a manual reset
switch, to generate a processor reset. The input is effectively
debounced by the timeout period (200 ms typical). The MR
input is TTL-/CMOS-compatible; it can also be driven by any
logic reset output. If unused, the MR input can be tied high or
left floating.
V
CC
RESET
MR
WDO
V
RT
MR EXTERNALLY
DRIVEN LOW
06435-008
V
RT
tRS tRS
NOTES
RESET = COMPLEMENT OF RESET
Figure 15. RESET, MR, and WDO Timing
WATCHDOG TIMER (ADM706P/ADM706R/
ADM706S/ADM706T)
The watchdog timer circuit monitors the activity of the
microprocessor to check that it is not stalled in an indefinite loop.
An output line on the processor is used to toggle the watchdog
input (WDI) line. If this line is not toggled within the timeout
period (1.6 sec), the watchdog output (WDO) is driven low. The
WDO output is connected to a nonmaskable interrupt (NMI) on
the processor. Therefore, if the watchdog timer times out, an
interrupt is generated. The interrupt service routine is used to
rectify the problem.
The watchdog timer is cleared either by a high to low or by a
low to high transition on WDI. Pulses as narrow as 50 ns are
detected. The timer is also cleared by RESET/RESET going
active. Therefore, the watchdog timeout period begins after
reset goes inactive.
When VCC falls below the reset threshold, WDO is forced low
whether or not the watchdog timer has timed out. Normally,
this generates an interrupt, but it is overridden by RESET/RESET
going active.
t
WP
WDI
WDO
RESET
t
RS
RESET EXTERNALLY
TRIGGERED BY MR
t
WD
t
WD tWD
06435-009
Figure 16. Watchdog Timing
Data Sheet ADM706P/ADM706R/ADM706S/ADM706T, ADM708R/ADM708S/ADM708T
Rev. E | Page 11 of 16
POWER FAIL COMPARATOR
The power fail comparator is an independent comparator that
monitors the input power supply. The inverting input of the
comparator internally connects to a 1.25 V reference voltage.
The noninverting input is available at the PFI input. This input
monitors the input power supply via a resistive divider network.
When the voltage on the PFI input drops below 1.25 V, the
comparator output (PFO) goes low, indicating a power failure.
For early warning of power failure, the comparator monitors the
preregulator input by choosing an appropriate resistive divider
network. The PFO output interrupts the processor to implement a
shutdown procedure before the power is lost.
As the voltage on the PFI pin is limited to VCC + 0.3 V, i t i s
recommended to connect the PFI pin with a Schottky diode to
the RESET pin, as shown in Figure 17. This helps with clamping
the PFI pin voltage during device power up and operation.
RESET
OUTPUT
RESET
INPUT
POWER
R1
R2
POWER-FAIL
INPUT
1.25V
PFI
PFO POWER-FAIL
OUTPUT
06435-010
ADM706R/ADM706S/
ADM706T/ADM708R/
ADM708S/ADM708T
Figure 17. Power Fail Comparator
ADDING HYSTERESIS TO THE POWER FAIL
COMPARATOR
For increased noise immunity, hysteresis can be added to the
power fail comparator. Because the comparator circuit is non-
inverting, hysteresis is added simply by connecting a resistor
between the PFO output and the PFI input as shown in Figure 18.
When PFO is low, Resistor R3 sinks current from the summing
junction at the PFI pin. When PFO is high, Resistor R3 sources
current into the PFI summing junction. This results in differing
trip levels for the comparator. Further noise immunity is achieved
by connecting a capacitor between PFI and GND.
06435-011
INPUT
POWER
TO µP NMI
R3
3.3V
VCC
R1
R2
1.25V
PFI
PFO
ADM663A
3.3V
0V 0V VL
VIN
VH
–
+
PFO
ADM706R/ADM706S/
ADM706T/ADM708R/
ADM708S/ADM708T
TO µP RESET
RESET
Figure 18. Adding Hysteresis to the Power Fail Comparator
×
+
+= R1
R3R2
R3R2
V
H
125.1
−
−+=
R3
V
R2
R1V
CC
L
25.1
25.1
25.1
+
=
R2
R2
R1
VMID 25.1
VALID RESET BELOW 1 V VCC
The ADM706R/ADM706S/ADM706T, ADM708R/ADM708S/
ADM708T are guaranteed to provide a valid reset level with VCC
as low as 1 V. Refer to the Typical Performance Characteristics
section. As VCC drops below 1 V, the internal transistor does not
have sufficient drive to hold it on so the voltage on RESET is no
longer held at 0 V. A pull-down resistor, as shown in Figure 19, can
connect externally to hold the line low if it is required.
GND
RESET
R1
06435-012
ADM706R/ADM706S/
ADM706T/ADM708R/
ADM708S/ADM708T
Figure 19. RESET Valid Below 1 V
ADM706P/ADM706R/ADM706S/ADM706T, ADM708R/ADM708S/ADM708T Data Sheet
Rev. E | Page 12 of 16
APPLICATIONS INFORMATION
A typical operating circuit is shown in Figure 20. The unregulated
dc input supply is monitored using the PFI input via the resistive
divider network. Resistor R1 and Resistor R2 are to be selected
so that when the supply voltage drops below the desired level
(for example, 5 V), the voltage on PFI drops below the 1.25 V
threshold, thereby generating an interrupt to the microprocessor.
Monitoring the preregulator input gives additional time to execute
an orderly shutdown procedure before power is lost.
06435-020
RESET
GND
MR
PFI
WDI
PFO
RESET
V
CC
3.3V
WDO
V
CC
I/O LINE
INTERRUPT
NMI
MANUAL
RESET
GND
GND
IN OUT
ADM666A
MICROPROCESSOR
ADM706R/
ADM706S/
ADM706T
UNREGULATED
DC
Figure 20. Typical Application Circuit
Microprocessor activity is monitored using the WDI input. This
is driven using an output line from the processor. The software
routines toggle this line at least once every 1.6 sec. If a problem
occurs and this line is not toggled, WDO goes low and a nonmask-
able interrupt is generated. This interrupt routine is to be used
to clear the problem.
If, in the event of inactivity on the WDI line, a system reset is
required, the WDO output is to be connected to the input as
shown in Figure 21.
0
6435-021
RESET
GND
I/O LINE
MR
PFI WDI
WDO
RESET
MICROPROCESSOR
ADM706R/
ADM706S/
ADM706T
Figure 21. RESET from WDO
MONITORING ADDITIONAL SUPPLY LEVELS
It is possible to use the power fail comparator to monitor a second
supply as shown in Figure 22. The two sensing resistors, R1 and
R2, are selected such that the voltage on PFI drops below 1.25 V at
the minimum acceptable input supply. The PFO output can
connect to the MR input so a reset generates when the supply drops
out of tolerance. In this case, if either supply drops out of tolerance,
a reset is generated.
06435-022
RESET
GND
MR
PFI
WDI
PFO
RESET
V
CC
R1
R2
V
X
+3V/+3.3V
ADM706R/
ADM706S/
ADM706T
MICROPROCESSOR
Figure 22. Monitoring 3 V/3.3 V and an Additional Supply, VX
MICROPROCESSORS WITH BIDIRECTIONAL RESET
To prevent contention for microprocessors with a bidirectional
reset line, a current limiting resistor is to be inserted between
the ADM706R/ADM706S/ADM706T, ADM708R/ADM708S/
ADM708T RESET output pin and the microprocessor reset pin.
This limits the current to a safe level if there are conflicting output
reset levels. A suitable resistor value is 4.7 kΩ. If the reset output is
required for other uses, it must be buffered as shown in Figure 23.
06435-023
RESET
GND
RESET
GND
BUFFERED
RESET
+3V/+3.3V
V
CC
ADM706R/ADM706S/
ADM706T/ADM708R/
ADM708S/ADM708T
MICROPROCESSOR
Figure 23. Bidirectional Input/Output RESET
Data Sheet ADM706P/ADM706R/ADM706S/ADM706T, ADM708R/ADM708S/ADM708T
Rev. E | Page 13 of 16
OUTLINE DIMENSIONS
COMPLIANT TO JEDEC STANDARDS MS-001
CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
CORNER LEADS MAY BE CONFIGURED AS WHOLE OR HALF LEADS.
070606-A
0.022 (0.56)
0.018 (0.46)
0.014 (0.36)
SEATING
PLANE
0.015
(0.38)
MIN
0.210 (5.33)
MAX
0.150 (3.81)
0.130 (3.30)
0.115 (2.92)
0.070 (1.78)
0.060 (1.52)
0.045 (1.14)
8
14
5
0.280 (7.11)
0.250 (6.35)
0.240 (6.10)
0.100 (2.54)
BSC
0.400 (10.16)
0.365 (9.27)
0.355 (9.02)
0.060 (1.52)
MAX
0.430 (10.92)
MAX
0.014 (0.36)
0.010 (0.25)
0.008 (0.20)
0.325 (8.26)
0.310 (7.87)
0.300 (7.62)
0.195 (4.95)
0.130 (3.30)
0.115 (2.92)
0.015 (0.38)
GAUGE
PLANE
0.005 (0.13)
MIN
Figure 24. 8-Lead Plastic Dual In-Line Package [PDIP]
Narrow Body
(N-8)
Dimension shown in inches and (millimeters)
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
COMPLIANT TO JEDEC STANDARDS MS-012-AA
012407-A
0.25 (0.0098)
0.17 (0.0067)
1.27 (0.0500)
0.40 (0.0157)
0.50 (0.0196)
0.25 (0.0099) 45°
8°
0°
1.75 (0.0688)
1.35 (0.0532)
SEATING
PLANE
0.25 (0.0098)
0.10 (0.0040)
4
1
8 5
5.00 (0.1968)
4.80 (0.1890)
4.00 (0.1574)
3.80 (0.1497)
1.27 (0.0500)
BSC
6.20 (0.2441)
5.80 (0.2284)
0.51 (0.0201)
0.31 (0.0122)
COPLANARITY
0.10
Figure 25. 8-Lead Standard Small Outline Package [SOIC_N]
Narrow Body
(R-8)
Dimensions shown in millimeters and (inches)
ADM706P/ADM706R/ADM706S/ADM706T, ADM708R/ADM708S/ADM708T Data Sheet
Rev. E | Page 14 of 16
ORDERING GUIDE
Model
1
Temperature Range
Package Description
Package Option
ADM706PANZ −40°C to +85°C 8-Lead Plastic Dual In-Line Package [PDIP] N-8
ADM706PARZ −40°C to +85°C 8-Lead Small Outline Package [SOIC_N] R-8
ADM706PARZ-REEL −40°C to +85°C 8-Lead Small Outline Package [SOIC_N] R-8
ADM706RANZ −40°C to +85°C 8-Lead Plastic Dual In-Line Package [PDIP] N-8
ADM706RAR −40°C to +85°C 8-Lead Small Outline Package [SOIC_N] R-8
ADM706RARZ −40°C to +85°C 8-Lead Small Outline Package [SOIC_N] R-8
ADM706RARZ-REEL −40°C to +85°C 8-Lead Small Outline Package [SOIC_N] R-8
ADM706RARZ-REEL7 −40°C to +85°C 8-Lead Small Outline Package [SOIC_N] R-8
ADM706SANZ −40°C to +85°C 8-Lead Plastic Dual In-Line Package [PDIP] N-8
ADM706SAR −40°C to +85°C 8-Lead Small Outline Package [SOIC_N] R-8
ADM706SAR-REEL −40°C to +85°C 8-Lead Small Outline Package [SOIC_N] R-8
ADM706SARZ −40°C to +85°C 8-Lead Small Outline Package [SOIC_N] R-8
ADM706SARZ-REEL
−40°C to +85°C
8-Lead Small Outline Package [SOIC_N]
R-8
ADM706TANZ −40°C to +85°C 8-Lead Plastic Dual In-Line Package [PDIP] N-8
ADM706TAR −40°C to +85°C 8-Lead Small Outline Package [SOIC_N] R-8
ADM706TAR-REEL −40°C to +85°C 8-Lead Small Outline Package [SOIC_N] R-8
ADM706TARZ −40°C to +85°C 8-Lead Small Outline Package [SOIC_N] R-8
ADM706TARZ-REEL −40°C to +85°C 8-Lead Small Outline Package [SOIC_N] R-8
ADM708RANZ −40°C to +85°C 8-Lead Plastic Dual In-Line Package [PDIP] N-8
ADM708RAR −40°C to +85°C 8-Lead Small Outline Package [SOIC_N] R-8
ADM708RAR-REEL −40°C to +85°C 8-Lead Small Outline Package [SOIC_N] R-8
ADM708RARZ −40°C to +85°C 8-Lead Small Outline Package [SOIC_N] R-8
ADM708RARZ-REEL −40°C to +85°C 8-Lead Small Outline Package [SOIC_N] R-8
ADM708SANZ −40°C to +85°C 8-Lead Plastic Dual In-Line Package [PDIP] N-8
ADM708SAR −40°C to +85°C 8-Lead Small Outline Package [SOIC_N] R-8
ADM708SAR-REEL −40°C to +85°C 8-Lead Small Outline Package [SOIC_N] R-8
ADM708SARZ
−40°C to +85°C
8-Lead Small Outline Package [SOIC_N]
R-8
ADM708SARZ-REEL −40°C to +85°C 8-Lead Small Outline Package [SOIC_N] R-8
ADM708TANZ −40°C to +85°C 8-Lead Plastic Dual In-Line Package [PDIP] N-8
ADM708TAR −40°C to +85°C 8-Lead Small Outline Package [SOIC_N] R-8
ADM708TARZ −40°C to +85°C 8-Lead Small Outline Package [SOIC_N] R-8
ADM708TARZ-REEL −40°C to +85°C 8-Lead Small Outline Package [SOIC_N] R-8
1 Z = RoHS Compliant Part.
Data Sheet ADM706P/ADM706R/ADM706S/ADM706T, ADM708R/ADM708S/ADM708T
Rev. E | Page 15 of 16
NOTES
